The GNU MP Library is free software; you can redistribute it and/or modify it under the terms of either:
* the GNU Lesser General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
or
* the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
or both in parallel, as here.
The GNU MP Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received copies of the GNU General Public License and the GNU Lesser General Public License along with the GNU MP Library. If not,
see https://www.gnu.org/licenses/. */
/* You have to define the following before including this file:
UWtype -- An unsigned type, default type for operations (typically a "word") UHWtype -- An unsigned type, at least half the size of UWtype UDWtype -- An unsigned type, at least twice as large a UWtype W_TYPE_SIZE -- size in bits of UWtype
SItype, USItype -- Signed and unsigned 32 bit types DItype, UDItype -- Signed and unsigned 64 bit types
On a 32 bit machine UWtype should typically be USItype; on a 64 bit machine, UWtype should typically be UDItype.
Optionally, define:
LONGLONG_STANDALONE -- Avoid code that needs machine-dependent support files NO_ASM -- Disable inline asm
CAUTION! Using this version of longlong.h outside of GMP is not safe. You need to include gmp.h and gmp-impl.h, or certain things might not work as expected.
*/
/* This is used to make sure no undesirable sharing between different libraries
that use this file takes place. */ #ifndef __MPN #define __MPN(x) __##x #endif
/* Define auxiliary asm macros.
1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype word product in HIGH_PROD and LOW_PROD.
2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a UDWtype product. This is just a variant of umul_ppmm.
3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, denominator) divides a UDWtype, composed by the UWtype integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less than DENOMINATOR for correct operation. If, in addition, the most significant bit of DENOMINATOR must be 1, then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, denominator). Like udiv_qrnnd but the numbers are signed. The quotient is rounded towards 0.
5) count_leading_zeros(count, x) counts the number of zero-bits from the msb to the first non-zero bit in the UWtype X. This is the number of steps X needs to be shifted left to set the msb. Undefined for X == 0, unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
6) count_trailing_zeros(count, x) like count_leading_zeros, but counts from the least significant end.
7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, high_addend_2, low_addend_2) adds two UWtype integers, composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is lost.
8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend, high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers, composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, and is lost.
If any of these macros are left undefined for a particular CPU, C macros are used.
Notes:
For add_ssaaaa the two high and two low addends can both commute, but unfortunately gcc only supports one "%" commutative in each asm block. This has always been so but is only documented in recent versions (eg. pre-release 3.3). Having two or more "%"s can cause an internal compiler error in certain rare circumstances.
Apparently it was only the last "%" that was ever actually respected, so the code has been updated to leave just that. Clearly there's a free choice whether high or low should get it, if there's a reason to favour one over the other. Also obviously when the constraints on the two operands are identical there's no benefit to the reloader in any "%" at all.
*/
/* The CPUs come in alphabetical order below.
Please add support for more CPUs here, or improve the current support
for the CPUs below! */
/* count_leading_zeros_gcc_clz is count_leading_zeros implemented with gcc 3.4 __builtin_clzl or __builtin_clzll, according to our limb size. Similarly count_trailing_zeros_gcc_ctz using __builtin_ctzl or __builtin_ctzll.
These builtins are only used when we check what code comes out, on some chips they're merely libgcc calls, where we will instead want an inline in that case (either asm or generic C).
These builtins are better than an asm block of the same insn, since an asm block doesn't give gcc any information about scheduling or resource usage. We keep an asm block for use on prior versions of gcc though.
For reference, __builtin_ffs existed in gcc prior to __builtin_clz, but it's not used (for count_leading_zeros) because it generally gives extra code to ensure the result is 0 when the input is 0, which we don't need
or want. */
/* clz_tab is required in all configurations, since mpn/alpha/cntlz.asm
always goes into libgmp.so, even when not actually used. */ #define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
#if ! defined (count_leading_zeros) \
&& defined (__GNUC__) && ! defined (LONGLONG_STANDALONE) /* ALPHA_CMPBGE_0 gives "cmpbge $31,src,dst", ie. test src bytes == 0. "$31" is written explicitly in the asm, since an "r" constraint won't select reg 31. There seems no need to worry about "r31" syntax for cray,
since gcc itself (pre-release 3.4) emits just $31 in various places. */ #define ALPHA_CMPBGE_0(dst, src) \ do { asm ("cmpbge $31, %1, %0" : "=r" (dst) : "r" (src)); } while (0) /* Zero bytes are turned into bits with cmpbge, a __clz_tab lookup counts them, locating the highest non-zero byte. A second __clz_tab lookup
counts the leading zero bits in that byte, giving the result. */ #define count_leading_zeros(count, x) \ do { \
UWtype __clz__b, __clz__c, __clz__x = (x); \
ALPHA_CMPBGE_0 (__clz__b, __clz__x); /* zero bytes */ \
__clz__b = __clz_tab [(__clz__b >> 1) ^ 0x7F]; /* 8 to 1 byte */ \
__clz__b = __clz__b * 8 - 7; /* 57 to 1 shift */ \
__clz__x >>= __clz__b; \
__clz__c = __clz_tab [__clz__x]; /* 8 to 1 bit */ \
__clz__b = 65 - __clz__b; \
(count) = __clz__b - __clz__c; \
} while (0) #define COUNT_LEADING_ZEROS_NEED_CLZ_TAB #endif/* clz using cmpbge */
#if ! defined (count_leading_zeros) && ! defined (LONGLONG_STANDALONE) #if HAVE_ATTRIBUTE_CONST long __MPN(count_leading_zeros) (UDItype) __attribute__ ((const)); #else long __MPN(count_leading_zeros) (UDItype); #endif #define count_leading_zeros(count, x) \
((count) = __MPN(count_leading_zeros) (x)) #endif/* clz using mpn */ #endif/* __alpha */
#ifdefined (__ia64) && W_TYPE_SIZE == 64 /* This form encourages gcc (pre-release 3.4 at least) to emit predicated "sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
register, which takes an extra cycle. */ #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ do { \
UWtype __x; \
__x = (al) - (bl); \ if ((al) < (bl)) \
(sh) = (ah) - (bh) - 1; \ else \
(sh) = (ah) - (bh); \
(sl) = __x; \
} while (0) #ifdefined (__GNUC__) && ! defined (__INTEL_COMPILER) /* Do both product parts in assembly, since that gives better code with all gcc versions. Some callers will just use the upper part, and in
that situation we waste an instruction, but not any cycles. */ #define umul_ppmm(ph, pl, m0, m1) \
__asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
: "=&f" (ph), "=f" (pl) \
: "f" (m0), "f" (m1)) #define count_leading_zeros(count, x) \ do { \
UWtype _x = (x), _y, _a, _c; \
__asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
__asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
_c = (_a - 1) << 3; \
_x >>= _c; \ if (_x >= 1 << 4) \
_x >>= 4, _c += 4; \ if (_x >= 1 << 2) \
_x >>= 2, _c += 2; \
_c += _x >> 1; \
(count) = W_TYPE_SIZE - 1 - _c; \
} while (0) /* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
based, and we don't need a special case for x==0 here */ #define count_trailing_zeros(count, x) \ do { \
UWtype __ctz_x = (x); \
__asm__ ("popcnt %0 = %1" \
: "=r" (count) \
: "r" ((__ctz_x-1) & ~__ctz_x)); \
} while (0) #endif #ifdefined (__INTEL_COMPILER) #include <ia64intrin.h> #define umul_ppmm(ph, pl, m0, m1) \ do { \
UWtype __m0 = (m0), __m1 = (m1); \
ph = _m64_xmahu (__m0, __m1, 0); \
pl = __m0 * __m1; \
} while (0) #endif #ifndef LONGLONG_STANDALONE #define udiv_qrnnd(q, r, n1, n0, d) \ do { UWtype __di; \
__di = __MPN(invert_limb) (d); \
udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
} while (0) #define UDIV_PREINV_ALWAYS 1 #define UDIV_NEEDS_NORMALIZATION 1 #endif #endif
#ifdefined (__GNUC__)
/* We sometimes need to clobber "cc" with gcc2, but that would not be
understood by gcc1. Use cpp to avoid major code duplication. */ #if __GNUC__ < 2 #define __CLOBBER_CC #define __AND_CLOBBER_CC #else/* __GNUC__ >= 2 */ #define __CLOBBER_CC : "cc" #define __AND_CLOBBER_CC , "cc" #endif/* __GNUC__ < 2 */
/* These macros are for ABI=2.0w. In ABI=2.0n they can't be used, since GCC (3.2) puts longlong into two adjacent 32-bit registers. Presumably this
is just a case of no direct support for 2.0n but treating it like 1.0. */ #ifdefined (__hppa) && W_TYPE_SIZE == 64 && ! defined (_LONG_LONG_LIMB) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%I5 %5,%r4,%1\n\tadd,dc %r2,%r3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rM" (ah), "rM" (bh), "%rM" (al), "rI" (bl)) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%I4 %4,%r5,%1\n\tsub,db %r2,%r3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rM" (ah), "rM" (bh), "rI" (al), "rM" (bl)) #endif/* hppa */
#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32 #ifdefined (__zarch__) || defined (HAVE_HOST_CPU_s390_zarch) #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ do { \ /* if (__builtin_constant_p (bl)) \ __asm__ ("alfi\t%1,%o5\n\talcr\t%0,%3" \ : "=r" (sh), "=&r" (sl) \ : "0" (ah), "r" (bh), "%1" (al), "n" (bl) __CLOBBER_CC);\ else \
*/
: "=r" (sh), "=&r" (sl) \
: "0" (ah), "r" (bh), "%1" (al), "r" (bl)__CLOBBER_CC); \
} while (0) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ do { \ /* if (__builtin_constant_p (bl)) \ __asm__ ("slfi\t%1,%o5\n\tslbr\t%0,%3" \ : "=r" (sh), "=&r" (sl) \ : "0" (ah), "r" (bh), "1" (al), "n" (bl) __CLOBBER_CC); \ else \
*/
: "=r" (sh), "=&r" (sl) \
: "0" (ah), "r" (bh), "1" (al), "r" (bl) __CLOBBER_CC); \
} while (0) #if __GMP_GNUC_PREREQ (4,5) #define umul_ppmm(xh, xl, m0, m1) \ do { \ union {UDItype __ll; \ struct {USItype __h, __l;} __i; \
} __x; \
__x.__ll = (UDItype) (m0) * (UDItype) (m1); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0) #else #if 0 /* FIXME: this fails if gcc knows about the 64-bit registers. Use only
with a new enough processor pretending we have 32-bit registers. */ #define umul_ppmm(xh, xl, m0, m1) \ do { \ union {UDItype __ll; \ struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("mlr\t%0,%2" \
: "=r" (__x.__ll) \
: "%0" (m0), "r" (m1)); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0) #else #define umul_ppmm(xh, xl, m0, m1) \ do { \ /* When we have 64-bit regs and gcc is aware of that, we cannot simply use DImode for the product, since that would be allocated to a single 64-bit register, whereas mlr uses the low 32-bits of an even-odd register pair.
*/ register USItype __r0 __asm__ ("0"); \ register USItype __r1 __asm__ ("1") = (m0); \
__asm__ ("mlr\t%0,%3" \
: "=r" (__r0), "=r" (__r1) \
: "r" (__r1), "r" (m1)); \
(xh) = __r0; (xl) = __r1; \
} while (0) #endif/* if 0 */ #endif #if 0 /* FIXME: this fails if gcc knows about the 64-bit registers. Use only
with a new enough processor pretending we have 32-bit registers. */ #define udiv_qrnnd(q, r, n1, n0, d) \ do { \ union {UDItype __ll; \ struct {USItype __h, __l;} __i; \
} __x; \
__x.__i.__h = n1; __x.__i.__l = n0; \
__asm__ ("dlr\t%0,%2" \
: "=r" (__x.__ll) \
: "0" (__x.__ll), "r" (d)); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0) #else #define udiv_qrnnd(q, r, n1, n0, d) \ do { \ register USItype __r0 __asm__ ("0") = (n1); \ register USItype __r1 __asm__ ("1") = (n0); \
__asm__ ("dlr\t%0,%4" \
: "=r" (__r0), "=r" (__r1) \
: "r" (__r0), "r" (__r1), "r" (d)); \
(q) = __r1; (r) = __r0; \
} while (0) #endif/* if 0 */ #else/* if __zarch__ */ /* FIXME: this fails if gcc knows about the 64-bit registers. */ #define smul_ppmm(xh, xl, m0, m1) \ do { \ union {DItype __ll; \ struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("mr\t%0,%2" \
: "=r" (__x.__ll) \
: "%0" (m0), "r" (m1)); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0) /* FIXME: this fails if gcc knows about the 64-bit registers. */ #define sdiv_qrnnd(q, r, n1, n0, d) \ do { \ union {DItype __ll; \ struct {USItype __h, __l;} __i; \
} __x; \
__x.__i.__h = n1; __x.__i.__l = n0; \
__asm__ ("dr\t%0,%2" \
: "=r" (__x.__ll) \
: "0" (__x.__ll), "r" (d)); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0) #endif/* if __zarch__ */ #endif
#ifdefined (__s390x__) && W_TYPE_SIZE == 64 /* We need to cast operands with register constraints, otherwise their types will be assumed to be SImode by gcc. For these machines, such operations will insert a value into the low 32 bits, and leave the high 32 bits with
garbage. */ #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ do { \
__asm__ ("algr\t%1,%5\n\talcgr\t%0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "r" ((UDItype)(bh)), \ "%1" ((UDItype)(al)), "r" ((UDItype)(bl)) __CLOBBER_CC); \
} while (0) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ do { \
__asm__ ("slgr\t%1,%5\n\tslbgr\t%0,%3" \
: "=r" (sh), "=&r" (sl) \
: "0" ((UDItype)(ah)), "r" ((UDItype)(bh)), \ "1" ((UDItype)(al)), "r" ((UDItype)(bl)) __CLOBBER_CC); \
} while (0) #if !defined (__clang__) #define umul_ppmm(xh, xl, m0, m1) \ do { \ union {unsignedint __attribute__ ((mode(TI))) __ll; \ struct {UDItype __h, __l;} __i; \
} __x; \
__asm__ ("mlgr\t%0,%2" \
: "=r" (__x.__ll) \
: "%0" ((UDItype)(m0)), "r" ((UDItype)(m1))); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0) #define udiv_qrnnd(q, r, n1, n0, d) \ do { \ union {unsignedint __attribute__ ((mode(TI))) __ll; \ struct {UDItype __h, __l;} __i; \
} __x; \
__x.__i.__h = n1; __x.__i.__l = n0; \
__asm__ ("dlgr\t%0,%2" \
: "=r" (__x.__ll) \
: "0" (__x.__ll), "r" ((UDItype)(d))); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0) #endif #if 0 /* FIXME: Enable for z10 (?) */ #define count_leading_zeros(cnt, x) \ do { \ union {unsignedint __attribute__ ((mode(TI))) __ll; \ struct {UDItype __h, __l;} __i; \
} __clr_cnt; \
__asm__ ("flogr\t%0,%1" \
: "=r" (__clr_cnt.__ll) \
: "r" (x) __CLOBBER_CC); \
(cnt) = __clr_cnt.__i.__h; \
} while (0) #endif #endif
#if HAVE_HOST_CPU_i586 || HAVE_HOST_CPU_pentium || HAVE_HOST_CPU_pentiummmx /* Pentium bsrl takes between 10 and 72 cycles depending where the most significant 1 bit is, hence the use of the following alternatives. bsfl is slow too, between 18 and 42 depending where the least significant 1 bit is, so let the generic count_trailing_zeros below make use of the
count_leading_zeros here too. */
#if HAVE_HOST_CPU_pentiummmx && ! defined (LONGLONG_STANDALONE) /* The following should be a fixed 14 or 15 cycles, but possibly plus an L1 cache miss reading from __clz_tab. For P55 it's favoured over the float below so as to avoid mixing MMX and x87, since the penalty for switching between the two is about 100 cycles.
The asm block sets __shift to -3 if the high 24 bits are clear, -2 for 16, -1 for 8, or 0 otherwise. This could be written equivalently as follows, but as of gcc 2.95.2 it results in conditional jumps.
The middle two sbbl and cmpl's pair, and with luck something gcc generates might pair with the first cmpl and the last sbbl. The "32+1" constant could be folded into __clz_tab[], but it doesn't seem worth
making a different table just for that. */
#else/* ! pentiummmx || LONGLONG_STANDALONE */ /* The following should be a fixed 14 cycles or so. Some scheduling opportunities should be available between the float load/store too. This sort of code is used in gcc 3 for __builtin_ffs (with "n&-n") and is apparently suggested by the Intel optimizing manual (don't know exactly where). gcc 2.95 or up will be best for this, so the "double" is
correctly aligned on the stack. */ #define count_leading_zeros(c,n) \ do { \ union { \ double d; \ unsigned a[2]; \
} __u; \
__u.d = (UWtype) (n); \
(c) = 0x3FF + 31 - (__u.a[1] >> 20); \
} while (0) #define COUNT_LEADING_ZEROS_0 (0x3FF + 31) #endif/* pentiummx */
/* On P6, gcc prior to 3.0 generates a partial register stall for __cbtmp^31, due to using "xorb $31" instead of "xorl $31", the former being 1 code byte smaller. "31-__cbtmp" is a workaround, probably at the cost of one extra instruction. Do this for "i386" too, since that means
generic x86. */ #if ! defined (count_leading_zeros) && __GNUC__ < 3 \
&& (HAVE_HOST_CPU_i386 \
|| HAVE_HOST_CPU_i686 \
|| HAVE_HOST_CPU_pentiumpro \
|| HAVE_HOST_CPU_pentium2 \
|| HAVE_HOST_CPU_pentium3) #define count_leading_zeros(count, x) \ do { \
USItype __cbtmp; \
ASSERT ((x) != 0); \
__asm__ ("bsrl %1,%0" : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
(count) = 31 - __cbtmp; \
} while (0) #endif/* gcc<3 asm bsrl */
/* In the past we had a block of various #defines tested _ARCH_PPC - AIX _ARCH_PWR - AIX __powerpc__ - gcc __POWERPC__ - BEOS __ppc__ - Darwin PPC - old gcc, GNU/Linux, SysV The plain PPC test was not good for vxWorks, since PPC is defined on all CPUs there (eg. m68k too), as a constant one is expected to compare CPU_FAMILY against.
At any rate, this was pretty unattractive and a bit fragile. The use of HAVE_HOST_CPU_FAMILY is designed to cut through it all and be sure of getting the desired effect.
ENHANCE-ME: We should test _IBMR2 here when we add assembly support for the system vendor compilers. (Is that vendor compilers with inline asm,
or what?) */
#ifdefined (__sparc__) && W_TYPE_SIZE == 32 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rI" (bh),"%rJ" (al), "rI" (bl) \
__CLOBBER_CC) #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
: "=r" (sh), "=&r" (sl) \
: "rJ" (ah), "rI" (bh), "rJ" (al), "rI" (bl) \
__CLOBBER_CC) /* FIXME: When gcc -mcpu=v9 is used on solaris, gcc/config/sol2-sld-64.h
doesn't define anything to indicate that to us, it only sets __sparcv8. */ #ifdefined (__sparc_v9__) || defined (__sparcv9) /* Perhaps we should use floating-point operations here? */ #if 0 /* Triggers a bug making mpz/tests/t-gcd.c fail.
Perhaps we simply need explicitly zero-extend the inputs? */ #define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulx %2,%3,%%g1; srl %%g1,0,%1; srlx %%g1,32,%0" : \ "=r" (w1), "=r" (w0) : "r" (u), "r" (v) : "g1") #else /* Use v8 umul until above bug is fixed. */ #define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v)) #endif /* Use a plain v8 divide for v9. */ #define udiv_qrnnd(q, r, n1, n0, d) \ do { \
USItype __q; \
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \
(r) = (n0) - __q * (d); \
(q) = __q; \
} while (0) #else #ifdefined (__sparc_v8__) /* gcc normal */ \
|| defined (__sparcv8) /* gcc solaris */ \
|| HAVE_HOST_CPU_supersparc /* Don't match immediate range because, 1) it is not often useful, 2) the 'I' flag thinks of the range as a 13 bit signed interval, while we want to match a 13 bit interval, sign extended to 32 bits,
but INTERPRETED AS UNSIGNED. */ #define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v))
#if HAVE_HOST_CPU_supersparc #else /* Don't use this on SuperSPARC because its udiv only handles 53 bit
dividends and will trap to the kernel for the rest. */ #define udiv_qrnnd(q, r, n1, n0, d) \ do { \
USItype __q; \
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \
(r) = (n0) - __q * (d); \
(q) = __q; \
} while (0) #endif/* HAVE_HOST_CPU_supersparc */
#else/* ! __sparc_v8__ */ #ifdefined (__sparclite__) /* This has hardware multiply but not divide. It also has two additional
instructions scan (ffs from high bit) and divscc. */ #define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v)) #define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("! Inlined udiv_qrnnd\n" \ " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \ " tst %%g0\n" \ " divscc %3,%4,%%g1\n" \ " divscc %%g1,%4,%%g1\n" \ " divscc %%g1,%4,%%g1\n" \
--> --------------------
--> maximum size reached
--> --------------------
¤ Dauer der Verarbeitung: 0.92 Sekunden
(vorverarbeitet)
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