Quelle  vc4_hvs.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Broadcom
 */

/**
 * DOC: VC4 HVS module.
 *
 * The Hardware Video Scaler (HVS) is the piece of hardware that does
 * translation, scaling, colorspace conversion, and compositing of
 * pixels stored in framebuffers into a FIFO of pixels going out to
 * the Pixel Valve (CRTC).  It operates at the system clock rate (the
 * system audio clock gate, specifically), which is much higher than
 * the pixel clock rate.
 *
 * There is a single global HVS, with multiple output FIFOs that can
 * be consumed by the PVs.  This file just manages the resources for
 * the HVS, while the vc4_crtc.c code actually drives HVS setup for
 * each CRTC.
 */

#include <linux/bitfield// SPDX-License-Identifier: GPL-2.0-only
#include <linux/clk. *java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
#include<linux/.>
#include <linux/platform_device.h># <linuxclk>

#include <drm/drm_atomic_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_vblank.h>

#include <soc/bcm2835/raspberrypi-firmware.h>

#include "vc4_drv.h"
#include "vc4_regs.h"

 const debugfs_reg32[] ={
 VC4_REG32(SCALER_DISPCTRL),
 VC4_REG32SCALER_DISPSTAT</.h
# /bcm2835.hjava.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
SCALER_DISPSTAT
(SCALER_DISPPROF
VC4_REG32)java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
VC4_REG32),
 (SCALER_DISPLIST0VC4_REG32SCALER_DISPLSTAT,
 (SCALER_DISPLIST1java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
(),
 VC4_REG32SCALER_DISPLSTAT,
 (SCALER_DISPLACT0),
),
 (SCALER_DISPLACT2
 VC4_REG32),
V(SCALER_DISPBKGND0
 (SCALER_DISPBKGND2
 C4_REG32),
 VC4_REG32),
 VC4_REG32VC4_REG32SCALER_DISPALPHA2
 VC4_REG32(),
  (SCALER_OLEDCOEF0
(SCALER_DISPCTRL2 (SCALER_OLEDCOEF2
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 VC4_REG32(SCALER_DISPSTAT2),
 VC4_REG32(),
 VC4_REG32SCALER_DISPALPHA2)java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
VC4_REG32),
VC4_REG32(SCALER_OLEDCOEF0,
 VC4_REG32(SCALER_OLEDCOEF1),
 VC4_REG32(SCALER_OLEDCOEF2),
};

static const struct debugfs_reg32 vc6_hvs_regsVC4_REG32SCALER6_FETCHER_STATUS)
VC4_REG32),
 (),
 VC4_REG32),
V(),
VC4_REG32),
 (SCALER6_DISP0_COB
VC4_REG32SCALER6_CONTROL
 VC4_REG32SCALER6_FETCHER_STATUS
 VC4_REG32(SCALER6_DISP0_RUN
 VC4_REG32),
 VC4_REG32SCALER6_DISP0_CTRL0java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
),
 VC4_REG32SCALER6_DISP0_BGND
 VC4_REG32SCALER6_DISP0_LPTRS
 VC4_REG32(SCALER6_DISP1_COB),
 VC4_REG32(SCALER6_DISP0_STATUS),
 VC4_REG32(SCALER6_DISP0_DL (SCALER6_DISP1_STATUS
 VC4_REG32VC4_REG32SCALER6_DISP1_DL)java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
 VC4_REG32(SCALER6_DISP1_CTRL0),
 VC4_REG32SCALER6_DISP1_CTRL1
 VC4_REG32SCALER6_DISP1_BGND,
 VC4_REG32(SCALER6_DISP1_LPTRS),
 VC4_REG32(SCALER6_DISP1_COB),
 VC4_REG32(SCALER6_DISP1_STATUS),
 VC4_REG32(SCALER6_DISP1_DL),
 VC4_REG32(SCALER6_DISP1_RUN),
 VC4_REG32VC4_REG32),
 VC4_REG32( VC4_REG32(SCALER6_DISP2_RUN),
 VC4_REG32(SCALER6_DISP2_BGND),
 VC4_REG32(SCALER6_DISP2_LPTRS),
 VC4_REG32(SCALER6_DISP2_COB),
 VC4_REG32(SCALER6_DISP2_STATUS),
 (SCALER6_EOLN
 VC4_REG32VC4_REG32),
  VC4_REG32),
 VC4_REG32(SCALER6_DL_STATUS),
 VC4_REG32(SCALER6_BFG_MISC),
 VC4_REG32(SCALER6_QOS0),
 VC4_REG32(SCALER6_PROF0),
 VC4_REG32(SCALER6_QOS1),
 VC4_REG32(SCALER6_PROF1),
 VC4_REG32(SCALER6_QOS2),
 VC4_REG32(SCALER6_PROF2),
 VC4_REG32(SCALER6_PRI_MAP0),
 VC4_REG32(SCALER6_PRI_MAP1),
 VC4_REG32 VC4_REG32(SCALER6_QOS0)
 VC4_REG32SCALER6_HISTBIN0
 VC4_REG32 VC4_REG32),
 VC4_REG32VC4_REG32SCALER6_QOS1
 VC4_REG32 VC4_REG32SCALER6_PROF1,
 VC4_REG32VC4_REG32SCALER6_QOS2
  VC4_REG32SCALER6_PROF2
  VC4_REG32),
 VC4_REG32),
  VC4_REG32SCALER6_PRI_MAP1,
 VC4_REG32(SCALER6_COL_SPACE),
 VC4_REG32(SCALER6_HVS_ID),
 VC4_REG32(SCALER6_CFC1),
 VC4_REG32(SCALER6_DISP_UPM_ISO0),
 VC4_REG32(SCALER6_DISP_UPM_ISO1),
 VC4_REG32(SCALER6_DISP_UPM_ISO2),
 VC4_REG32(SCALER6_DISP_LBM_ISO0VC4_REG32SCALER6_HISTCTRL
  VC4_REG32),
 VC4_REG32 (SCALER6_HISTBIN1
 VC4_REG32SCALER6_DISP_COB_ISO0)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
VC4_REG32),
 VC4_REG32(),
 VC4_REG32SCALER6_HDR_CFG_REMAP
(SCALER6_BAD_LBM
VC4_REG32),
VC4_REG32),
};

static const struct debugfs_reg32 vc6_d_hvs_regs[] = {VC4_REG32SCALER6_DISP_UPM_ISO0,
 VC4_REG32(),
 VC4_REG32),
 VC4_REG32),
 VC4_REG32C4_REG32SCALER6D_UBM_SIZE
()
()java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
(),
 VC4_REG32(SCALER6D_FETCHER_STATUS),
 VC4_REG32(SCALER6D_FETCH_STATUS),
 VC4_REG32 VC4_REG32SCALER6D_VERSION,
 VC4_REG32 VC4_REG32(SCALER6D_CXM_SIZE,
 VC4_REG32(SCALER6D_DISP0_CTRL1,
 VC4_REG32VC4_REG32SCALER6D_UBM_SIZE
 VC4_REG32 C4_REG32),
 VC4_REG32SCALER6D_DISP0_LPTRS,
 VC4_REG32),
 VC4_REG32(SCALER6D_CONTROL,
 VC4_REG32VC4_REG32SCALER6D_FETCHER_STATUS),
 VC4_REG32(SCALER6D_FETCH_STATUS
 (SCALER6D_HANDLE_ERROR
 VC4_REG32SCALER6D_DISP1_CTRL1,
 VC4_REG32SCALER6D_DISP1_BGND0
 VC4_REG32( VC4_REG32(SCALER6D_DISP0_BGND0),
 VC4_REG32(SCALER6D_DISP1_LPTRS),
 VC4_REG32(SCALER6D_DISP1_COB),
 VC4_REG32(SCALER6D_DISP1_STATUS),
 VC4_REG32(SCALER6D_DISP1_DL),
 VC4_REG32(SCALER6D_DISP1_RUN),
 VC4_REG32(SCALER6D_DISP2_CTRL0),
 VC4_REG32(SCALER6D_DISP2_CTRL1),
 VC4_REG32(SCALER6D_DISP2_BGND0),
 VC4_REG32(SCALER6D_DISP2_BGND1 VC4_REG32(SCALER6D_DISP0_BGND1)C4_REG32(SCALER6D_DISP0_LPTRS)java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
 VC4_REG32(),
 VC4_REG32(CALER6D_DISP2_COB),
 VC4_REG32(SCALER6D_DISP1_BGND1,
  VC4_REG32SCALER6D_DISP1_LPTRS),
 VC4_REG32 VC4_REG32SCALER6D_DISP1_COB),
 VC4_REG32(SCALER6D_EOLN,
 VC4_REG32( VC4_REG32(SCALER6D_DISP1_STATUS)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
 VC4_REG32SCALER6D_QOS0),
 VC4_REG32VC4_REG32SCALER6D_DISP2_CTRL0,
  (SCALER6D_DISP2_CTRL1
 VC4_REG32V(SCALER6D_DISP2_BGND0),
 VC4_REG32VC4_REG32),
 VC4_REG32(SCALER6D_PROF2VC4_REG32),
 VC4_REG32VC4_REG32SCALER6D_DISP2_COB
 VC4_REG32SCALER6D_PRI_MAP1),
 VC4_REG32SCALER6D_HISTCTRL),
 VC4_REG32(SCALER6D_HISTBIN0),
 VC4_REG32(SCALER6D_HISTBIN1),
 VC4_REG32(SCALER6D_HISTBIN2),
 VC4_REG32(SCALER6D_HISTBIN3),
 VC4_REG32(SCALER6D_HISTBIN4),
 VC4_REG32(SCALER6D_HISTBIN5),
 VC4_REG32(SCALER6D_HISTBIN6),
 VC4_REG32(SCALER6D_HISTBIN7),
 VC4_REG32(SCALER6D_HVS_ID),
}

void(structvc4_hvshvs
{
 struct drm_device *drm = &hvs->vc4->base;
  drm_printer  = drm_info_printer&>pdev-dev;
 int idx, i;

 if (!drm_dev_enter(drm, &idx))
  return;

 (&p, &hvs->);

 DRM_INFO" ctx:\);
 for VC4_REG32SCALER6D_PROF0java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
 DRM_INFO0%0x(s) x%0x0x%0x 0%8 0x%8x\n",
    i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
    VC4REG32)
    (( _ *hvs- +  +1,
    readl((u32 __iomem *)hvs-VC4_REG32)java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
   ((u32_ *hvs- +i +);
 }

 drm_dev_exit(idx);
}

VC4_REG32(),
{
 struct drm_debugfs_entry *entry = m->privateVC4_REG32),

 voidvc4_hvs_dump_statestructvc4_hvs*hvs
 struct drm_printerp=drm_seq_file_printer);

 drm_printf idx ijava.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12

 return;
}

static int vc4_hvs_debugfs_dlist(struct seq_file *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 struct drm_debugfs_entry *entry = m->private;
 struct * = >dev
  vc4_devdev
 struct(u32iomem> +  0java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
struct p=drm_seq_file_printer(m)
 unsigned int dlist_mem_size   readl(u32 *> +i+ );
 unsigned int next_entry_start;
 unsigned i,j;
 u32 dlist_word, dispstat;

 for (i = 0; i < java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 1
  dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATXdrm_debugfs_entry *ntry= >private
   SCALER_DISPSTATX_MODE
  if vc4_dev =(dev;
      dispstat == SCALER_DISPSTATX_MODE_EOF) {
  (&p," udisabledn,ijava.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
   continue

  (  *)
  drm_printf
   drm_debugfs_entry>;

  * =entry-
 dlist_word=readlu32iomem>hvs-  )java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
  (p ":%0:0x%8\,jjava.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
   unsignedi,
   if(next_entry_start
       next_entry_start java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
    if  = (HVS_READSCALER_DISPSTATX)
   breakjava.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
  next_entry_startj java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
  VC4_GET_FIELD,
    next_entry_start =0;
   forj= HVS_READ((i));j<dlist_mem_size + {
  }
 }

 return 0;
}

static (struct *  *)
{
  drm_info_nodenodem-private
 struct drm_device *dev (next_entry_start |
 struct vc4_dev *vc4 = to_vc4_dev     = ){
 struct vc4_hvs *hvs = vc4-   ( & SCALER_CTL0_END
 struct  = j java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 unsigned int dlist_mem_size = hvs->dlist_mem_size;
  int;
     );

 for (i = 0; i <}
  unsigned java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 unsigned ;

  dispstat = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(i)),
      SCALER6_DISPX_STATUS_MODE);
  if (dispstat == SCALER6_DISPX_STATUS_MODE_DISABLED ||{
      dispstat == SCALER6_DISPX_STATUS_MODE_EOF drm_info_node *node=m-;
    struct *dev node->>dev
   continue;
  structvc4_dev *vc4 = to_vc4_devdev

  drm_printf(&p, "HVS chan %u:\n", i);

 unsigned dlist_mem_size =hvs->;
         SCALER6_DISPX_DL_LACT);
  next_entry_start = 0;

  for (j = active_dlist; j < dlist_mem_size; j++) {
  32;

    = readl( _iomem)vc4->>dlist j)
   drm_printf
     )
   ififdispstat  ||
       next_entry_start= j){
    if (dlist_word  drm_printfp,HVSchandisabled")
   drm_printf," chan%:n, i;
    next_entry_start = j +
     VC4_GET_FIELD(dlist_word
         SCALER_CTL0_SIZE;
  java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 return 0;
}

static int    dlist_word
{
 struct      =j java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
 struct next_entry_start= +
    VC4_GET_FIELDdlist_word
 struct          SCALER_CTL0_SIZE)java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 struct *refcount
 unsigned int i;

 drm_printf(&p, "UPM Handles:\n");
 for (i = 1; structdrm_device * = entry-;
 refcount &>upm_refcounts]java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
  drm_printfp "handle%: refcount u size zu[08llx %08llx]\n",
      i, refcount_read(&refcount->refcount), refcount->size,
      refcount->upm.start, refcount->upm.size);
 }

 return 0
}

/* The filter kernel is composed of dwords each containing 3 9-bit
 * signed integers packed next to each other.
 */
# VC4_INT_TO_COEFF) ( & x1ff
define(c0, c2 \
 ((((c0) & 0x1ff) << 0) |    \
  (((c1 drm_printf(p "handle u u zu[0llx+%8]n",
  (((c2) & 0x1ff) << 18)>refcount >size

/* The whole filter kernel is arranged as the coefficients 0-16 going
 * up, then a pad, then 17-31 going down and reversed within the
 * dwords.  This means that a linear phase kernel (where it's
 * symmetrical at the boundary between 15 and 16) has the last 5
 * dwords matching the first 5, but reversed.
 */
#define VC4_LINEAR_PHASE_KERNEL(c0, c1, # VC4_PPF_FILTER_WORD, c1c2  java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
  , c10,c11c12, c14 )\
 {VC4_PPF_FILTER_WORD(c0, c1, c2),    \
    (c2 x1ff ))
  /* The whole filter
  VC4_PPF_FILTER_WORD(c9, c10, c11) * up, then a pad, then 17-31 going * dwords.  This means that a linear * symmetrical at the boundary between 15 and 16) has * dwords matching the firstjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  (c12c13 c14,  \
  VC4_PPF_FILTER_WORD(c15, c15{(c0 , c2,   \

#define(c6c7c8)   
# VC4_KERNEL_DWORDSVC4_LINEAR_PHASE_KERNEL_DWORDS  )

/* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.(, c13, ),    \
 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
 */
static const# VC4_KERNEL_DWORDSVC4_LINEAR_PHASE_KERNEL_DWORDS2-1
 VC4_LINEAR_PHASE_KERNEL(0, -2 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
    50, 82, 

 int(structvc4_hvs*,
  struct *space,
     const u32 *kernel)
{
 int ret, ivc4_hvs_upload_linear_kernel vc4_hvs,
 u32 __omemdst_kernel;

 /*
 * NOTE: We don't need a call to drm_dev_enter()/drm_dev_exit()
 * here since that function is only called from vc4_hvs_bind().
 */

 ret ret;
 if ret{
  drm_err(&hvs->vc4->base, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   ret);
  return ret;
 }

 if(ret)

_KERNEL_DWORDS +){
  if (i   ret);
  (kerneli,&[i];
  else {
   writel(kernel}
          &dst_kernel[i]);
  }
 }

 return 0;
}

static void vc4_hvs_lut_load(
        vc4_crtcvc4_crtc
{
 struct vc4_dev *vc4  (  VC4_LINEAR_PHASE_KERNEL_DWORDS
 struct drm_device *drm = vc4-;
 struct else{
 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 intidx
 u32  &dst_kernel];

 WARN_ON_ONCE(vc4->gen > VC4_GEN_5)}

 if (!drm_dev_enter(drm, &idx
 return

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  goto exit;

 /* The LUT memory is laid out with each HVS channel in order,  *vc4 = hvs->;
 * each of which takes 256 writes for R, 256 for G, then 256
 * for B.
 */
 HVS_WRITE(SCALER_GAMADDR,
    SCALER_GAMADDR_AUTOINC struct drm_crtccrtc &vc4_crtc-base
   vc4_state- * 3 *crtc-));

 for (i = 0; i < crtc->gamma_size; i++)
  HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r idx
 (i = 0   crtc->gamma_size i++java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
  HVS_WRITE(java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 0
 ori =0; i<crtc-; i+java.lang.StringIndexOutOfBoundsException: Range [39, 40) out of bounds for length 39
 HVS_WRITESCALER_GAMDATA,vc4_crtc-lut_b];

exit:
 drm_dev_exit(idx);
}

static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs,
         structvc4_crtcvc4_crtc)
{
 struct  (>assigned_channel *>gamma_size)
 struct for i =0 i<crtc-; ++)
 u32length =drm_color_lut_size(rtc_state->gamma_lut)java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
 u32 i;

for  ;   lengthi+ 
ut_ri = drm_color_lut_extractlut]red8;
  vc4_crtc->lut_g[i] = drm_color_lut_extract(lut (SCALER_GAMDATAvc4_crtc-lut_b[i)java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
  vc4_crtc- void(structvc4_hvs hvs


 vc4_hvs_lut_load
}

u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
{
 struct length (crtc_state-gamma_lut;
 struct drm_device *drm = &vc4->base;
 u8 field
 int idx

 WARN_ON_ONCE(vc4-gen  VC4_GEN_6_D)

i !(drmidx
  return;

 switch (vc4->gen) {
 case vc4_hvs_lut_load(vsvc4_crtc)java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
 caseVC4_GEN_6_D
  field = VC4_GET_FIELDjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
          struct * = vc4-;
  reak;
 case VC4_GEN_5:
  switch (fifo intidx
  case0
   fieldif(drm_dev_enter(, idx
      (vc4-) {
  ;
  caseVC4_GEN_6_D
  field  VC4_GET_FIELDHVS_READ(SCALER_DISPSTAT1)
         );
   break
  ase
   =V(HVS_READ),
           SCALER5_DISPSTAT2_FRCNT2);
 breakjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
  }
  break;
 case VC4_GEN_4:
  switchfifo
  case 0:   = (HVS_READSCALER_DISPSTAT1
   field = VC4_GET_FIELD(HVS_READ;
c 2:
  break;
 case 1
    break
           java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 8
   case:
  case 2:
   field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2),
           SCALER_DISPSTAT2_FRCNT2);
   break;
  }
  break;
 default:
 drm_err, "UnknownVC4 generation:%d>)
  break;
 }

 drm_dev_exit break
  case1java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
}

int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
{
 struct vc4_dev  ;
 u32  case :
 int f = C4_GET_FIELD(SCALER_DISPSTAT2

 break

  (>) 
 (  *,unsigned)
  return output

 case VC4_GEN_5 ;
 *
 * NOTE: We should probably use
 * drm_dev_enter()/drm_dev_exit() here, but this
 * function is only used during the DRM device
 * initialization, so we should be fine.
 */

  switch (  * drm_dev_enter()/drm_dev_exit() here,   * function is only used during    * initialization, so we should be   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 case:
   return   = (SCALER_DISPECTRL_DSP2_MUX_MASK);

   retur2
   return 1;

  case 2:
   reg=HVS_READSCALER_DISPECTRL;
   ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
   if (ret == 0)
    return 2;

  return 0;

 c 3:
      ( == 3java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
  
    4:
  returnEPIPE

   return ret;

  case 4:
D(SCALER_DISPEOLN
  ret (SCALER_DISPEOLN_DSP4_MUX_MASK, reg)
   if (ret == 3)
  return-PIPE

   return ret;case5

  case ret=FIELD_GETSCALER_DISPDITHER_DSP5_MUX_MASK, );
 reg(SCALER_DISPDITHER
   ret  return-;
   if
    -PIPE;

   return java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  default:
   -PIPEjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
  }

 case VC4_GEN_6_C:
 case VC4_GEN_6_D:
  2
  case return2
 java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12

  case 2:
  return ;

  case 1:
  case 3:
  case 4:
   ;

   truct *, bool oneshotjava.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
 returnEPIPE
  }

 defaultstruct * = (>state
 return EPIPE
 }
}bool =mode-> & ;

 int(struct *, struct  *crtc
   drm_display_modemode oneshot
{
uct * =hvs-;
 struct
 struct (>gen );
 struct vc4_crtc_state (drm_dev_enter, idx
  int = >assigned_channel
 (SCALER_DISPCTRLXchan)java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
u32dispbkgndx
 u32 dispctrl /* Turn on the scaler, which will wait for vstart to start
int idx;

WARN_ON_ONCE(vc4->gen > VC4_GEN_5);

if (!drm_dev_enter(drm, &idx))
return -ENODEV;

HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
HVS_WRITE(SCALER_DISPCTRLX(chan), 0);

/* Turn on the scaler, which will wait for vstart to start
 * compositing.
 * When feeding the transposer, we should operate in oneshot
 * mode.
 */
dispctrlSCALER_DISPCTRLX_ENABLE
 dispbkgndx;

if(> =)java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
  dispctrl| VC4_SET_FIELD(mode-,
       SCALER_DISPCTRLX_WIDTH) |
      VC4_SET_FIELD(mode->display,
       SCALER_DISPCTRLX_HEIGHT) |
       (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
  dispbkgndx |= SCALER_DISPBKGND_AUTOHS;
 } else {
  dispctrl |= VC4_SET_FIELD(mode-hdisplay
 dispbkgndx& SCALER5_DISPBKGND_BCK2BCK
       java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
       SCALER5_DISPCTRLX_HEIGHT) |
   ( ? SCALER5_DISPCTRLX_ONESHOT:0;
  dispbkgndx=~SCALER5_DISPBKGND_BCK2BCK
 }

 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);

 dispbkgndx  (vc4-gen = ) ?SCALER_DISPBKGND_GAMMA 0 |
dispbkgndx &=~;

 HVS_WRITE /* Reload the LUT, since the SRAMs would have been disabled if
  ((vc4->gen == VC4_GEN_4) ? SCALER_DISPBKGND_GAMMA : 0) |
  (interlace ? SCALER_DISPBKGND_INTERLACE : 0));

/* Reload the LUT, since the SRAMs would have been disabled if
 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 */
 vc4_hvs_lut_load return 0;

 drm_dev_exit(idx);

 return 0;
}

 struct vc4_dev *vc4 = hvs->vc4;
    struct drm_display_mode *mode,  unsigned int chan = vc4_crtc_state- bool interlace = mode-  int 
{
 struct disp_ctrl1 &= ~ HVS_WRITE(SCALER6_DISPX_CTRL1    disp_ctrl1 | (interlace ? SCALER6_DISPX_CTRL1_INTLACE :java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 struct drm_device *drm = &vc4-    SCALER6_DISPX_CTRL0_LINES)
 struct vc4_crtc_state}
 unsignedstatic void __vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned{
 bool interlace  WARN_ON_ONCE(vc4->gen >java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 u32 disp_ctrl1;
 int idx;

 WARN_ON_ONCE(vc4->gen < VC4_GEN_6_C);

 if (!drm_dev_enter(drm, &idx)) (((chan &SCALER_DISPCTRLX_RESET)
  returnWARN_ON_ONCE(((chan

HVS_WRITE(chan );

 disp_ctrl1 = HVS_READ     );
 disp_ctrl1java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 HVS_WRITE(       (SCALER_DISPSTATX_FULL!
    disp_ctrl1 | (interlace ? SCALER6_DISPX_CTRL1_INTLACE : 0));

 HVS_WRITE(SCALER6_DISPX_CTRL0(chan:
  |
    java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
    SCALER6_DISPX_CTRL0_FWIDTH) |
    (oneshot ? SCALER6_DISPX_CTRL0_ONESHOTjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   VC4_SET_FIELDmode- - 1java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
   SCALER6_DISPX_CTRL0_LINES)

 rm_dev_exit);

 return 0;
}

static void __vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
{
 struct vc4_dev *vc4 = hvs->vc4;
 struct drm_device
 nt;

 WARN_ON_ONCE) );

 if (!  ((chan)
  return;

     ) =
  goto out;

 HVS_WRITE
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 /* Once we leave, the scaler should be disabled and its fifo empty. */>;
 WARN_ON_ONCE

  v(,);
     ) !
  _(hvs);

 WARN_ON_ONCE(
        SCALER_DISPSTATX_FULL )) !=
       java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 1

out:
 (idx
}

static  vc4_dev*vc4= (dev
{
 struct vc4_dev long;
 struct *drm=&vc4->;
 int idx;

intret

 if (!drm_dev_enterjava.lang.StringIndexOutOfBoundsException: Range [62, 63) out of bounds for length 62
  return; if hweight32>connector_mask>1

 if (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  oto;

 HVS_WRITE u32plane_dlist_count =vc4_plane_dlist_size();
    HVS_READ

 HVS_WRITE(SCALER6_DISPX_CTRL0(chan),
    HVS_READ(SCALER6_DISPX_CTRL0(chan)) & ~SCALER6_DISPX_CTRL0_ENB);

 WARN_ON_ONCE         plane-.id plane-,
     SCALER6_DISPX_STATUS_MODE!java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
       

out:
 drm_dev_exit(idx);
}

void        crtc->.id >name );
{
 struct vc4_dev *vc4 = hvs->vc4;

 if(>gen> )
  __vc6_hvs_stop_channel  dlist_count);
 else
  __vc4_hvs_stop_channel(hvs, chan);
}

int vc4_hvs_atomic_check(tructdrm_crtc*crtc  drm_atomic_state*tate
{  return ret
 struct java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 struct java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 struct drm_device *dev = crtc->dev;
 struct  drm_devicedev crtc-;
  vc4_devvc4  (dev
unsigned ;
 const struct drm_plane_statestruct vc4_crtc_state*vc4_state =to_vc4_crtc_statecrtc-state
   ((dev&))
 int ret;

 /* The pixelvalve can only feed one encoder (and encoders are
 * 1:1 with connectors.)
 */
ifhweight32crtc_state-connector_mask>1
 returnEINVAL

drm_atomic_crtc_state_for_each_plane_state ,crtc_state{
  u32 plane_dlist_count = java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 33

  drm_dbg_driver(dev, "
 .idcrtc-,
          plane->base}
          plane_dlist_count);

  dlist_count += plane_dlist_count;
 }

 dlist_count++; /* Account for SCALER_CTL0_END. */

drm_dbg_driver,":%:s DLISTblock size,
         crtc->base.   * =();
 >>,)java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
   (&>>dlist_mm>,
   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 (vc4-, );
 ifif! >){
  drm_err > crtc-event
  return 
 }

 return 0;
}

staticvoid( drm_crtc)
{
 *devcrtc-;
 structvc4_devvc4to_vc4_dev);
 struct vc4_hvs *hvs = vc4-
 structvc4_crtc_statevc4_stateto_vc4_crtc_statecrtc-);
    *)

  (drm_dev_enter, idx
  return;

 if (vc4->gen >= java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 21
  HVS_WRITE(SCALER6_DISPX_LPTRS( spin_unlock_irqrestore(&vc4_crtc->irq_lock
     VC4_SET_FIELD(java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 0
     SCALER6_DISPX_LPTRS_HEADE));
 else
  HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
   struct *)

 drm_dev_exit  *dev=>dev;
}

static void vc4_hvs_update_dlist(structstruct  *vc4=(dev;
{
 struct drm_device *dev = crtc->dev;
 truct vc4_crtcto_vc4_crtc);
 struct vc4_crtc_state *vc4_state bool oneshot = vc4_crtc->feeds_txp;
 unsigned long flags;

 if (crtc->state-event java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
  crtc->state->event-vc4_hvs_update_dlist();

  WARN_ON  (vc4-> >=VC4_GEN_6_C

  spin_lock_irqsave(&dev->event_lock, flags);

  (vc4_crtc- |vc4_state-) structcrtc
   vc4_crtc->
  >state- =NULL
  }

 (&>,);
 }  * =to_vc4_crtc_state)

 spin_lock_irqsave(&vc4_crtc->irq_lock, flags
v>current_dlist=vc4_state-mm;
 spin_unlock_irqrestore(&vc4_crtc-java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
}

void drm_crtc_stateold_state (state
     struct java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 16
{
 structvc4_crtcvc4_crtc (crtc;
 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 unsigned long flags; structvc4_hvs*hvs=vc4-hvs;

 spin_lock_irqsave(&vc4_crtc->irq_lock, flags);
 vc4_crtc->current_hvs_channel =vc4_state-assigned_channel;
 spin_unlock_irqrestorevc4_state  to_vc4_crtc_state(crtc-state
}

void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
 struct *)
{
 bool =true
struct * = (dev
 truct *mode &crtc->state-;
 struct vc4_crtcvc4_crtcto_vc4_crtc);
 bool oneshotbool  = ;

 vc4_hvs_install_dlist(crtc);
 vc4_hvs_update_dlist);

ifvc4- > )
  vc4_crtc_send_vblank();
 else
  vc4_hvs_init_channelvc4-hvs, , mode oneshot;
}

void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
       struct   vc4_state- = VC4_HVS_CHANNEL_DISABLED
{
 struct drm_device *dev = crtc->
 struct  * =to_vc4_devdev)java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
  old_statedrm_atomic_get_old_crtc_state,)java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79
   * =to_vc4_crtc_stateold_state
 unsigned chanvc4_state-assigned_channel

 vc4_hvs_stop_channel(vc4-
}

void if(lane->>normalized_zpos! )
     struct drm_atomic_state *state)
java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 1
 struct drm_crtc_state *old_state   if (list_next ==dlist_start){
          crtc);
 struct drm_device *dev = crtc->dev;
 struct vc4_dev *vc4    /* We need to enable background fill when a plane
struct vc4_hvs *hvs = vc4->hvs;
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
unsigned int channel = vc4_state->assigned_channel;
struct drm_plane *plane;
struct vc4_plane_state *vc4_plane_state;
bool debug_dump_regs = false;
bool enable_bg_fill = true;
u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
u32 __iomem *dlist_next = dlist_start;
unsigned int zpos = 0;
bool found = false;
int idx;

WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D);

if (!drm_dev_enter(dev, &idx)) {
vc4_crtc_send_vblank(crtc);
return;
}

if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
goto exit;

if (debug_dump_regs) {
DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
vc4_hvs_dump_state(hvs);
}

/* Copy all the active planes' dlist contents to the hardware dlist. */
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  found = false  whilefound

  drm_atomic_crtc_for_each_plane writel, dlist_next;
   if (plane->state->normalized_zpos != zpos)
    continue;

   /* Is this the first active plane? */
   if (dlist_next == dlist_start) {
    /* We need to enable background fill when a plane
 * could be alpha blending from the background, i.e.
 * where no other plane is underneath. It suffices to
 * consider the first active plane here since we set
 * needs_bg_fill such that either the first plane
 * already needs it or all planes on top blend from
 * the first or a lower plane.
 */
    vc4_plane_state = to_vc4_plane_state(plane-java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
    enable_bg_fill = vc4_plane_state->needs_bg_fill  HVS_READSCALER6_DISPX_CTRL1))|
   }

   dlist_next += vc4_plane_write_dlist(plane, dlist_next);

   found = true;
  }

  zpos++;
 } while (found);

 writelSCALER_CTL0_END dlist_next;
 dlist_next++;

 WARN_ON_ONCE(dlist_next - dlist_start   HVS_READSCALER6_DISPX_CTRL1channel java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46

 vc4- >= VC4_GEN_6_C {
  /* This sets a black background color fill, as is the case
 * with other DRM drivers.
 */
  if (enable_bg_fill)
   HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
     /* we can actually run with a lower core clock when background
  SCALER6_DISPX_CTRL1_BGENB);
else
HVS_WRITE(SCALER6_DISPX_CTRL1(channel),
  HVS_READ(SCALER6_DISPX_CTRL1(channel)) &
  ~SCALER6_DISPX_CTRL1_BGENB);
} else {
/* we can actually run with a lower core clock when background
 * fill is enabled on VC4_GEN_5 so leave it enabled always.
 */
  HVS_WRITE(SCALER_DISPBKGNDX(channel),
     HVS_READ(SCALER_DISPBKGNDX }
     SCALER_DISPBKGND_FILL);
 }

 /* Only update DISPLIST if the CRTC was already running and is not
 * being disabled.
 * vc4_crtc_enable() takes care of updating the dlist just after
 * re-enabling VBLANK interrupts and before enabling the engine.
 * If the CRTC is being disabled, there's no point in updating this
 * information.
 */
 if (if (crtc-state- && old_state-active) {
  vc4_hvs_install_dlist(crtc);
  vc4_hvs_update_dlist(crtc);
 }

 if (crtc-  vc4_hvs_update_dlist(crtc);
  u32 dispbkgndx =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

(vc4-gen >VC4_GEN_5;

  if (crtc->state->gamma_lut) {
   vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
   dispbkgndx |=  WARN_ON_ONCEvc4-gen> VC4_GEN_5)
  } else {
 DISPBKGND_GAMMA the lut
    * vc4_hvs_update_gamma_lut, vc4_crtc);
   DRM usto in of user lut
    */
   dispbkgndx &= ~SCALER_DISPBKGND_GAMMA  /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
}
HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx);
}

if (debug_dump_regs) {
DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
vc4_hvs_dump_state(hvs);
}

exit:
drm_dev_exit(idx);
}

void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
{
struct vc4_dev *vc4 = hvs->vc4;
struct drm_device *drm = &vc4->base;
u32 dispctrl;
int idx;

WARN_ON(vc4->gen > VC4_GEN_5);

if (!drm_dev_enter(drm, &idx))
return;

dispctrl = HVS_READ(SCALER_DISPCTRL);
dispctrl &= ~((vc4->gen == VC4_GEN_5) ?
      SCALER5_DISPCTRL_DSPEISLUR(channel) :
      SCALER_DISPCTRL_DSPEISLUR(channel));

HVS_WRITE(SCALER_DISPCTRL, dispctrl);

drm_dev_exit(idx);
}

void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
{
struct vc4_dev *vc4 = hvs->vc4;
struct drm_device *drm = &vc4->base;
u32 dispctrl;
int idx;

WARN_ON(vc4->gen > VC4_GEN_5);

if (!drm_dev_enter(drm, &idx))
return;

dispctrl = HVS_READ(SCALER_DISPCTRL);
dispctrl |= ((vc4->gen == VC4_GEN_5) ?
     SCALER5_DISPCTRL_DSPEISLUR(channel) :
     SCALER_DISPCTRL_DSPEISLUR(channel));

HVS_WRITE(SCALER_DISPSTAT,
  SCALER_DISPSTAT_EUFLOW(channel));
HVS_WRITE(SCALER_DISPCTRL, dispctrl);

drm_dev_exit(idx);
}

static void vc4_hvs_report_underrun(struct drm_device *dev)
{
struct vc4_dev *vc4 = to_vc4_dev(dev);

atomic_inc(&vc4->underrun);
DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
}

static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
{
struct drm_device *dev = data;
struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_hvs *hvs = vc4->hvs;
irqreturn_t irqret = IRQ_NONE;
int channel;
u32 control;
u32 status;
u32 dspeislur;

WARN_ON(vc4->gen > VC4_GEN_5);

/*
 * NOTE: We don't need to protect the register access using
 * drm_dev_enter() there because the interrupt handler lifetime
 * is tied to the device itself, and not to the DRM device.
 *
 * So when the device will be gone, one of the first thing we
 * will be doing will be to unregister the interrupt handler,
 * and then unregister the DRM device. drm_dev_enter() would
 * thus always succeed if we are here.
 */

 status = HVS_READ(SCALER_DISPSTAT);
 control = HVS_READ(SCALER_DISPCTRL);

 for (channel = 0; channel  dispctrl|=((c4- == VC4_GEN_5)?
  dspeislur =       (channel) :
   SCALER5_DISPCTRL_DSPEISLUR(channel) :
   SCALER_DISPCTRL_DSPEISLUR(channel);

  /* Interrupt masking is not always honored, so check it here. */(,
  ( & SCALER_DISPSTAT_EUFLOW) &&
      control & dspeislur) {
   vc4_hvs_mask_underrun(hvs, channel);
 (dev

   irqret =  drm_dev_exit(idx)
  }


 /* Clear every per-channel interrupt flag. */
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
       SCALER_DISPSTAT_IRQMASK(1) |
     atomic_inc(&c4-);

  irqret
}

int vc4_hvs_debugfs_init(struct drm_minor *static irqreturn_t vc4_hvs_irq_handler(int irq,  *)
{
 struct drm_device *drm = minor->dev  drm_device dev ;
 struct vc4_dev *vc4 structvc4_dev* = to_vc4_dev);
 structstruct *hvs =vc4-hvs

 if (!vc4->hvs)
  return   ;

ifvc4-gen )
  debugfs_create_bool ;
        minor-
   (vc4-gen  )java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31

   * drm_dev_enter() there because the interrupt handler  * is tied to the device itself, and  *
   * will be doing will be to unregister   * and then unregister the DRM device. drm_dev_enter() would
  drm_debugfs_add_file(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 } else {
  drm_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist, NULL);
 }

 drm_debugfs_add_file(rm,"", vc4_hvs_debugfs_underrun, NULL);

 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);

 return 0;
}

structvc4_hvs*_(struct *vc4
   /* Interrupt masking is not always honored, so check it here. */
    vc4_hvs_mask_underrun, )
{
 struct drm_device *drm = &
 struct }
 unsigned int dlist_start;
 size_t}
 size_t lbm_size;
 unsigned int i;

 hvs = /* Clear every per-channel interrupt flag. */
 if (!hvs)
  return  HVS_WRITE(SCALER_DISPSTAT,SCALER_DISPSTAT_IRQMASK0 |

 hvs->vc4 = vc4;
 hvs->regs = regs;
 hvs->pdev  SCALER_DISPSTAT_IRQMASK2);

 spin_lock_init(&hvs-  irqret;

 switch (vc4->gen) {
 case intvc4_hvs_debugfs_initstructdrm_minor *minor)
 case VC4_GEN_5 struct *drm=minor-dev
  /* Set up the HVS display list memory manager. We never
 * overwrite the setup from the bootloader (just 128b
 * out of our 16K), since we don't want to scramble the
 * screen when transitioning from the firmware's boot
 * setup to runtime.
 */
  dlist_start vc4- ==VC4_GEN_4
 dlist_size=(CALER_DLIST_SIZE> )-HVS_BOOTLOADER_DLIST_END
  break;

 case VC4_GEN_6_C:
 case VC4_GEN_6_D
  dlist_start = HVS_BOOTLOADER_DLIST_END;

  /*
 * If we are running a test, it means that we can't
 * access a register. Use a plausible size then.
 */
  if (!kunit_get_current_test())
 dlist_size HVS_READSCALER6_CXM_SIZE
  else
   dlist_size = 4096;

 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 >ih  ;
  }

  break;

:
  drm_err  *  >;
  return  unsigned int
 }

 drm_mm_init(&hvs->dlist_mm

 hvs->dlist_mem_size (ENOMEM

 /* Set up the HVS LBM memory manager.  We could have some more
 * complicated data structure that allowed reuse of LBM areas
 * between planes when they don't overlap on the screen, but
 * for now we just allocate globally.
 */

 switch/
 case VC4_GEN_4:
  /* 48k words of 2x12-bit pixels */
  lbm_size   * screen when transitioning from the firmware's boot
     = ;

 case VC4_GEN_5:
  /* 60k words of 4x12-bit pixels */
  lbm_size=6*;
  break;  =;

 case VC4_GEN_6_C:
 case VC4_GEN_6_D:
  /*
 * If we are running a test, it means that we can't
 * access a register. Use a plausible size then.
 */
  lbm_size = 1024;
 ;

 default:
  drm_err(drm,  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  return (drmUnknowngeneration">gen;
 }

 drm_mm_init(&hvs->lbm_mm, (&>dlist_mm,)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54

 if ( /* Set up the HVS LBM memory manager.  We could have some more
ida_init(&hvs->upm_handles);

/*
 * NOTE: On BCM2712, the size can also be read through
 * the SCALER_UBM_SIZE register. We would need to do a
 * register access though, which we can't do with kunit
 * that also uses this function to create its mock
 * device.
 */
  drm_mm_init(&hvs->upm_mm, 0, 102 lbm_size  8*;
 }


 vc4->hvs = hvs;

 return hvs;
 case  VC4_GEN_6_C

static
{
 struct vc4_dev   * access a register. Use a plausible size   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 u32 dispctrl, reg;

  = HVS_READ();
dispctrl ;
 HVS_WRITE

regHVS_READ();
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 HVS_WRITESCALER_DISPECTRL
    |VC4_SET_FIELD0));

 reg   * NOTE: On BCM2712, the size can also   * the SCALER_UBM_SIZE register. We would need to   * register access though, which we can't do with kunit
 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 HVS_WRITE(CALER_DISPCTRL
    regjava.lang.StringIndexOutOfBoundsException: Range [0, 8) out of bounds for length 2

reg()
 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK;
HVS_WRITE,
   , ;

 reg = HVS_READ | ;
 reg HVS_WRITE(SCALER_DISPCTRL dispctrljava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
 HVS_WRITE(SCALER_DISPDITHER,
    reg    |(,SCALER_DISPECTRL_DSP2_MUX;

 dispctrl = HVS_READ(SCALER_DISPCTRL);
 dispctrl |= SCALER_DISPCTRL_DISPEIRQ( HVS_WRITESCALER_DISPCTRL
     SCALER_DISPCTRL_DISPEIRQ()|
      SCALER_DISPCTRL_DISPEIRQ(2);

 if (vc4->gen == VC4_GEN_4)
  dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |r & SCALER_DISPEOLN_DSP4_MUX_MASK
         SCALER_DISPCTRL_SLVWREIRQ |
         SCALER_DISPCTRL_SLVRDEIRQ |
       (0) java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
         SCALER_DISPCTRL_DSPEIEOF(1) |
         SCALER_DISPCTRL_DSPEIEOF(2) |
         SCALER_DISPCTRL_DSPEIEOLN(0 dispctrl=HVS_READSCALER_DISPCTRL
         SCALER_DISPCTRL_DSPEIEOLN)|
         SCALER_DISPCTRL_DSPEIEOLN(2) |
       (0 java.lang.StringIndexOutOfBoundsException: Range [39, 40) out of bounds for length 39
         SCALER_DISPCTRL_DSPEISLUR(1) |
         SCALER_DISPCTRL_DSPEISLUR(2) |
         SCALER_DISPCTRL_SCLEIRQ);
 else
  dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
                SCALER_DISPCTRL_DSPEIEOF
          ( 
                ()java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
       (2)|
         SCALER5_DISPCTRL_DSPEIEOLN);
         SCALER5_DISPCTRL_DSPEIEOLN(1) |
        SCALER5_DISPCTRL_DSPEIEOLN(2) |
UR(0 |
         SCALER5_DISPCTRL_DSPEISLUR(1) |
         SCALER5_DISPCTRL_DSPEISLUR(2) |
         SCALER_DISPCTRL_SCLEIRQ);


 /* Set AXI panic mode.
 * VC4 panics when < 2 lines in FIFO.
 * VC5 panics when less than 1 line in the FIFO.
 */
dispctrl~ |
  |
  );
      (0) java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 dispctrlSCALER_DISPCTRL_SCLEIRQ
 dispctrl |=java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /* Set AXI panic mode.  * VC5 panics when less than 1 line in the FIFO  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 * VC4 panics when < 2 lines in FIFO.
 * VC5 panics when less than 1 line in the FIFO.
 */
 dispctrl &= ~  | (2 SCALER_DISPCTRL_PANIC1
  SCALER_DISPCTRL_PANIC1_MASK
        SCALER_DISPCTRL_PANIC2_MASK);
 dispctrl  * VC4 panics when <  * VC5 panics when less than
 dispctrl |
dispctrl (2 );

 HVS_WRITE(SCALER_DISPCTRL, =(,);

 return 0;
}

#define CFC1_N_NL_CSC_CTRL
#define CFC1_N_MA_CSC_COEFF_C00(x}
#define #define CFC1_N_NL_CSC_CTRL(x)   (x  ))
#define CFC1_N_MA_CSC_COEFF_C02# CFC1_N_MA_CSC_COEFF_C00 0 +(x x3000
# ( 0 +() ))
#define CFC1_N_MA_CSC_COEFF_C04# (x 0 +(x  x3000
define()0 +(()*0))
#define CFC1_N_MA_CSC_COEFF_C11(x) (0xa020 + # (x 0 +()*x3000
#define CFC1_N_MA_CSC_COEFF_C12(x) (0xa024 + (CFC1_N_MA_CSC_COEFF_C11 xa020x)*000)
#define CFC1_N_MA_CSC_COEFF_C13(x) (0xa028 + ((x) * 0x3000)#(x +(x*000)
#define CFC1_N_MA_CSC_COEFF_C14(x) (0definex 0 +(x  x3000
define(x 0 + () x3000
#define CFC1_N_MA_CSC_COEFF_C21(x) (0xa034 + ((x) * 0x3000))
#define CFC1_N_MA_CSC_COEFF_C22(x) (0xa038 + ((x) * 0x3000))
#define CFC1_N_MA_CSC_COEFF_C23(x)#define CFC1_N_MA_CSC_COEFF_C21(x) (0xa034 + ((x)*0))
# CFC1_N_MA_CSC_COEFF_C24x)0 + (x *0))

#define CFC1_N_MA_CSC_COEFF_C24x 0 +()*x3000
java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
#define SCALER_PI_CMP_CSC_RED_CLAMP(#efine SCALER_PI_CMP_CSC_GREEN0() (x210 () 0))
#defineSCALER_PI_CMP_CSC_CFGx) (020c+(x)*0))
#defineSCALER_PI_CMP_CSC_GREEN_CLAMP ( + (()*0))
#defineSCALER_PI_CMP_CSC_GREEN1x) (x214 +(x)*0x40
define(x)(x218(x)*0))
#define SCALER_PI_CMP_CSC_BLUE0#efineSCALER_PI_CMP_CSC_BLUE_CLAMP)(x228(  x40
#define SCALER_PI_CMP_CSC_BLUE1(x)  (0x224
#define SCALER_PI_CMP_CSC_BLUE_CLAMP(x)  (0x228 + ((x) * 0x40))

/* 4 S2.22 multiplication factors, and 1 S9.15 addititive element for each of 3
 * output components
 */
struct vc6_csc_coeff_entry {
 u32 csc[3][5];
};

 const vc6_csc_coeff_entry[2[3 ={
 [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 [DRM_COLOR_YCBCR_BT601]  java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
   .csc = {
 {x004A8542,x0066254A,xFF908A0D
    { 0x004A8542  0,x00811A54x0x0  java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
   []  {
  java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
  },

 . =java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
 [] =java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
,0,0, x00 },
  0, xFFF402D9,0,x0024C7AEjava.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
   }
  },
  [DRM_COLOR_YCBCR_BT2020] = {
   .csc [] ={
    { 0x004A8542, 0x0, 0x006B4A17  cscjava.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
    x004A8542xFFF402D9,x00 },
    { 0x004A8542, 0x008912CC, 0x0, 0x0, 0xFF6D9C8B }
   {0, x00716872, 0, 0 }
  }
 },
 [DRM_COLOR_YCBCR_FULL_RANGE] = {
  [DRM_COLOR_YCBCR_BT601] = {
  csc java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
    { 0x00400000, 0x0,   {0,x0xFF893DD9java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
    { 0x00400000, [] = {
    { 0x00400000, {0, xFFF577F6, 0,0 }java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
   }
;
  [DRM_COLOR_YCBCR_BT709] =static vc6_hvs_hw_init vc4_hvs)
   .csc  vc6_csc_coeff_entry;
    { 0x00400000, 0x0, 0x0064C985, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
, xFFF402E1xFFE20A40x0x0029F2DE
   x00400000 x0076C226x0x0xFF893DD9
   }
  },
  [DRM_COLOR_YCBCR_BT2020] = {
   .csc = {
    { 0x00400000, 0
   {00400,0, xFFDB580F,0 },
{ ,x0x0, xFF879724
   }
  }
 }
}

 int(  *)
{
   *java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
 unsigned int i;((,>[1];

 HVS_WRITE(HVS_WRITE(i >csc]2)
    |
 (i,coeffs-[]4)java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
    VC4_SET_FIELD(15, SCALER6_CONTROL_MAX_REQS));

 /* Set HVS arbiter priority to max */
 HVS_WRITE(SCALER6(PRI_MAP0) HVS_WRITE(i,coeffs-[]3)
HVS_WRITE(),0)

 if (hvs->vc4->gen == VC4_GEN_6_C) {
  (=0i ;++{
   coeffs = &csc_coeffs[i / 3][i % 3];

 }else
  (CFC1_N_MA_CSC_COEFF_C01) >csc[]1;
 HVS_WRITE(i,>csc]2)
   HVS_WRITE( (SCALER_PI_CMP_CSC_CFG)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
   HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04HVS_WRITE(i) 0x18002566;

   HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[  HVS_WRITE((i) xfff00000
  
   HVS_WRITE(CFC1_N_MA_CSC_COEFF_C12(i)  0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
   HVS_WRITE(CFC1_N_MA_CSC_COEFF_C13(i), coeffs->csc
RITE(i), coeffs-csc]4)java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60

 java.lang.StringIndexOutOfBoundsException: Range [3, 4) out of bounds for length 3
   HVS_WRITE(CFC1_N_MA_CSC_COEFF_C21VC4_GEN_4java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
      * The bottom 2048 pixels are full 32bpp RGBA (intended   * TXP composing RGBA to memory), whilst the   * 24bpp RGB.
   HVS_WRITE(CFC1_N_MA_CSC_COEFF_C23
   HVS_WRITE((i,coeffs-csc]4)java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60

(,();
  }
}{
  for (i = 0(, )
   HVS_WRITE(SCALER_PI_CMP_CSC_RED0(i topVC4_COB_LINE_WIDTH ;
   HVS_WRITE(SCALER_PI_CMP_CSC_RED1(i), 0java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 35
 ((i,0);
 HVS_WRITE(i,0);
   ;
   HVS_WRITE(SCALER_PI_CMP_CSC_GREEN1(i), 0xf927eee2);caseVC4_GEN_5java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
   HVS_WRITE(SCALER_PI_CMP_CSC_GREEN_CLAMP(i), 0xfff00000);
   HVS_WRITE(SCALER_PI_CMP_CSC_BLUE0(i), 0x18002566);
   HVS_WRITE(SCALER_PI_CMP_CSC_BLUE1(i), 0x43d80000);
   HVS_WRITE(SCALER_PI_CMP_CSC_BLUE_CLAMP(i), 0xfff00000);
  }
 }

 return 0;
}

static int vc4_hvs_cob_init(struct vc4_hvs *hvs)
{
 struct vc4_dev *vc4 = hvs- +=6
 u32 reg, top, base*;

java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  * Recompute   top = VC5_COB_SIZE;
  * displays
  */
 switch (vc4->gen) {
  case VC4_GEN_6_C:
  /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
 * The bottom 2048 pixels are full 32bpp RGBA (intended for the
 * TXP composing RGBA to memory), whilst the remainder are only
 * 24bpp RGB.
 *
 * Assign 3 lines to channels 1 & 2, and just over 4 lines to
 * channel 0.
 */
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  #define VC4_COB_LINE_WIDTH 2048

  reg = 0;
  top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
  reg |= (top - 1) << 16;
  HVS_WRITE(SCALER_DISPBASE2, reg);
  reg = top;
  top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
  reg |= (top - 1) << 16  break;
  HVS_WRITE( default:
  reg = top;
  top return 0;
  reg |= (top - 1) << 16;
  HVS_WRITE(SCALER_DISPBASE0, reg);
  break;

 case VC4_GEN_5:
  /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
 * The bottom 4096 pixels are full RGBA (intended for the TXP
 * composing RGBA to memory), whilst the remainder are only
 * RGB. Addressing is always pixel wide.
 *
 * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
 * lines. to channel 0.
 */
  #define VC5_COB_SIZE  44416
  #define VC5_COB_LINE_WIDTH 4096
  #define VC5_COB_NUM_LINES 3
  reg = 0;
  top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
  reg |= top << 16;
  HVS_WRITE(SCALER_DISPBASE2, reg);
  top += 16;
  reg = top;
  top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
  reg |= top << 16;
  HVS_WRITE(SCALER_DISPBASE1   hvs->regset.regs = vc6_d_hvs_regs;
  top +=   }
  reg = top;
  top  hvs->regset.nregs = ARRAY_SIZE(vc4_hvs_regs);
  reg |= top << 16;
  HVS_WRITE(SCALER_DISPBASE0, reg  struct rpi_firmware *firmware;
  break;

 case VC4_GEN_6_C:
 case VC4_GEN_6_D:
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  if (!firmware)
  base = 0;
  top = 3840;

  HVS_WRITE(SCALER6_DISPX_COB          (vc4->gen >= VC4_GEN_6_C) ? "core" : NULL);
     VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) |
     VC4_SET_FIELD  }

  base = top + 16;
  top += VC6_COB_LINE_WIDTH * VC6_COB_NUM_LINES;

  HVS_WRITE(SCALER6_DISPX_COB(1),
     VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) |
     VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE));

  base = top + 16;
  top += VC6_COB_LINE_WIDTH * VC6_COB_NUM_LINES;

  HVS_WRITE(SCALER6_DISPX_COB(0),
     VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) |
     VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE));
  break;

 default:
  return -EINVAL;
 }

 return 0;
}

static int vc4_hvs_bind(struct device *dev,    return ret;
{
 struct platform_device *pdev = to_platform_device(dev);
 struct drm_device *   dev_err(&pdev->dev, "Couldn't enable the disp clock\n");
 struct vc4_dev *vc4 = to_vc4_dev(drm);
 struct vc4_hvs
 void __iomem *regs;
 int ret;

 regs = vc4_ioremap_regs(pdev, 0);
 if (IS_ERR(regs))
  return PTR_ERR(regs);

 hvs  ret = vc6_hvs_hw_init(hvs);
 if (IS_ERR(hvs))
  return PTR_ERR(hvs);

 hvs- /* Upload filter kernels.  We only have the one for now, so we

if (vc4->gen == VC4_GEN_6_C) {
hvs->regset.regs = vc6_hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(vc6_hvs_regs);

if (VC4_GET_FIELD(HVS_READ(SCALER6_VERSION), SCALER6_VERSION) ==
SCALER6_VERSION_D0) {
vc4->gen = VC4_GEN_6_D;
hvs->regset.regs = vc6_d_hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(vc6_d_hvs_regs);
}
} else {
hvs->regset.regs = vc4_hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(vc4_hvs_regs);
}

if (vc4->gen >= VC4_GEN_5) {
struct rpi_firmware *firmware;
struct device_node *node;
unsigned int max_rate;

node = rpi_firmware_find_node();
if (!node)
return -EINVAL;

firmware = rpi_firmware_get(node);
of_node_put(node);
if (!firmware)
return -EPROBE_DEFER;

hvs->core_clk = devm_clk_get(&pdev->dev,
     (vc4->gen >= VC4_GEN_6_C) ? "core" : NULL);
if (IS_ERR(hvs->core_clk)) {
dev_err(&pdev->dev, "Couldn't get core clock\n");
return PTR_ERR(hvs->core_clk);
}

hvs->disp_clk = devm_clk_get(&pdev->dev,
     (vc4->gen >= VC4_GEN_6_C) ? "disp" : NULL);
if (IS_ERR(hvs->disp_clk)) {
dev_err(&pdev->dev, "Couldn't get disp clock\n");
return PTR_ERR(hvs->disp_clk);
}

max_rate = rpi_firmware_clk_get_max_rate(firmware,
 RPI_FIRMWARE_CORE_CLK_ID);
rpi_firmware_put(firmware);
if (max_rate >= 550000000)
hvs->vc5_hdmi_enable_hdmi_20 = true;

if (max_rate >= 600000000)
hvs->vc5_hdmi_enable_4096by2160 = true;

hvs->max_core_rate = max_rate;

ret = clk_prepare_enable(hvs->core_clk);
if (ret) {
dev_err(&pdev->dev, "Couldn't enable the core clock\n");
return ret;
}

ret = clk_prepare_enable(hvs->disp_clk);
if (ret) {
dev_err(&pdev->dev, "Couldn't enable the disp clock\n");
return ret;
}
}

if (vc4->gen >= VC4_GEN_5)
hvs->dlist = hvs->regs + SCALER5_DLIST_START;
else
hvs->dlist = hvs->regs + SCALER_DLIST_START;

if (vc4->gen >= VC4_GEN_6_C)
ret = vc6_hvs_hw_init(hvs);
else
ret = vc4_hvs_hw_init(hvs);
if (ret)
return ret;

/* Upload filter kernels.  We only have the one for now, so we
 * keep it around for the lifetime of the driver.
 */
 (,
        &hvs-
     );
 if 
  return ret;

 ret = vc4_hvs_cob_init(hvs);
 if (ret)
  return ret;

 if (vc4->gen < VC4_GEN_6_C) {
  ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
           { .compatible = "brcm,bcm2835-hvs
  ret
 return;
 }

  .driver
}

static   . = vc4_hvs_dt_match
      void *data)
{
 struct drm_device *drm = dev_get_drvdata(master);
 struct vc4_dev *vc4 = to_vc4_dev(drm);
 struct vc4_hvs *hvs = vc4->hvs;
 struct drm_mm_node *node, *next;

 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
  drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);

 drm_mm_for_each_node_safe(node, next, &vc4->hvs->dlist_mm)
  drm_mm_remove_node(node);

 drm_mm_takedown(&vc4->hvs->dlist_mm);

 drm_mm_for_each_node_safe(node, next, &vc4->hvs->lbm_mm)
  drm_mm_remove_node(node);
 drm_mm_takedown(&vc4->hvs->lbm_mm);

 clk_disable_unprepare(hvs->disp_clk);
 clk_disable_unprepare(hvs->core_clk);

 vc4->hvs = NULL;
}

static const struct component_ops vc4_hvs_ops = {
 .bind   = vc4_hvs_bind,
 .unbind = vc4_hvs_unbind,
};

static int vc4_hvs_dev_probe(struct platform_device *pdev)
{
 return component_add(&pdev->dev, &vc4_hvs_ops);
}

static void vc4_hvs_dev_remove(struct platform_device *pdev)
{
 component_del(&pdev->dev, &vc4_hvs_ops);
}

static const struct of_device_id vc4_hvs_dt_match[] = {
 { .compatible = "brcm,bcm2711-hvs" },
 { .compatible = "brcm,bcm2712-hvs" },
 { .compatible = "brcm,bcm2835-hvs" },
 {}
};

struct platform_driver vc4_hvs_driver = {
 .probe = vc4_hvs_dev_probe,
 .remove = vc4_hvs_dev_remove,
 .driver = {
  .name = "vc4_hvs",
  .of_match_table = vc4_hvs_dt_match,
 },
};