if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD)) return;
/* Set the pattern */ for (i = 0; i < sdm->table_size; i++) if (sdm->table[i].rate == rate)
writel(sdm->table[i].pattern,
common->base + sdm->tuning_reg);
/* * Sigma delta modulation provides a way to do fractional-N frequency * synthesis, in essence allowing the PLL to output any frequency * within its operational range. On earlier SoCs such as the A10/A20, * some PLLs support this. On later SoCs, all PLLs support this. * * The datasheets do not explain what the "wave top" and "wave bottom" * parameters mean or do, nor how to calculate the effective output * frequency. The only examples (and real world usage) are for the audio * PLL to generate 24.576 and 22.5792 MHz clock rates used by the audio * peripherals. The author lacks the underlying domain knowledge to * pursue this. * * The goal and function of the following code is to support the two * clock rates used by the audio subsystem, allowing for proper audio * playback and capture without any pitch or speed changes.
*/ bool ccu_sdm_helper_has_rate(struct ccu_common *common, struct ccu_sdm_internal *sdm, unsignedlong rate)
{ unsignedint i;
if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD)) returnfalse;
for (i = 0; i < sdm->table_size; i++) if (sdm->table[i].rate == rate) returntrue;