// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 PHYTEC Messtechnik GmbH
*/
/dts-v1/;
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx95-phycore-fpsc.dtsi"
/ {
compatible = "phytec,imx95-libra-rdk-fpsc",
"phytec,imx95-phycore-fpsc", "fsl,imx95";
model = "PHYTEC Libra i.MX95 RDK FPSC";
aliases {
can1 = &flexcan2;
can2 = &flexcan1;
ethernet0 = &enetc_port0;
serial0 = &lpuart7;
serial1 = &lpuart8;
};
chosen {
stdout-path = &lpuart7;
};
backlight_lvds0: backlight0 {
compatible = "pwm-backlight";
pinctrl-0 = <&pinctrl_lvds0>;
power-supply = <®_vdd_12v0>;
status = "disabled";
};
transceiver1: can-phy {
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <8000000>;
enable-gpios = <&gpio_expander 10 GPIO_ACTIVE_LOW>;
};
transceiver2: can-phy {
compatible = "ti,tcan1043";
#phy-cells = <0>;
max-bitrate = <8000000>;
enable-gpios = <&gpio_expander 9 GPIO_ACTIVE_LOW>;
};
panel0_lvds: panel-lvds0 {
backlight = <&backlight_lvds0>;
power-supply = <®_vdd_3v3>;
status = "disabled";
};
reg_vdd_12v0: regulator-vdd-12v0 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <12000000>;
regulator-min-microvolt = <12000000>;
regulator-name = "VDD_12V0";
};
reg_vdd_1v8: regulator-vdd-1v8 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "VDD_1V8";
};
reg_vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_3V3";
};
reg_vdd_5v0: regulator-vdd-5v0 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "VDD_5V0";
};
};
&enetc_port0 {
phy-handle = <ðphy0>;
status = "okay";
};
&enetc_port2 {
managed = "in-band-status";
phy-handle = <ðphy2>;
phy-mode = "10gbase-r";
};
/* CAN FD */
&flexcan1 {
phys = <&transceiver1>;
status = "okay";
};
&flexcan2 {
phys = <&transceiver2>;
status = "okay";
};
/* SPI-NOR */
&flexspi1 {
pinctrl-0 = <&pinctrl_flexspi>;
pinctrl-names = "default";
status = "okay";
spi_nor: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <166000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
vcc-supply = <®_vdd_1v8>;
};
};
&gpio2 {
gpio-line-names = "", "", "", "", "",
"", "", "", "", "",
"", "", "", "", "",
"", "RGMII2_nINT", "GPIO4", "RTC_INT", "",
"LVDS1_BL_EN";
};
&lpi2c1 {
temperature-sensor@4f {
compatible = "nxp,p3t1755";
reg = <0x4f>;
vs-supply = <®_vdd_1v8>;
};
};
&lpi2c3 {
status = "okay";
leds@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-1 {
type = <PCA9532_TYPE_LED>;
};
led-2 {
type = <PCA9532_TYPE_LED>;
};
led-3 {
type = <PCA9532_TYPE_LED>;
};
};
};
&lpi2c4 {
status = "okay";
gpio_expander: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
interrupt-parent = <&gpio2>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3",
"CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2",
"CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV",
"nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE",
"PCIE2_nWAKE", "PCIE2_nALERT_3V3",
"UART1_BT_RS_SEL", "UART1_RS232_485_SEL";
vcc-supply = <®_vdd_1v8>;
uart1_bt_rs_sel: bt-rs-hog {
gpios = <14 GPIO_ACTIVE_HIGH>;
gpio-hog;
line-name = "UART1_BT_RS_SEL";
output-low;
};
};
};
&lpi2c5 {
status = "okay";
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
vcc-supply = <®_vdd_1v8>;
};
};
/* Used for M33 debug */
&lpuart2 {
pinctrl-0 = <&pinctrl_lpuart2>;
pinctrl-names = "default";
};
/* A-55 debug UART */
&lpuart7 {
status = "okay";
};
/* RS232/RS485/BT */
&lpuart8 {
uart-has-rtscts;
status = "okay";
};
&netc_emdio { /* RGMII2 */
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
interrupt-parent = <&gpio2>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
ethphy2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x8>;
max-speed = <10000>; /* 10Gbit/s */
status = "disabled";
};
};
&pcie0 {
reset-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_vdd_3v3>;
status = "okay";
};
&pcie1 {
reset-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_vdd_3v3>;
status = "okay";
};
&rv3028 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio2>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
aux-voltage-chargeable = <1>;
wakeup-source;
trickle-resistor-ohms = <3000>;
};
&scmi_iomuxc {
pinctrl_lpuart2: lpuart2grp { /* FPSC proprietary */
fsl,pins = <
IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e
IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e
>;
};
pinctrl_lvds0: lvds0grp {
fsl,pins = <
IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x31e
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x31e
>;
};
pinctrl_tpm4: tpm4grp {
fsl,pins = <
IMX95_PAD_GPIO_IO21__TPM4_CH1 0x51e
>;
};
};
&tpm4 {
pinctrl-0 = <&pinctrl_tpm4>;
pinctrl-names = "default";
};
&usb3 {
fsl,over-current-active-low;
fsl,power-active-low;
status = "okay";
};
&usb3_dwc3 {
dr_mode = "peripheral";
status = "okay";
};
&usb3_phy {
vbus-supply = <®_vdd_5v0>;
status = "okay";
};
/* uSD Card */
&usdhc2 {
status = "okay";
};
