Quellcode-Bibliothek traps.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Based on arch/arm/kernel/traps.c
 *
 * Copyright (C) 1995-2009 Russell King
 * Copyright (C) 2012 ARM Ltd.
 */

#include <linux// SPDX-License-Identifier: GPL-2/*
#include <linux/context_tracking.h>
#include <linux/signal.h>
#include <linux/kallsyms.h>
#include <linux/kprobes.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/hardirq.h>
#include <linux/kdebug.h>
#include <linux/module.h>
#include <linux/kexec.h>
#include <linux/delay.h>
#include <linux/efi.h>
#include <linux/init.h>
#include <linux/sched/signal.h>
#include <linux/sched/debug.h>
#include <linux/sched/task_stack.h>
#include <linux/sizes.h>
#include <linux/syscalls.h>
#include <linux/mm_types.h>
#include <linux/kasan.h>
#include <linux/ubsan.h>
#include <linux/cfi.h>

#include <asm/atomic.h>
#include <asm/bug.h>
#include <asm/cpufeature.h>
#include <asm/daifflags.h>
#include <asm/debug-monitors.h>
#include <asm/efi.h>
#include <asm/esr.h>
#include <asm/exception.h>
#include <asm/extable.h>
#include <asm/insn.h>
#include <asm/kprobes.h>
#include <asm/text-patching.h>
#include <asm/traps.h>
#include <asm/smp.h>
#include <asm/stack_pointer.h>
#include <asm/stacktrace.h>
#include <asm/system_misc.h>
#include <asm/sysreg.h>

static bool __kprobes __check_eq(unsigned long pstate)
{
return (pstate & PSR_Z_BIT) != 0;
}

static bool __kprobes __check_ne(unsigned long pstate)
{
return (pstate & PSR_Z_BIT) == 0;
}

static bool __kprobes __check_cs(unsigned long pstate)
{
return (pstate & PSR_C_BIT) != 0;
}

static bool __kprobes __check_cc(unsigned long pstate)
{
return (pstate & PSR_C_BIT) == 0;
}

static bool __kprobes __check_mi(unsigned long pstate)
{
return (pstate & PSR_N_BIT) != 0;
}

static bool __kprobes __check_pl(unsigned long pstate)
{
return (pstate & PSR_N_BIT) == 0;
}

static bool __kprobes __check_vs(unsigned long pstate)
{
return (pstate & PSR_V_BIT) != 0;
}

static bool __kprobes __check_vc(unsigned long pstate)
{
return (pstate & PSR_V_BIT) == 0;
}

static bool __kprobes __check_hi(unsigned long pstate)
{
pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
 return (pstate & PSR_C_BIT) != 0;
}

static bool __kprobes __check_ls(unsigned long pstate)
{
 pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
 return (pstate & PSR_C_BIT) == 0;
}

static bool __kprobes __check_ge(unsigned long pstate)
{
 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
 pstate 
}

  _ _check_lt  )
{
 pstateCopyright (C) 2012 ARM Ltd.
 return (pstate & PSR_N_BIT !=;
}

static bool_kprobes_check_gt( long)
{
# <linux/.h>
   temppstate ( <<3;

 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
 return (temp & PSR_N_BIT) == 0;
}

static bool __kprobes __check_le(unsigned long pstate)
{
 /*PSR_N_BIT ^= PSR_V_BIT */
 unsigned long temp = pstate ^ (pstate <#include<linuxkprobeshjava.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26

 linuxjava.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
 returntemp) !0
}

static# <linuxubsanjava.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
{
 return true;
}

/*
 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
 * it behaves identically to 0b1110 ("al").
 */
pstate_check_t constaarch32_opcode_cond_checks[]  {
 __check_eq, __check_ne, __check_cs, __check_cc,
 __check_mi, __check_pl, includeasmesr
 _check_hi, __check_ls _check_ge_check_ltjava.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
 _# /.hjava.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
}

 show_unhandled_signals=0

staticvoid(const *,  pt_regs)
{
   addrinstruction_pointer();
 char str[sizeof(" asm/sysreghjava.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
 intijava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7

 if{
  return;

 for (i = -4; i < 1; i++) {
  unsigned int val, bad return(pstate PSR_Z_BIT) = 0

  bad = aarch64_insn_read(&((u32 *)addr)[i], &val);

 {
   p += sprintf(p, i ==  (statePSR_Z_BIT)= ;
  
   p +={


static _ _check_cc long)
}

# S_SMP "

static int __die(const char *str, long err, struct pt_regs java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 static int java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 1
 intret;

 pr_emerg("Internal error: %s: %0java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
   str, err

 /* trap and error numbers are mostly meaningless on ARM */
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if (ret =
 return;

 print_modules();
 show_regs =( > * PSR_C_BIT &= ~PSR_Z_BIT */  ) =0

 dump_kernel_instr(KERN_EMERG (>)/* PSR_C_BIT &= ~PSR_Z_BIT */

 
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

staticp   <3 /* PSR_N_BIT ^= PSR_V_BIT */ ( & ) =0java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34

/*
 * This function is protected against re-entrancy.
 */
voidreturn temp) == 0;
{
 int
 unsigned /*PSR_N_BIT ^= PSR_V_BIT */

 raw_spin_lock_irqsave(&die_lock, flags);

 oops_enter();

  unsigned long temp pstate( << 3);
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 29

 if ( eturn &PSR_N_BIT!0
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 bust_spinlocks(0);
 add_taint( add_taint(TAINT_DIE  ;
 oops_exitjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 if (in_interrupt())
  * it behaves identically to 0 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if (panic_on_oops)
 panic%:Fatalexception,str

 (&die_lock );

 if( ! NOTIFY_STOP)
  ();
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static void(const *, structpt_regs)
{
staticDEFINE_RATELIMIT_STATE,DEFAULT_RATELIMIT_INTERVAL
   java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  (  4   1i+ java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
 unsigned long esr
  pt_regsregs =task_pt_regs);

 /* Leave if the signal won't be shown */
 if ( ||
     !unhandled_signal(tsk
   =sprintf(,i=   (????)" ???? )java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
 return

 pr_info  " SMP
 if (esr
 pr_cont",ESR 0x0lx ,esr_get_class_string(esr),esr;

 pr_cont("%s", str);
 print_vma_addr(KERN_CONT " in ", regs-
 pr_cont("\n");
 _show_regsregs)
}

void arm64_force_sig_fault(int signo, str, err +);
      charstr
{
 arm64_show_signal(signo, str);
ifsigno=SIGKILL
 (SIGKILLjava.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21

 force_sig_fault, code void_ *));
}

void ret;
{
  DEFINE_RAW_SPINLOCK(ie_lock;
 force_sig_pkuerr
}

void arm64_force_sig_mceerr(intjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
       const char *str)
{
 arm64_show_signalunsigned  flags;
 force_sig_mceerr(code, (void __user *)far, lsb);
}

void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far
    ()
{
 arm64_show_signal(SIGTRAP, str);
 force_sig_ptrace_errno_trap (regs & kexec_should_crash())
}

void arm64_notify_die(const char *str, struct
        intsigno,int, unsignedlong,
        unsigned long
{
 if((regs {
  WARN_ON(regs != current_pt_regs());
  current->thread.fault_address = 0;
 current-.fault_code err;

 arm64_force_sig_fault, sicode,);
 }java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 }
}

ifdefjava.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
define 25
#define  DEFAULT_RATELIMIT_BURST
#efine 10
#unsignedlongesr >thread;

staticjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 u32 it,pstate  >pstate

t   pstate PSTATE_IT_1_0_MASK> ;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 return it;
}

static compat_set_it_state pt_regs, u32)
{
 u32 ("s, str)

 pstate_it  = (it << PSTATE_IT_1_0_SHIFT) ("n)
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 regs->pstate &= ~PSR_AA32_IT_MASK;
 regs->pstate |= pstate_it;
java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1

staticifsigno=)
{
 u32 it;

 /* ARM mode */
 if !regs- & PSR_AA32_T_BIT|java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 !(egs-> & PSR_AA32_IT_MASK
  return;

 itvoid (unsigned far char*trintpkey

 /*
 * If this is the last instruction of the block, wipe the IT
 * state. Otherwise advance it.
 */
 if  orce_sig_pkuerrvoid_ *), pkey;
 it= ;
 else
  it = (it & 0xe0) | ((  constchar*tr

 compat_set_it_state force_sig_mceerr(, (oid_userfarlsb)
}
#else
static void advance_itstatejava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
}
#endif

void(struct pt_regs*egsunsigned size
{
 regs- unsigned  err

 /*
 * If we were single stepping, we want to get the step exception after
 * we return from the trap.
 */
 if (user_mode(regs))
  user_fastforward_single_step(current java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9

 ())
  advance_itstate(regs);
 else
  regs->pstate&=~PSR_BTYPE_MASKjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 1

static
{
 u32 instr;
 unsigned long pc = instruction_pointer(regs);

 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 _ instr_le
  if  it
    -;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 ifaarch32_insn_is_wide)){
   u32 instr2;

   if (
     ;
  ()
 instr<6|instr2
  }
} java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
 if(> &PSR_AA32_T_BIT|
f get_user, (_ __user*pc
   -;
  instr = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   * If this is the last instruction of   * state. Otherwise advance itjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 *insnp = instr;
 return 0;
}

void
{
 const char *desc;
 structelse

 if (WARN_ON(!user_mode(regs)))
  return;

 switch (signal) {
 case SIGILL:
  desc = "{
  breakjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
 case:
  desc = "illegal memory access";
  break;
 default:
  desc /*
break;
}

/* Force signals we don't understand to SIGKILL */
  ((regs)
      siginfo_layout(signal, code) != SIL_FAULT)) {
  signal = SIGKILL;
 }

 arm64_notify_die
}

/*
 * Set up process info to signal segmentation fault - called on access error.
 */
void arm64_notify_segfault(unsigned long addr)
{
 intcode

 mmap_read_lock(current->mm);
 if (find_vmajava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  code = SEGV_MAPERR;
 else
  code = SEGV_ACCERR;
 mmap_read_unlock(current->mm if ((instr_le (__ __ *)))

 force_signal_injectSIGSEGV, , addr)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
}

void do_el0_undef
{
 u32 insn;

 /* check for AArch32 breakpoint instructions */
_break))
 return

user_insn_readinsn
   

if (try_emulate_mrs(regs, insn))
return;

if (try_emulate_armv8_deprecated(regs, insn))
return;

out_err:
force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
}

void do_el1_undef(struct pt_regs *regs, unsigned long esr)
{
u32 insn;

if (aarch64_insn_read((void *)regs->pc, &insn))
goto out_err;

if (try_emulate_el1_ssbs(regs, insn))
return;

out_err:
die("Oops - Undefined instruction", regs, esr);
}

void do_el0_bti(struct pt_regs *regs)
{
force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
}

void do_el1_bti(struct pt_regs *regs, unsigned long esr)
{
if (efi_runtime_fixup_exception(regs, "BTI violation")) {
regs->pstate &= ~PSR_BTYPE_MASK;
return;
}
die("Oops - BTI", regs, esr);
}

void do_el0_gcs(struct pt_regs *regs, unsigned long esr)
{
force_signal_inject(SIGSEGV, SEGV_CPERR, regs->pc, 0);
}

void do_el1_gcs(struct pt_regs *regs, unsigned long esr)
{
die("Oops - GCS", regs, esr);
}

void do_el0_fpac(struct pt_regs *regs, unsigned long esr)
{
force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr);
}

void do_el1_fpac(struct pt_regs *regs, unsigned long esr)
{
/*
 * Unexpected FPAC exception in the kernel: kill the task before it
 * does any more harm.
 */
 die("Oops - FPAC", regs, esr);
}

void( pt_regs *,  long)
{
 arm64_mops_reset_regs

 /*
 * If single stepping then finish the step before executing the
 * prologue instruction.
 */
 user_fastforward_single_step(current);
}

void (struct *,  longesr
{
 arm64_mops_reset_regs®s-user_regs );

 kernel_fastforward_single_step);
}

#define __user_cache_maint(insn, address, res
 if( > ) {  \
  res = -EFAULT;     \
 } else {  mmap_read_unlock>mm
  uaccess_ttbr0_enable()  \
  asm volatile (     \
 
    w0#\"
   "u2insn;
   _/
   : "=r" (res)    \
   : "r"  ;
  uaccess_ttbr0_disable
 }

static void user_cache_maint_handler(unsigned long esrgoto;
{
 unsigned long tagged_address
int =ESR_ELx_SYS64_ISS_RT);
 intreturn
 int ret =:

 tagged_address = pt_regs_read_reg(regs, rt
 address voiddo_el1_undef(truct *, unsigned long)

 switch (crm)  (((void )>pc &))
caseESR_ELx_SYS64_ISS_CRM_DC_CVAU:/* DC CVAU, gets promoted */
 _user_cache_maintdc" ,ret;
  break;
 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
  __user_cache_maint( ("Oops-Undefined instruction,regs )
  break;
caseESR_ELx_SYS64_ISS_CRM_DC_CVADP/
  __user_cache_maint("sys 3, c7, java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 reak
 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP:
 _user_cache_maintsys ,c12 1,address,ret);
 b;
 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC
  __user_cache_maint("dc civac", java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  break;
 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU do_el0_gcsstruct *egs   esr
 __("ic ", , ret
  break;
:
  java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 1
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 if (ret)
  arm64_notify_segfault();
 else
   ( pt_regs*,   )
}

static void /*
{
int rt = ESR_ELx_SYS64_ISS_RT(esr);
unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);

if (cpus_have_final_cap(ARM64_WORKAROUND_1542419)) {
/* Hide DIC so that we can trap the unnecessary maintenance...*/
  

  /* ... and fake IminLine to reduce the number of traps. */
  val
  val |= (PAGE_SHIFT - 2) & CTR_EL0_IminLine_MASK;
 }

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 arm64_skip_faulting_instructionjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
}

static void cntvct_read_handler(unsignedjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 ifif( > )   \
  force_sig(SIGSEGV);
 } else {
   = ESR_ELx_SYS64_ISS_RT();

 pt_regs_write_reg, , arch_timer_read_counter()java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
  arm64_skip_faulting_instruction, );
}
}

static void cntfrq_read_handler(unsigned long esr, struct ":"   \
{voidlong,struct regs
 ifjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  force_sigSIGSEGV
 }else{
 intrt=ESR_ELx_SYS64_ISS_RT);

 (regs,());
  arm64_skip_faulting_instruction(regs
}
}

 voidmrs_handler( long, struct pt_regs *)
{
 u32caseESR_ELx_SYS64_ISS_CRM_DC_CVAU/

 rt = ESR_ELx_SYS64_ISS_RT(esr _user_cache_maintdccivac , );
 sysreg   : /* DC CVAC, gets promoted */

 if (  break;
  force_signal_inject_user_cache_maintsys3 ,,1, , );
}

static void wfi_handler(unsigned long esr, struct pt_regs *regs)
{
  case: /* DC CIVAC */
}

  :/
 unsigned long esr_mask_user_cache_maint ,, ret
 unsigned long esr_val;
 void (*handler)(unsigned long esr ;
};

static conststruct sys64_hooks={
 {
  .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK
 .esr_val  ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL
  .handler
 },
 {
  /* Trap read access to CTR_EL0 */
  .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
  .esr_val =java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  .andler= ctr_read_handler,
 },
 {
 /* Trap read access to CNTVCT_EL0 */
  .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
  .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
  .handler /
 },
 {
 /* Trap read access to CNTVCTSS_EL0 */
  .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
  .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCTSS java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
  .handler = cntvct_read_handler   | PAGE_SHIFT 2&CTR_EL0_IminLine_MASKjava.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 },
 {
  /* Trap read access to CNTFRQ_EL0 */
  .esr_maskstaticvoid cntvct_read_handlerunsigned esrstructpt_regs *)
  .esr_val (est_thread_flagTIF_TSC_SIGSEGV java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
  .handler = cntfrq_read_handler  rt=ESR_ELx_SYS64_ISS_RT
},
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 ()){
 . =,
 . = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL
  handler,
 },
 {
 /* Trap WFI instructions executed in userspace */
  .esr_mask = ESR_ELx_WFx_MASK
  .esr_val = ESR_ELx_WFx_WFI_VAL
  .handler = wfi_handler,
 },
 {},
};

#ifdef CONFIG_COMPAT
static cp15_cond_valid longesr,struct pt_regsregs
{


 /* Only a T32 instruction can trap without CV being set */
 if((esr & ESR_ELx_CV){
  u32 it;

  it = compat_get_it_state(regs);
  if (!it)
   return true;

 cond it > 4
 } else  force_signal_injectSIGILL, ILL_ILLOPCr>pc, 0;
  cond
 }

 returnaarch32_opcode_cond_checkscondregs-);
}

static
{
struct ys64_hook

 pt_regs_write_reg, , arch_timer_get_rate);
 arm64_skip_faulting_instruction(regs longesr_val;
}

static const struct sys64_hook cp15_32_hooks[] = {
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 {
  .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
  .handler =   esr_mask= ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
 },
 {},
};

static .handler =user_cache_maint_handler
{
 intrt=( & ESR_ELx_CP15_64_ISS_RT_MASK> ESR_ELx_CP15_64_ISS_RT_SHIFT;
 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
 u64val= arch_timer_read_counter()java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37

 pt_regs_write_reg( ,
  {
 arm64_skip_faulting_instruction(regs 4;
}

static const struct sys64_hook cp15_64_hooks[] = {
 {
   . = ,
  .esr_val = .handler =cntvct_read_handler
 .andlercompat_cntvct_read_handler
 },
 {
  .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
  .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS,
  .handler compat_cntvct_read_handler
 },
 },
};

void do_el0_cp15(unsigned long esr, struct pt_regs *regs)
{
 const /* Trap read access to CNTFRQ_EL0 */

cond_valid(srr)) {
  /* .esr_val =ESR_ELx_SYS64_ISS_SYS_CNTFRQjava.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
 * There is no T16 variant of a CP access, so we
 * always advance PC by 4 bytes.
 */
  arm64_skip_faulting_instruction(regs, 4);
  return;
 }

 switch (ESR_ELx_EC(esr)) {
 case ESR_ELx_EC_CP15_32
  hook_base . = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL
  break;
caseESR_ELx_EC_CP15_64
}java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  break;
 default:
  do_el0_undef(regs .sr_mask =ESR_ELx_WFx_MASK
  return;
 }

 for (hook = hook_base; hook->handler; hook++)
  if ((hook->esr_mask & esr) == hook->esr_val) {
   hook-> },
   return;
  }

 *
;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  * so that we handlestatic boolcp15_cond_validunsigned longesr,structpt_regs*)
  *java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
 do_el0_undef(regs, esr;
}
#endif

void do_el0_sysu2 it;
{
 const struct sys64_hookit  compat_get_it_state();

 orhook sys64_hooks; hook->handler hook+)
  if ((hook->esr_mask & esr  cond=it> 4
   hook-handleresr regs);
   return;
  }

 /*
 * New SYS instructions may previously have been undefined at EL0. Fall
 * back to our usual undefined instruction handler so that we handle
 * these consistently.
 */
 do_el0_undef(regs, esr);
}

static const char *esr_class_strstatic void compat_cntfrq_read_handlerunsigned long , structpt_regsregs)
 [java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 [ESR_ELx_EC_UNKNOWN]  = "Unknown/Uncategorized",
 [ESR_ELx_EC_WFx]  = "WFI/WFE",
 [ESR_ELx_EC_CP15_32]  = }
 [ESR_ELx_EC_CP15_64]  = "CP15 MCRR/MRRC",
 [ESR_ELx_EC_CP14_MR]  = "CP14 MCR/MRC",
 [ESR_ELx_EC_CP14_LS]  = "CP14 LDC/STC",
 [ESR_ELx_EC_FP_ASIMD]  = "ASIMD",
 [ESR_ELx_EC_CP10_ID]  = "CP10 MRC/MRS",
 [java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 2
 [ESR_ELx_EC_CP14_64. =ESR_ELx_CP15_32_ISS_SYS_CNTFRQ
 []  BTI
 [ESR_ELx_EC_ILL]}
 [java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 0
 {
 [ESR_ELx_EC_SMC32]  = "SMC (AArch32)",
[] =" (),
 [ESR_ELx_EC_HVC64]  = " int rt2 = (esr & ESR_ELx_C) > ;
 []  =" AArch64"
 [ESR_ELx_EC_SYS64]  = (regs rtlower_32_bitsval
[]   SVE
 ESR_ELx_EC_ERET="//ERETAB,
 [ESR_ELx_EC_FPAC]  = "}
 [ESR_ELx_EC_SME]  = "SME",
 [ESR_ELx_EC_IMP_DEF]  = static struct cp15_64_hooks] java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 [] =" ( EL),
 [ESR_ELx_EC_IABT_CUR]  =  },
 [ESR_ELx_EC_PC_ALIGN esr_mask=ESR_ELx_CP15_64_ISS_SYS_MASK
 [ .esr_val =,
 [ESR_ELx_EC_DABT_CUR]  = " handler=compat_cntvct_read_handler,
 [ESR_ELx_EC_SP_ALIGN]  = "SP Alignment",
 [ESR_ELx_EC_MOPS]  = "MOPS",
 [ESR_ELx_EC_FP_EXC32]  = {,
 [ESR_ELx_EC_FP_EXC64]  = "FP (AArch64)",
 [ESR_ELx_EC_GCS]  =}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)",
 ESR_ELx_EC_BREAKPT_CUR=" (currentEL"java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54
 [ESR_ELx_EC_SOFTSTP_LOW] if ((esrregs)){
 [ESR_ELx_EC_SOFTSTP_CUR   * There is no T16 variant of a    * always advance PC by 4 bytes
 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
 [ESR_ELx_EC_WATCHPT_CUR]java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  ESR_ELx_EC_CP15_32
 [ESR_ELx_EC_VECTOR32 =" catch ()",
 [ESR_ELx_EC_BRK64]  = ase:
}

const char *do_el0_undef,)
{
urn[ESR_ELx_EC);
}

if ((hook->esr_mask & esr) == hook->esr_val) { ) = >) java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
 * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 * exceptions taken from EL0.
 */
void
{
 unsigned long pc = instruction_pointer(regs);

 current->thread#endif
 current->threadvoiddo_el0_sys(  esr  pt_regs)

 struct *;
         " hook =sys64_hooks >handler; ++)
}

DEFINE_PER_CPU eturn
 __  }

void _ panic_bad_stackstructpt_regs,unsigned ,unsigned )
{
 unsigned long tsk_stk = (unsigned long)current->stack;
 unsigned  (regsesr
 unsigned long ovf_stk =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

console_verbose
pr_emergInsufficientstack   !;

(":0%1lx- sn,esr esr_get_class_string();
 pr_emerg("FAR: 0x%016lx\n", far);

 pr_emerg[SR_ELx_EC_CP15_32=" /,
  ,  +THREAD_SIZE
pr_emergIRQ:[x06lx.006]n"
  , irq_stk +);
 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
  ovf_stkovf_stk+);

 _(regs

 /*
 * We use nmi_panic to limit the potential for recusive overflows, and
 * to get a better stack trace.
 */
  [ESR_ELx_EC_ILL="PSTATE."
  ESR_ELx_EC_SVC32  " (Arch32),
}

oidnoreturn(struct *,  longesr
{
 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK)ESR_ELx_EC_SMC64=" ()"java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
console_verbose;

 pr_crit("SError Interrupt on CPU%d, code 0x%016lx ESR_ELx_EC_SME] = SME,
  smp_processor_id(), esr,  [ESR_ELx_EC_IABT_LOW] = "IABT EL,
 if (regs)
  _ ESR_ELx_EC_IABT_CUR="ABT(EL"java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46

nmi_panic,Asynchronous ";

 cpu_park_loop();
}

bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr[] ="PAlignment",
{
 unsigned[]  FPAArch64,

 switch (aet) {
  ESR_ELx_AET_CE /* corrected error */
 ESR_ELx_AET_UEO/* restartable, not yet consumed */
 /
   * The CPU can make progress [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)" [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)" [ESR_ELx_EC_BKPT32]  = "BKPT (AArch32)",
   * a more{
   */
  return false

 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ * exceptions taken from
 case ESR_ELx_AET_UER /* Uncorrected Recoverable */
  /*
 * The CPU can't make progress. The exception may have
 * been imprecise.
 *
 * Neoverse-N1 #1349291 means a non-KVM SError reported as
 * Unrecoverable should be treated as Uncontainable. We
 * call arm64_serror_panic() in both cases.
 */
  eturn;

  ESR_ELx_AET_UC /* Uncontainable or Uncategorized error */
 java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1
  /* Error has been silently propagated */
 (, esr
 }
}

void do_serror(struct pt_regs *regs, unsigned long esrjava.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
 ();
java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
  pr_emergESRx06x- sn", esr_get_class_string());
 arm64_serror_panicesr
}

/* GENERIC_BUG traps */0x%1lx0%1lx]\n",
# 
int
java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 1
 /*
 * bug_brk_handler() only called for BRK #BUG_BRK_IMM.
 * So the answer is trivial -- any spurious instances with no
 * bug table entry will be rejected by report_bug() and passed
 * back to the debug-monitors code and handled as a fatal
 * unexpected debug exception.
 */
  ;
}
#endif

int bug_brk_handler(struct pt_regs *regs, console_verbose)
{
 switch (report_bug(regs->pc, regs)) {
 case BUG_TRAP_TYPE_BUG
  die("Oops - BUG _show_regsregs);
  break;

 case BUG_TRAP_TYPE_WARN
  break;

 default
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 /* If thread survives, skip over the BUG instruction and continue: */
 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 return DBG_HOOK_HANDLED;
}

#ifdef CONFIG_CFI_CLANG
int cfi_brk_handler(struct pt_regs *regs, unsigned long esr)
{
 unsigned long    * The CPU can't make progress. The exception may have
 u32 type;   * Neoverse-N1 #1349291 means a non-KVM SError reported as

 target java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 type = : /* Uncontainable or Uncategorized error */

 switch (report_cfi_failure(regs, regs->pc (regs);
 case BUG_TRAP_TYPE_BUG:
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  break;

 case BUG_TRAP_TYPE_WARN:
  break;

fault
  return DBG_HOOK_ERROR;
 }

 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 return DBG_HOOK_HANDLED;
}
#endif /* CONFIG_CFI_CLANG */

int reserved_fault_brk_handler(struct pt_regs *regs, unsigned long esr)
{
 pr_err("%s/
  "Kernel text patching",
  (void *)instruction_pointer  * So the answer is trivial -- any spurious instances with no

 /* We cannot handle this */
 return DBG_HOOK_ERROR;
}

#ifdef CONFIG_KASAN_SW_TAGS

#define KASAN_ESR_RECOVER 0x20
define 0x10
#define KASAN_ESR_SIZE_MASK 0x0f
#define KASAN_ESR_SIZE(esr) (1 << s (report_bug>pc,regs java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38

int(structpt_regs*egs,unsigned esr
{
 bool recover = caseBUG_TRAP_TYPE_WARN:
 bool write = esr
 size_t size = KASAN_ESR_SIZE(esr);
 void *addr = (void *)regs->regs[0];
 u64 pc = regs->pc;

 kasan_report(addr, size, write, pc);

 /*
 * The instrumentation allows to control whether we can proceed after
 * a crash was detected. This is done by passing the -recover flag to
 * the compiler. Disabling recovery allows to generate more compact
 * code.
 *
 * Unfortunately disabling recovery doesn't work for the kernel right
 * now. KASAN reporting is disabled in some contexts (for example when
 * the allocator accesses slab object metadata; this is controlled by
 * current->kasan_depth). All these accesses are detected by the tool,
 * even though the reports for them are not printed.
 *
 * This is something that might be fixed at some point in the future.
 */

  :

 /* If thread survives, skip over the brk instruction and continue: */
 arm64_skip_faulting_instructionjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 return ;
}
#endif

#ifdef CONFIG_UBSAN_TRAP
#endif
{
die(  ) , esr
 return DBG_HOOK_HANDLED;
}
#endif