/* SPDX-License-Identifier: GPL-2.0-only */ /* * xchg/cmpxchg operations for the Hexagon architecture * * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*/
#ifndef _ASM_CMPXCHG_H #define _ASM_CMPXCHG_H
/* * __arch_xchg - atomically exchange a register and a memory location * @x: value to swap * @ptr: pointer to memory * @size: size of the value * * Only 4 bytes supported currently. * * Note: there was an errata for V2 about .new's and memw_locked. *
*/ staticinlineunsignedlong
__arch_xchg(unsignedlong x, volatilevoid *ptr, int size)
{ unsignedlong retval;
/* Can't seem to use printk or panic here, so just stop */ if (size != 4) do { asmvolatile("brkpt;\n"); } while (1);
__asm__ __volatile__ ( "1: %0 = memw_locked(%1);\n"/* load into retval */ " memw_locked(%1,P0) = %2;\n"/* store into memory */ " if (!P0) jump 1b;\n"
: "=&r" (retval)
: "r" (ptr), "r" (x)
: "memory", "p0"
); return retval;
}
/* * Atomically swap the contents of a register with memory. Should be atomic * between multiple CPU's and within interrupts on the same CPU.
*/ #define arch_xchg(ptr, v) ((__typeof__(*(ptr)))__arch_xchg((unsignedlong)(v), (ptr), \ sizeof(*(ptr))))
/* * see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps. * looks just like atomic_cmpxchg on our arch currently with a bunch of * variable casting.
*/
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