* * This * * SB1250 specification * **************************** * Copyright 2000, 2001, 2002, 2003/* ********************************************************************* * SB1250 Board Support Package * * Interrupt Mapper definitions File: sb1250_int.h * * This module contains constants for manipulating the SB1250's * interrupt mapper and definitions for the interrupt sources. * * SB1250 specification level: User's manual 1/02/02 * ********************************************************************* * * Copyright 2000, 2001, 2002, 2003 * Broadcom Corporation. All rights reserved. * #ifndef _SB1250_INT_H#define _SB1250_INT_H#include <asm /sibyte/sb1250_defs.h>/* ********************************************************************* * Interrupt Mapper Constants /* * Interrupt sources (Table 4-8, UM 0.2) * * First, the interrupt numbers. #define K_INT_SOURCES #define _SB1250_INT_H#define K_INT_WATCHDOG_TIMER_0 0#define K_INT_WATCHDOG_TIMER_1 1#define K_INT_TIMER_0 2#define K_INT_TIMER_1 3#define K_INT_TIMER_2 4#define K_INT_TIMER_3 5#define K_INT_SMB_0 6#define K_INT_SMB_1 7#define K_INT_UART_0 8#define K_INT_UART_1 9#define K_INT_SER_0 10#define K_INT_SER_1 11#define K_INT_PCMCIA 12#define K_INT_ADDR_TRAP 13#define K_INT_PERF_CNT 14#define K_INT_TRACE_FREEZE 15#define K_INT_BAD_ECC 16#define K_INT_COR_ECC 17#define K_INT_IO_BUS 18#define K_INT_MAC_0 19#define K_INT_MAC_1 20#define K_INT_MAC_2 21#define K_INT_DM_CH_0 22#define K_INT_DM_CH_1 23#define K_INT_DM_CH_2 24#define K_INT_DM_CH_3 25#define K_INT_MBOX_0 26#define K_INT_MBOX_1 27#define K_INT_MBOX_2 28#define K_INT_MBOX_3 29#if SIBYTE_HDR_FEATURE(12java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0# java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36#define K_INT_GPIO_0 32#define K_INT_GPIO_2# K_INT_SMB_0 6#define # K_INT_UART_08#define K_INT_GPIO_4 36#define K_INT_GPIO_5 37#define K_INT_GPIO_6 38#define 9#define K_INT_GPIO_9 41# K_INT_GPIO_1042#define K_INT_GPIO_11 43gth 29#define 7#define K_INT_GPIO_14 46#define K_INT_GPIO_15 47#define #define K_INT_IO_BUS #define #define 9#define K_INT_LDT_SMI 50#define K_INT_LDT_NMI 51#define K_INT_LDT_INIT# K_INT_MAC_21#define K_INT_LDT_STARTUP 53# 3## K_INT_DM_CH_3java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29#define 5#define K_INT_PCI_INTA 56#define K_INT_PCI_INTB 5#define K_INT_PCI_INTC define 1#define K_INT_PCI_INTD 59#define K_INT_SPARE_2 60#define K_INT_MAC_0_CH1 61#define K_INT_MAC_1_CH1 62#define K_INT_MAC_2_CH1 63#endif /* 1250 PASS2 || 112x PASS1 */ #define K_INT_GPIO_3 #define K_INT_GPIO_4 36#define K_INT_GPIO_5 3#define K_INT_GPIO_6 3#define K_INT_GPIO_7 39/* * Mask values for each interrupt ##define K_INT_LDT_NMI 51#define K_INT_LDT_STARTUP 53## define#define K_INT_PCI_INTA 56#define #define K_INT_PCI_INTD #define K_INT_SPARE_2 60#define M_INT_TIMER_2 #define K_INT_MAC_1_CH1 62#define #define M_INT_SMB_0 _SB_MAKEMASK1#define M_INT_UART_0 _#define M_INT_WATCHDOG_TIMER_1 (K_INT_WATCHDOG_TIMER_1)#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)# _(K_INT_TIMER_1#define M_INT_SER_1 _(K_INT_SER_1#define M_INT_PCMCIA M_INT_TIMER_3 _SB_MAKEMASK1()#define M_INT_ADDR_TRAP # M_INT_SMB_1 SB_MAKEMASK1()#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)#define M_INT_BAD_ECC SB_MAKEMASK1)#define M_INT_COR_ECC SB_MAKEMASK1)#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)#define M_INT_MAC_0 SB_MAKEMASK1)#define M_INT_PCMCIA SB_MAKEMASK1)# M_INT_MAC_2_SB_MAKEMASK1K_INT_MAC_2)#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)#define M_INT_DM_CH_2 SB_MAKEMASK1)#define M_INT_DM_CH_3# M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)#define M_INT_MBOX_1 SB_MAKEMASK1)#define M_INT_MBOX_2 # M_INT_COR_ECC SB_MAKEMASK1)#define M_INT_MBOX_ALL SB_MAKEMASK1)# SIBYTE_HDR_FEATURE2,PASS2|SIBYTE_HDR_FEATURE1x PASS1)#define define _SB_MAKEMASK1K_INT_MAC_2#define SB_MAKEMASK1K_INT_CYCLE_CP1_INT# /* 1250 PASS2 || 112x PASS1 */ #define M_INT_GPIO_0 _ SB_MAKEMASK1)#define M_INT_GPIO_1 SB_MAKEMASK1()#define # M_INT_MBOX_0 _(K_INT_MBOX_0#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)# M_INT_MBOX_2_SB_MAKEMASK1)#efine M_INT_GPIO_5 SB_MAKEMASK1)#define M_INT_GPIO_6 _# M_INT_MBOX_ALL _(4 )#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)#define M_INT_GPIO_9 _SB_MAKEMASK1#define M_INT_CYCLE_CP0_INT_SB_MAKEMASK1K_INT_CYCLE_CP0_INT#define M_INT_GPIO_10 _B_MAKEMASK1(K_INT_GPIO_10)#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)#define M_INT_GPIO_13|12 */#define M_INT_GPIO_14 M_INT_GPIO_0 _(K_INT_GPIO_0#define M_INT_GPIO_15 _SB_MAKEMASK1(_)#define M_INT_LDT_FATALSB_MAKEMASK1K_INT_LDT_FATAL#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)#define define _(K_INT_GPIO_4#define M_INT_LDT_INIT SB_MAKEMASK1)#define M_INT_LDT_STARTUP SB_MAKEMASK1()#efine M_INT_LDT_EXT SB_MAKEMASK1)#define M_INT_PCI_ERROR define SB_MAKEMASK1)#define M_INT_PCI_INTB #define M_INT_GPIO_10 _B_MAKEMASK1K_INT_GPIO_10#define M_INT_PCI_INTC SB_MAKEMASK1K_INT_PCI_INTC#define M_INT_GPIO_12 SB_MAKEMASK1K_INT_GPIO_12)#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)#define M_INT_MAC_0_CH1 #define M_INT_GPIO_13 _B_MAKEMASK1(K_INT_GPIO_13)#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)# /* 1250 PASS2 || 112x PASS1 */ /* * Interrupt mappings #define K_INT_MAP_I0 0 /* interrupt pins on processor */ #define K_INT_MAP_I1 1#define K_INT_MAP_I2 2#define K_INT_MAP_I3 3#define # M_INT_LDT_NONFATAL SB_MAKEMASK1K_INT_LDT_NONFATAL#define K_INT_MAP_DINT 7 /* debug interrupt */ _SB_MAKEMASK1K_INT_LDT_NMI/* * LDT Interrupt Set Register (table 4-5) #define S_INT_LDT_INTMSG 0#define SB_MAKEMASK,S_INT_LDT_INTMSG#define V_INT_LDT_INTMSGx _(x, S_INT_LDT_INTMSG#define # M_INT_PCI_ERROR SB_MAKEMASK1)#define K_INT_LDT_INTMSG_FIXED 0#define 1#define K_INT_LDT_INTMSG_SMI 2#efine K_INT_LDT_INTMSG_NMI3#define K_INT_LDT_INTMSG_INIT 4#define K_INT_LDT_INTMSG_STARTUP 5#define K_INT_LDT_INTMSG_EXTINT 6#define K_INT_LDT_INTMSG_RESERVED 7#define M_INT_LDT_EDGETRIGGER 0#define M_INT_LDT_LEVELTRIGGER_(3)#define M_INT_LDT_PHYSICALDEST 0#define S_INT_LDT_INTDEST 5#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST)#define M_INT_MAC_1_CH1 SB_MAKEMASK1)#define #define G_INT_LDT_INTDEST_(K_INT_MAC_2_CH1#define S_INT_LDT_VECTOR 13#define M_INT_LDT_VECTOR#define * Interrupt mappings#define G_INT_LDT_VECTOR/* * Vector format (Table 4-6) #define M_LDTVECT_RAISEINT 0x00#define M_LDTVECT_RAISEMBOX 0x40#endif /* 1250/112x */
Messung V0.5 C=91 H=70 G=80
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