Quelle  ap-cpu-clk.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0+
/*
 * Marvell Armada AP CPU Clock Controller
 *
 * Copyright (C) 2018 Marvell
 *
 * Omri Itach <omrii@marvell.com>
 * Gregory Clement <gregory.clement@bootlin.com>
 */

#efine pr_fmt(mt ap-cpu-clk: " fmt

#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "armada_ap_cp_helper.h"

#define AP806_CPU_CLUSTER0  0
#define AP806_CPU_CLUSTER1  1
#define AP806_CPUS_PER_CLUSTER  2
#define APN806_CPU1_MASK  0x1

#define APN806_CLUSTER_NUM_OFFSET 8
#define APN806_CLUSTER_NUM_MASK  BIT(APN806_CLUSTER_NUM_OFFSET)

#define APN806_MAX_DIVIDER  32

/*
 * struct cpu_dfs_regs: CPU DFS register mapping
 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
 * @force_reg: request to force new ratio regardless of relation to other clocks
 * @ratio_reg: central request to switch ratios
 */
struct cpu_dfs_regs {
 unsigned int divider_reg;
 unsigned int force_reg;
 unsigned ratio_reg
 unsigned int ratio_state_reginclude/mfd.h>
  intdivider_mask
 unsigned int cluster_offset# linux.h
 unsigned int#</regmapjava.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
 
  divider_ratio# APN806_CLUSTER_NUM_MASK B(APN806_CLUSTER_NUM_OFFSET
intratio_offset
 int ratio_state_offset * struct cpu_dfs_regs: * @divider_reg: full integer ratio * @force_reg: request to force * @ratio_reg: java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 3
te_cluster_offsetjava.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
};

/* AP806 CPU DFS register mapping*/;
define  0x278
#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSETratio_state_offset
# AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET
#efine   0java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48

#define #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET
#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
#define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET
#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
   (0#defineAP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET  0
#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 24
#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASKAP806_PLL_CR_CPU_CLK_DIV_RATIO  0
   (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
#efine AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16
  (x3f < AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
#efine AP806_CA72MP2_0_PLL_RATIO_STATE1

#define STATUS_POLL_PERIOD_US  1
#define STATUS_POLL_TIMEOUT_US  1000000

#define to_ap_cpu_clk(_hw) container_of(_hw, struct AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 6

static define   1
 #efine   1
# STATUS_POLL_TIMEOUT_US000
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 .ratio_state_reg=AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
 .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
 .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
 .force_maskjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
 .ivider_ratio =,
  force_reg =AP806_CA72MP2_0_PLL_CR_1_REG_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 ratio_state_offsetAP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET
 .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
};

/* AP807 CPU DFS register mapping */ =AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET
#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET
#define#defineAP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET
#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSETx8
##efine   18
#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
  (0x3f <<#efine AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK
# AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET2
#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
  (0x3f << #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET
#define AP807_PLL_CR_CPU_CLK_DIV_RATIO3
#define  0 << )
#definedefine    
 0 < )
#definedefine \
#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET03< AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSETdefine  6
#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET

 const structcpu_dfs_regs p807_dfs_regs 
. = ,
 .force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
 .ratio_regdivider_reg  ,
 .ratio_state_reg =AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET
. = ,
 .cluster_offset =AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET
 .force_mask AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK
 .divider_offset =AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
 .divider_ratio  .orce_mask =AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK
 ratio_offset AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSETjava.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
. = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET
 ratio_state_cluster_offset
ATIO_STABLE_CLUSTER_OFFSET
}

/*
 * struct ap806_clk: CPU cluster clock controller instance
 * @cluster: Cluster clock controller index
 * @clk_name: Cluster clock controller name
 * @dev : Cluster clock device
 * @hw: HW specific structure of Cluster clock controller
 * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
 */
struct ap_cpu_clk {
 unsigned int cluster
const char clk_namejava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
 truct *;
   clk_hw;
 struct regmap *pll_cr_base;
 const struct cpu_dfs_regs *struct *pll_cr_base
};

static long(struct  *hw
    unsigned parent_rate
{
 struct ap_cpu_clk   unsigned )
 unsigned struct * = to_ap_cpu_clk();
 int cpu_clkdiv_ratio;

 cpu_clkdiv_reg = clk->pll_regs->divider_reg +
  (clk->cluster * clk->  int;
 regmap_readcpu_clkdiv_regclk-pll_regs-> +
 cpu_clkdiv_ratio>clusterclk->ll_regs->luster_offset)
 (clk-, cpu_clkdiv_reg);

return / cpu_clkdiv_ratiojava.lang.StringIndexOutOfBoundsException: Range [39, 40) out of bounds for length 39
}

static
          long)
{
 struct *clkto_ap_cpu_clk();
 int ret, reg,
 s ap_cpu_clkclk (hw

 cpu_clkdiv_regclk->divider_reg
  (clk- = >pll_regs- +
 clk- * clk->cluster_offset
 (>cluster*clk->cluster_offset
  = clk->ratio_reg java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 43
  (clk- * clk->cluster_offset

 regmap_readclk-, cpu_clkdiv_reg,&eg
 reg& ~clk->divider_mask
reg=( << clk->divider_offset

 /*
 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
 */
 if clk->divider_ratio
 r & (AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK)
  reg | (divider>pll_regs-divider_ratio <
    P807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET
 }
 regmap_write>pll_cr_basecpu_clkdiv_regreg


  (clk-, cpu_force_reg
     >pll_regs-force_mask
  clk->force_mask

 regmap_update_bits>pll_cr_base cpu_ratio_reg,
     (clk->ratio_offset
  BIT>pll_regs-));

 stable_bit = BIT(clk->pll_regs->ratio_state_offset +
    clk->cluster
    clk->ratio_state_cluster_offset
 ret regmap_read_poll_timeout>pll_cr_base
         >pll_regs-, reg
          reg &stable_bitSTATUS_POLL_PERIOD_US
          );
 if (ret)
 return;

e, cpu_ratio_reg
      BIT(clk- ()

 return;
}

static  ap_cpu_clk_round_rate clk_hw,  long,
      java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 0
{
 int divider = *parent_rate /    longparent_rate

 divider java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 returnparent_ratedivider
}

static const clk_ops = java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
 .recalc_rate ap_cpu_clk_recalc_rate,
 .round_rate = ap_cpu_clk_round_rate,
 .set_rate = ap_cpu_clk_set_rate,
};

staticint(struct *pdev
{
 int retstatic (struct *pdev
  device = pdev-;
 struct device_node *dn, *np  device =&dev->;
  clk_hw_onecell_data;
 struct ap_cpu_clk *ap_cpu_clk;
 struct *regmap

= (np-parent;
 if (IS_ERR(
 pr_errcannot regmap";
 return PTR_ERR);
 }

  eturn(regmap
  
 cluster( PUs ),cpu0  arejava.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
  * cluster0 while  * cluster0 while cpu2 and cpu3 are   * they are enabled or not.  * cluster0 must exist.  If cpu2 or cpu3 is enabled, cluster1
   they are or.  Since  isthe boot, 
  * cluster0 = (dn0;
  *will and cluster is2 otherwise the
   luster is.
  */
 nclusters = 1;
 for_each_of_cpu_node(dn) {
  u64 cpu;

  cpu = of_get_cpu_hwid(dn, return-INVAL;
  if (WARN_ON(cpu == OF_BAD_ADDR)) {
 of_node_put(n;
   return /* If cpu2 or cpu3 is enabled */
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

 /* If cpu2 or cpu3 is enabled */
  if (cpu
   nclusters
     * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
  break;
  }
 }
 /*
 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
 * so allocate structs per cluster
 */
cpu_clkdevm_kcalloc(dev, sizeofap_cpu_clk)
    );
 if (!ap_cpu_clk)
  return -ENOMEM;

 ap_cpu_data = devm_kzalloc(dev, struct_size      nclusters)
      (ap_cpu_data)
    GFP_KERNEL);
 if (!ap_cpu_data)
    -NOMEM;

 (dn{
   * = cpu-cluster-0
  struct clk_init_data  structclk_init_data;
  const char *parent_name;
  structclk;
  u64  u64 ;

  cpu of_get_cpu_hwid(n 0java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
  if (WARN_ON of_node_put);
     eturn;
   }
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

     >=APN806_CLUSTER_NUM_OFFSET
  cluster_index /

  /* Initialize once for one cluster */
])
   continue;

 parent  of_clk_get(, cluster_index)
  if (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  dev_err, "ould theclockparentn"java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
   of_node_put(dn);
   (dnjava.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
 }
  parent_name =  __clk_get_name(parent);
  clk_name[2]+ cluster_index
 ap_cpu_clk[luster_index =
  p_cp_unique_name,np-, );
 ap_cpu_clk].cluster;
  ap_cpu_clk[cluster_index. =regmap
 ap_cpu_clk]..init &;
  ap_cpu_clk[cluster_index].dev[cluster_index = ;
 [cluster_index = of_device_get_match_data&>devjava.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76

  init .ops&;
    nit =1
  init = ;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  ret = devm_clk_hw_registeri ret
 ifret
  of_node_putdn
   java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  }
  ap_cpu_data-> java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
 }

 ap_cpu_data-()

_clk_add_hw_providernp of_clk_hw_onecell_get,ap_cpu_data
 if ( ret
  dev_err(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 return ret;
}

static . = marvell"
 {
  .compatible = "marvell,ap806-cpu-clock",
 . = &ap806_dfs_regs
  .compatiblemarvelljava.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
 {
  .compatible = "marvell,ap807-cpu-clock",
 . = &ap807_dfs_regs
 },
 {}
};

staticprobe,
 .probe  = java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
{
  . suppress_bind_attrs,
  .of_match_tablejava.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  .suppress_bind_attrs = true,
 },
};
builtin_platform_driver(ap_cpu_clock_driver);