// SPDX-License-Identifier: GPL-2.0 /* * arch/sh/kernel/cpu/sh4a/clock-sh7724.c * * SH7724 clock framework support * * Copyright (C) 2009 Magnus Damm #include <linux/init.h>#include <linux/kernel.h>#include <linux/io.h>#include <linux/clk.h>#include <linux/clkdev.h>#include <linux/sh_clk.h>#include <asm /clock.h>#include <cpu/sh7724.h>/* SH7724 registers */ #define FRQCRA 0xa4150000#define FRQCRB 0xa4150004#define VCLKCR 0xa4150048#define FCLKACR 0xa4150008#define FCLKBCR 0xa415000c#define IRDACLKCR 0xa4150018#define PLLCR 0xa4150024#define MSTPCR0 0xa4150030#define MSTPCR1 0xa4150034#define MSTPCR2 0xa4150038#define SPUCLKCR 0xa415003c#define FLLFRQ 0xa4150050#define LSTATS 0xa4150060/* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = {/* * Default rate for the root input clock, reset this with clk_set_rate() * from the platform code. static struct clk extal_clk = {/* The fll multiplies the 32khz r_clk, may be used instead of extal */ static unsigned long fll_recalc(struct clk *clk)unsigned long mult = 0;unsigned long div = 1;if (__raw_readl(PLLCR) & 0x1000)if (__raw_readl(FLLFRQ) & 0x4000)return (clk->parent->rate * mult) / div;static struct sh_clk_ops fll_clk_ops = {static struct clk fll_clk = {static unsigned long pll_recalc(struct clk *clk)unsigned long mult = 1;if (__raw_readl(PLLCR) & 0x4000)return clk->parent->rate * mult;static struct sh_clk_ops pll_clk_ops = {static struct clk pll_clk = {/* A fixed divide-by-3 block use by the div6 clocks */ static unsigned long div3_recalc(struct clk *clk)return clk->parent->rate / 3;static struct sh_clk_ops div3_clk_ops = {static struct clk div3_clk = {/* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */ struct clk sh7724_fsimcka_clk = {struct clk sh7724_fsimckb_clk = {struct clk sh7724_dv_clki = {static struct clk *main_clks[] = {static void div4_kick(struct clk *clk)unsigned long value;/* set KICK bit in FRQCRA to update hardware setting */ static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };static struct clk_div_mult_table div4_div_mult_table = {static struct clk_div4_table div4_table = {enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };#define DIV4(_reg, _bit, _mask, _flags) \struct clk div4_clks[DIV4_NR] = {enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR };/* Indices are important - they are the actual src selecting values */ static struct clk *common_parent[] = {static struct clk *vclkcr_parent[8] = {static struct clk *fclkacr_parent[] = {static struct clk *fclkbcr_parent[] = {static struct clk div6_clks[DIV6_NR] = {static struct clk mstp_clks[HWBLK_NR] = {static struct clk_lookup lookups[] = {/* main clocks */ "rclk" , &r_clk),"extal" , &extal_clk),"fll_clk" , &fll_clk),"pll_clk" , &pll_clk),"div3_clk" , &div3_clk),/* DIV4 clocks */ "cpu_clk" , &div4_clks[DIV4_I]),"shyway_clk" , &div4_clks[DIV4_SH]),"bus_clk" , &div4_clks[DIV4_B]),"peripheral_clk" , &div4_clks[DIV4_P]),"vpu_clk" , &div4_clks[DIV4_M1]),/* DIV6 clocks */ "video_clk" , &div6_clks[DIV6_V]),"fsia_clk" , &div6_clks[DIV6_FA]),"fsib_clk" , &div6_clks[DIV6_FB]),"irda_clk" , &div6_clks[DIV6_I]),"spu_clk" , &div6_clks[DIV6_S]),/* MSTP clocks */ "tlb0" , &mstp_clks[HWBLK_TLB]),"ic0" , &mstp_clks[HWBLK_IC]),"oc0" , &mstp_clks[HWBLK_OC]),"rs0" , &mstp_clks[HWBLK_RSMEM]),"ilmem0" , &mstp_clks[HWBLK_ILMEM]),"l2c0" , &mstp_clks[HWBLK_L2C]),"fpu0" , &mstp_clks[HWBLK_FPU]),"intc0" , &mstp_clks[HWBLK_INTC]),"sh-dma-engine.0" , &mstp_clks[HWBLK_DMAC0]),"sh0" , &mstp_clks[HWBLK_SHYWAY]),"hudi0" , &mstp_clks[HWBLK_HUDI]),"ubc0" , &mstp_clks[HWBLK_UBC]),"fck" , "sh-tmu.0" , &mstp_clks[HWBLK_TMU0]),"fck" , "sh-tmu.1" , &mstp_clks[HWBLK_TMU1]),"fck" , "sh-cmt-32.0" , &mstp_clks[HWBLK_CMT]),"sh-wdt.0" , &mstp_clks[HWBLK_RWDT]),"sh-dma-engine.1" , &mstp_clks[HWBLK_DMAC1]),"sh-sci.0" , &mstp_clks[HWBLK_SCIF0]),"sh-sci.1" , &mstp_clks[HWBLK_SCIF1]),"sh-sci.2" , &mstp_clks[HWBLK_SCIF2]),"sh-sci.3" , &mstp_clks[HWBLK_SCIF3]),"sh-sci.4" , &mstp_clks[HWBLK_SCIF4]),"sh-sci.5" , &mstp_clks[HWBLK_SCIF5]),"spi_sh_msiof.0" , &mstp_clks[HWBLK_MSIOF0]),"spi_sh_msiof.1" , &mstp_clks[HWBLK_MSIOF1]),"sh_keysc.0" , &mstp_clks[HWBLK_KEYSC]),"rtc0" , &mstp_clks[HWBLK_RTC]),"i2c-sh_mobile.0" , &mstp_clks[HWBLK_IIC0]),"i2c-sh_mobile.1" , &mstp_clks[HWBLK_IIC1]),"sh_mmcif.0" , &mstp_clks[HWBLK_MMC]),"sh7724-ether.0" , &mstp_clks[HWBLK_ETHER]),"atapi0" , &mstp_clks[HWBLK_ATAPI]),"tpu0" , &mstp_clks[HWBLK_TPU]),"irda0" , &mstp_clks[HWBLK_IRDA]),"tsif0" , &mstp_clks[HWBLK_TSIF]),"renesas_usbhs.1" , &mstp_clks[HWBLK_USB1]),"renesas_usbhs.0" , &mstp_clks[HWBLK_USB0]),"usb1" , &mstp_clks[HWBLK_USB1]),"usb0" , &mstp_clks[HWBLK_USB0]),"2dg0" , &mstp_clks[HWBLK_2DG]),"sh_mobile_sdhi.0" , &mstp_clks[HWBLK_SDHI0]),"sh_mobile_sdhi.1" , &mstp_clks[HWBLK_SDHI1]),"veu1" , &mstp_clks[HWBLK_VEU1]),"renesas-ceu.1" , &mstp_clks[HWBLK_CEU1]),"beu1" , &mstp_clks[HWBLK_BEU1]),"2ddmac0" , &mstp_clks[HWBLK_2DDMAC]),"sh_fsi.0" , &mstp_clks[HWBLK_SPU]),"jpu0" , &mstp_clks[HWBLK_JPU]),"sh-vou" , &mstp_clks[HWBLK_VOU]),"beu0" , &mstp_clks[HWBLK_BEU0]),"renesas-ceu.0" , &mstp_clks[HWBLK_CEU0]),"veu0" , &mstp_clks[HWBLK_VEU0]),"vpu0" , &mstp_clks[HWBLK_VPU]),"sh_mobile_lcdc_fb.0" , &mstp_clks[HWBLK_LCDC]),int __init arch_clk_init(void )int k, ret = 0;/* autodetect extal or fll configuration */ if (__raw_readl(PLLCR) & 0x1000)else for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)if (!ret)if (!ret)if (!ret)return ret;
Messung V0.5 C=96 H=96 G=95
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