/* BIOS may enable hardware IRQ balancing for * E7520/E7320/E7525(revision ID 0x9 and below) * based platforms. * Disable SW irqbalance/affinity on those platforms.
*/ if (dev->revision > 0x9) return;
/* * read xTPR register. We may not have a pci_dev for device 8 * because it might be hidden until the above write.
*/
pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
/* put back the original value for config space*/ if (!(config & 0x2))
pci_write_config_byte(dev, 0xf4, config);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
quirk_intel_irqbalance);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
quirk_intel_irqbalance); #endif
/* use bits 31:14, 16 kB aligned */
rcba_base = ioremap(rcba, 0x4000); if (rcba_base == NULL) {
dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " "cannot force enable HPET\n"); return;
}
/* read the Function Disable register, dword mode only */
val = readl(rcba_base + 0x3404);
if (val & 0x80) { /* HPET is enabled in HPTC. Just not reported by BIOS */
val = val & 0x3;
force_hpet_address = 0xFED00000 | (val << 12);
dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " "0x%lx\n", force_hpet_address);
iounmap(rcba_base); return;
}
/* HPET disabled in HPTC. Trying to enable */
writel(val | 0x80, rcba_base + 0x3404);
val = readl(rcba_base + 0x3404); if (!(val & 0x80)) {
err = 1;
} else {
val = val & 0x3;
force_hpet_address = 0xFED00000 | (val << 12);
}
if (err) {
force_hpet_address = 0;
iounmap(rcba_base);
dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
} else {
force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " "0x%lx\n", force_hpet_address);
}
}
pci_read_config_dword(dev, 0xD0, &gen_cntl); /* * Bit 17 is HPET enable bit. * Bit 16:15 control the HPET base address.
*/
val = gen_cntl >> 15;
val &= 0x7; if (val & 0x4) {
val &= 0x3;
force_hpet_address = 0xFED00000 | (val << 12);
dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
force_hpet_address); return;
}
/* * HPET is disabled. Trying enabling at FED00000 and check * whether it sticks
*/
gen_cntl &= (~(0x7 << 15));
gen_cntl |= (0x4 << 15);
pci_write_config_dword(dev, 0xD0, gen_cntl);
pci_read_config_dword(dev, 0xD0, &gen_cntl);
val = gen_cntl >> 15;
val &= 0x7; if (val & 0x4) { /* HPET is enabled in HPTC. Just not reported by BIOS */
val &= 0x3;
force_hpet_address = 0xFED00000 | (val << 12);
dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " "0x%lx\n", force_hpet_address);
cached_dev = dev;
force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; return;
}
dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
}
/* * Undocumented chipset features. Make sure that the user enforced * this.
*/ staticvoid old_ich_force_enable_hpet_user(struct pci_dev *dev)
{ if (hpet_force_user)
old_ich_force_enable_hpet(dev);
}
if (!hpet_force_user) {
hpet_print_force_info(); return;
}
pci_read_config_dword(dev, 0x68, &val); /* * Bit 7 is HPET enable bit. * Bit 31:10 is HPET base address (contrary to what datasheet claims)
*/ if (val & 0x80) {
force_hpet_address = (val & ~0x3ff);
dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
force_hpet_address); return;
}
/* * HPET is disabled. Trying enabling at FED00000 and check * whether it sticks
*/
val = 0xfed00000 | 0x80;
pci_write_config_dword(dev, 0x68, val);
void force_hpet_resume(void)
{ switch (force_hpet_resume_type) { case ICH_FORCE_HPET_RESUME:
ich_force_hpet_resume(); return; case OLD_ICH_FORCE_HPET_RESUME:
old_ich_force_hpet_resume(); return; case VT8237_FORCE_HPET_RESUME:
vt8237_force_hpet_resume(); return; case NVIDIA_FORCE_HPET_RESUME:
nvidia_force_hpet_resume(); return; case ATI_FORCE_HPET_RESUME:
ati_force_hpet_resume(); return; default: break;
}
}
/* * According to the datasheet e6xx systems have the HPET hardwired to * 0xfed00000
*/ staticvoid e6xx_force_enable_hpet(struct pci_dev *dev)
{ if (hpet_address || force_hpet_address) return;
/* * HPET MSI on some boards (ATI SB700/SB800) has side effect on * floppy DMA. Disable HPET MSI on such platforms. * See erratum #27 (Misinterpreted MSI Requests May Result in * Corrupted LPC DMA Data) in AMD Publication #46837, * "SB700 Family Product Errata", Rev. 1.0, March 2010.
*/ staticvoid force_disable_hpet_msi(struct pci_dev *unused)
{
hpet_msi_disable = true;
}
#ifdef CONFIG_PCI /* * Processor does not ensure DRAM scrub read/write sequence * is atomic wrt accesses to CC6 save state area. Therefore * if a concurrent scrub read/write access is to same address * the entry may appear as if it is not written. This quirk * applies to Fam16h models 00h-0Fh * * See "Revision Guide" for AMD F16h models 00h-0fh, * document 51810 rev. 3.04, Nov 2013
*/ staticvoid amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
{
u32 val;
/* * Suggested workaround: * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
*/
pci_read_config_dword(dev, 0x58, &val); if (val & 0x1F) {
val &= ~(0x1F);
pci_write_config_dword(dev, 0x58, val);
}
pci_read_config_dword(dev, 0x5C, &val); if (val & BIT(0)) {
val &= ~BIT(0);
pci_write_config_dword(dev, 0x5c, val);
}
}
/* * CAPID0{7:6} indicate whether this is an advanced RAS SKU * CAPID5{8:5} indicate that various NVDIMM usage modes are * enabled, so memory machine check recovery is also enabled.
*/ if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
enable_copy_mc_fragile();
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