/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2003, 2004 Ralf Baechle * Copyright (C) 2004 Maciej W. Rozycki
*/ #ifndef __ASM_CPU_FEATURES_H #define __ASM_CPU_FEATURES_H
/* * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during * boot (typically by cpu_probe()). * * Note that these should only be used in cases where a kernel built for an * older ISA *cannot* run on a CPU which supports the feature in question. For * example this may be used for features introduced with MIPSr6, since a kernel * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a * MIPSr2 CPU.
*/ #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt))
/* * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during * boot (typically by cpu_probe()). * * These are for use with features that are optional up until a particular ISA * revision & then become required.
*/ #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt))
/* * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during * boot (typically by cpu_probe()). * * These are for use with features that are optional up until a particular ISA * revision & are then removed - ie. no longer present in any CPU implementing * the given ISA revision.
*/ #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt))
/* * Similarly allow for ISA level checks that take into account knowledge of the * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
*/ #define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) #define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) #define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) #define __isa_range(ge, lt) \
((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) #define __isa_range_or_flag(ge, lt, flag) \
(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) #define __isa_range_and_ase(ge, lt, ase) \
(__isa_range(ge, lt) && __ase(ase))
/* * SMP assumption: Options of CPU 0 are a superset of all processors. * This is true for all known MIPS systems.
*/ #ifndef cpu_has_tlb #define cpu_has_tlb __opt(MIPS_CPU_TLB) #endif #ifndef cpu_has_ftlb #define cpu_has_ftlb __opt(MIPS_CPU_FTLB) #endif #ifndef cpu_has_tlbinv #define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) #endif #ifndef cpu_has_segments #define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) #endif #ifndef cpu_has_eva #define cpu_has_eva __opt(MIPS_CPU_EVA) #endif #ifndef cpu_has_htw #define cpu_has_htw __opt(MIPS_CPU_HTW) #endif #ifndef cpu_has_ldpte #define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) #endif #ifndef cpu_has_rixiex #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) #endif #ifndef cpu_has_maar #define cpu_has_maar __opt(MIPS_CPU_MAAR) #endif #ifndef cpu_has_rw_llb #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) #endif
/* * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors * such as the R10000 have I-Caches that snoop local stores; the embedded ones * don't. For maintaining I-cache coherency this means we need to flush the * D-cache all the way back to whever the I-cache does refills from, so the * I-cache has a chance to see the new data at all. Then we have to flush the * I-cache also. * Note we may have been rescheduled and may no longer be running on the CPU * that did the store so we can't optimize this into only doing the flush on * the local CPU.
*/ #ifndef cpu_icache_snoops_remote_store #ifdef CONFIG_SMP #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) #else #define cpu_icache_snoops_remote_store 1 #endif #endif
/* MIPSR2 - MIPSR6 have a lot of similarities */ #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r5 | \
cpu_has_mips_r6)
/* * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor * * Returns non-zero value if the current processor implementation requires * an IHB instruction to deal with an instruction hazard as per MIPS R2 * architecture specification, zero otherwise.
*/ #ifndef cpu_has_mips_r2_exec_hazard #define cpu_has_mips_r2_exec_hazard \
({ \ int __res; \
\ switch (boot_cpu_type()) { \ case CPU_M14KC: \ case CPU_74K: \ case CPU_1074K: \ case CPU_PROAPTIV: \ case CPU_P5600: \ case CPU_M5150: \ case CPU_QEMU_GENERIC: \ case CPU_CAVIUM_OCTEON: \ case CPU_CAVIUM_OCTEON_PLUS: \ case CPU_CAVIUM_OCTEON2: \ case CPU_CAVIUM_OCTEON3: \
__res = 0; \ break; \
\ default: \
__res = 1; \
} \
\
__res; \
}) #endif
/* * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
*/ #ifndef cpu_has_clo_clz #define cpu_has_clo_clz cpu_has_mips_r #endif
/* * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. * This indicates the availability of WSBH and in case of 64 bit CPUs also * DSBH and DSHD.
*/ #ifndef cpu_has_wsbh #define cpu_has_wsbh cpu_has_mips_r2 #endif
#ifdef CONFIG_SMP /* * Some systems share FTLB RAMs between threads within a core (siblings in * kernel parlance). This means that FTLB entries may become invalid at almost * any point when an entry is evicted due to a sibling thread writing an entry * to the shared FTLB RAM. * * This is only relevant to SMP systems, and the only systems that exhibit this * property implement MIPSr6 or higher so we constrain support for this to * kernels that will run on such systems.
*/ # ifndef cpu_has_shared_ftlb_ram # define cpu_has_shared_ftlb_ram \
__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) # endif
/* * Some systems take this a step further & share FTLB entries between siblings. * This is implemented as TLB writes happening as usual, but if an entry * written by a sibling exists in the shared FTLB for a translation which would * otherwise cause a TLB refill exception then the CPU will use the entry * written by its sibling rather than triggering a refill & writing a matching * TLB entry for itself. * * This is naturally only valid if a TLB entry is known to be suitable for use * on all siblings in a CPU, and so it only takes effect when MMIDs are in use * rather than ASIDs or when a TLB entry is marked global.
*/ # ifndef cpu_has_shared_ftlb_entries # define cpu_has_shared_ftlb_entries \
__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) # endif #endif/* SMP */
/* * We only enable MMID support for configurations which natively support 64 bit * atomics because getting good performance from the allocator relies upon * efficient atomic64_*() functions.
*/ #ifndef cpu_has_mmid # ifdef CONFIG_GENERIC_ATOMIC64 # define cpu_has_mmid 0 # else # define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID) # endif #endif
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