/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _gc_9_4_3_OFFSET_HEADER
#define _gc_9_4_3_OFFSET_HEADER
// addressBlock: xcd0_gc_grbmdec
// base address: 0x8000
#define regGRBM_CNTL 0x0000
#define regGRBM_CNTL_BASE_IDX 0
#define regGRBM_SKEW_CNTL 0x0001
#define regGRBM_SKEW_CNTL_BASE_IDX 0
#define regGRBM_STATUS2 0x0002
#define regGRBM_STATUS2_BASE_IDX 0
#define regGRBM_PWR_CNTL 0x0003
#define regGRBM_PWR_CNTL_BASE_IDX 0
#define regGRBM_STATUS 0x0004
#define regGRBM_STATUS_BASE_IDX 0
#define regGRBM_STATUS_SE0 0x0005
#define regGRBM_STATUS_SE0_BASE_IDX 0
#define regGRBM_STATUS_SE1 0x0006
#define regGRBM_STATUS_SE1_BASE_IDX 0
#define regGRBM_SOFT_RESET 0x0008
#define regGRBM_SOFT_RESET_BASE_IDX 0
#define regGRBM_GFX_CLKEN_CNTL 0x000c
#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0
#define regGRBM_WAIT_IDLE_CLOCKS 0x000d
#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0
#define regGRBM_STATUS_SE2 0x000e
#define regGRBM_STATUS_SE2_BASE_IDX 0
#define regGRBM_STATUS_SE3 0x000f
#define regGRBM_STATUS_SE3_BASE_IDX 0
#define regGRBM_READ_ERROR 0x0016
#define regGRBM_READ_ERROR_BASE_IDX 0
#define regGRBM_READ_ERROR2 0x0017
#define regGRBM_READ_ERROR2_BASE_IDX 0
#define regGRBM_INT_CNTL 0x0018
#define regGRBM_INT_CNTL_BASE_IDX 0
#define regGRBM_TRAP_OP 0x0019
#define regGRBM_TRAP_OP_BASE_IDX 0
#define regGRBM_TRAP_ADDR 0x001a
#define regGRBM_TRAP_ADDR_BASE_IDX 0
#define regGRBM_TRAP_ADDR_MSK 0x001b
#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0
#define regGRBM_TRAP_WD 0x001c
#define regGRBM_TRAP_WD_BASE_IDX 0
#define regGRBM_TRAP_WD_MSK 0x001d
#define regGRBM_TRAP_WD_MSK_BASE_IDX 0
#define regGRBM_WRITE_ERROR 0x001f
#define regGRBM_WRITE_ERROR_BASE_IDX 0
#define regGRBM_IOV_ERROR 0x0020
#define regGRBM_IOV_ERROR_BASE_IDX 0
#define regGRBM_CHIP_REVISION 0x0021
#define regGRBM_CHIP_REVISION_BASE_IDX 0
#define regGRBM_GFX_CNTL 0x0022
#define regGRBM_GFX_CNTL_BASE_IDX 0
#define regGRBM_RSMU_CFG 0x0023
#define regGRBM_RSMU_CFG_BASE_IDX 0
#define regGRBM_IH_CREDIT 0x0024
#define regGRBM_IH_CREDIT_BASE_IDX 0
#define regGRBM_PWR_CNTL2 0x0025
#define regGRBM_PWR_CNTL2_BASE_IDX 0
#define regGRBM_UTCL2_INVAL_RANGE_START 0x0026
#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0
#define regGRBM_UTCL2_INVAL_RANGE_END 0x0027
#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0
#define regGRBM_RSMU_READ_ERROR 0x0028
#define regGRBM_RSMU_READ_ERROR_BASE_IDX 0
#define regGRBM_CHICKEN_BITS 0x0029
#define regGRBM_CHICKEN_BITS_BASE_IDX 0
#define regGRBM_FENCE_RANGE0 0x002a
#define regGRBM_FENCE_RANGE0_BASE_IDX 0
#define regGRBM_FENCE_RANGE1 0x002b
#define regGRBM_FENCE_RANGE1_BASE_IDX 0
#define regGRBM_IOV_READ_ERROR 0x002c
#define regGRBM_IOV_READ_ERROR_BASE_IDX 0
#define regGRBM_NOWHERE 0x003f
#define regGRBM_NOWHERE_BASE_IDX 0
#define regGRBM_SCRATCH_REG0 0x0040
#define regGRBM_SCRATCH_REG0_BASE_IDX 0
#define regGRBM_SCRATCH_REG1 0x0041
#define regGRBM_SCRATCH_REG1_BASE_IDX 0
#define regGRBM_SCRATCH_REG2 0x0042
#define regGRBM_SCRATCH_REG2_BASE_IDX 0
#define regGRBM_SCRATCH_REG3 0x0043
#define regGRBM_SCRATCH_REG3_BASE_IDX 0
#define regGRBM_SCRATCH_REG4 0x0044
#define regGRBM_SCRATCH_REG4_BASE_IDX 0
#define regGRBM_SCRATCH_REG5 0x0045
#define regGRBM_SCRATCH_REG5_BASE_IDX 0
#define regGRBM_SCRATCH_REG6 0x0046
#define regGRBM_SCRATCH_REG6_BASE_IDX 0
#define regGRBM_SCRATCH_REG7 0x0047
#define regGRBM_SCRATCH_REG7_BASE_IDX 0
#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0048
#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0
// addressBlock: xcd0_gc_cpdec
// base address: 0x8200
#define regCP_CPC_DEBUG_CNTL 0x0080
#define regCP_CPC_DEBUG_CNTL_BASE_IDX 0
#define regCP_CPF_DEBUG_CNTL 0x0082
#define regCP_CPF_DEBUG_CNTL_BASE_IDX 0
#define regCP_CPC_STATUS 0x0084
#define regCP_CPC_STATUS_BASE_IDX 0
#define regCP_CPC_BUSY_STAT 0x0085
#define regCP_CPC_BUSY_STAT_BASE_IDX 0
#define regCP_CPC_STALLED_STAT1 0x0086
#define regCP_CPC_STALLED_STAT1_BASE_IDX 0
#define regCP_CPF_STATUS 0x0087
#define regCP_CPF_STATUS_BASE_IDX 0
#define regCP_CPF_BUSY_STAT 0x0088
#define regCP_CPF_BUSY_STAT_BASE_IDX 0
#define regCP_CPF_STALLED_STAT1 0x0089
#define regCP_CPF_STALLED_STAT1_BASE_IDX 0
#define regCP_CPC_GRBM_FREE_COUNT 0x008b
#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0
#define regCP_CPC_PRIV_VIOLATION_ADDR 0x008c
#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0
#define regCP_MEC_CNTL 0x008d
#define regCP_MEC_CNTL_BASE_IDX 0
#define regCP_MEC_ME1_HEADER_DUMP 0x008e
#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0
#define regCP_MEC_ME2_HEADER_DUMP 0x008f
#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0
#define regCP_CPC_SCRATCH_INDEX 0x0090
#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0
#define regCP_CPC_SCRATCH_DATA 0x0091
#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0
#define regCP_CPF_GRBM_FREE_COUNT 0x0092
#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0
#define regCP_CPC_HALT_HYST_COUNT 0x00a7
#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0
#define regCP_CE_COMPARE_COUNT 0x00c0
#define regCP_CE_COMPARE_COUNT_BASE_IDX 0
#define regCP_CE_DE_COUNT 0x00c1
#define regCP_CE_DE_COUNT_BASE_IDX 0
#define regCP_DE_CE_COUNT 0x00c2
#define regCP_DE_CE_COUNT_BASE_IDX 0
#define regCP_DE_LAST_INVAL_COUNT 0x00c3
#define regCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
#define regCP_DE_DE_COUNT 0x00c4
#define regCP_DE_DE_COUNT_BASE_IDX 0
#define regCP_STALLED_STAT3 0x019c
#define regCP_STALLED_STAT3_BASE_IDX 0
#define regCP_STALLED_STAT1 0x019d
#define regCP_STALLED_STAT1_BASE_IDX 0
#define regCP_STALLED_STAT2 0x019e
#define regCP_STALLED_STAT2_BASE_IDX 0
#define regCP_BUSY_STAT 0x019f
#define regCP_BUSY_STAT_BASE_IDX 0
#define regCP_STAT 0x01a0
#define regCP_STAT_BASE_IDX 0
#define regCP_ME_HEADER_DUMP 0x01a1
#define regCP_ME_HEADER_DUMP_BASE_IDX 0
#define regCP_PFP_HEADER_DUMP 0x01a2
#define regCP_PFP_HEADER_DUMP_BASE_IDX 0
#define regCP_GRBM_FREE_COUNT 0x01a3
#define regCP_GRBM_FREE_COUNT_BASE_IDX 0
#define regCP_CE_HEADER_DUMP 0x01a4
#define regCP_CE_HEADER_DUMP_BASE_IDX 0
#define regCP_PFP_INSTR_PNTR 0x01a5
#define regCP_PFP_INSTR_PNTR_BASE_IDX 0
#define regCP_ME_INSTR_PNTR 0x01a6
#define regCP_ME_INSTR_PNTR_BASE_IDX 0
#define regCP_CE_INSTR_PNTR 0x01a7
#define regCP_CE_INSTR_PNTR_BASE_IDX 0
#define regCP_MEC1_INSTR_PNTR 0x01a8
#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0
#define regCP_MEC2_INSTR_PNTR 0x01a9
#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0
#define regCP_CSF_STAT 0x01b4
#define regCP_CSF_STAT_BASE_IDX 0
#define regCP_ME_CNTL 0x01b6
#define regCP_ME_CNTL_BASE_IDX 0
#define regCP_CNTX_STAT 0x01b8
#define regCP_CNTX_STAT_BASE_IDX 0
#define regCP_ME_PREEMPTION 0x01b9
#define regCP_ME_PREEMPTION_BASE_IDX 0
#define regCP_ROQ_THRESHOLDS 0x01bc
#define regCP_ROQ_THRESHOLDS_BASE_IDX 0
#define regCP_MEQ_STQ_THRESHOLD 0x01bd
#define regCP_MEQ_STQ_THRESHOLD_BASE_IDX 0
#define regCP_RB2_RPTR 0x01be
#define regCP_RB2_RPTR_BASE_IDX 0
#define regCP_RB1_RPTR 0x01bf
#define regCP_RB1_RPTR_BASE_IDX 0
#define regCP_RB0_RPTR 0x01c0
#define regCP_RB0_RPTR_BASE_IDX 0
#define regCP_RB_RPTR 0x01c0
#define regCP_RB_RPTR_BASE_IDX 0
#define regCP_RB_WPTR_DELAY 0x01c1
#define regCP_RB_WPTR_DELAY_BASE_IDX 0
#define regCP_RB_WPTR_POLL_CNTL 0x01c2
#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0
#define regCP_ROQ1_THRESHOLDS 0x01d5
#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0
#define regCP_ROQ2_THRESHOLDS 0x01d6
#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0
#define regCP_STQ_THRESHOLDS 0x01d7
#define regCP_STQ_THRESHOLDS_BASE_IDX 0
#define regCP_QUEUE_THRESHOLDS 0x01d8
#define regCP_QUEUE_THRESHOLDS_BASE_IDX 0
#define regCP_MEQ_THRESHOLDS 0x01d9
#define regCP_MEQ_THRESHOLDS_BASE_IDX 0
#define regCP_ROQ_AVAIL 0x01da
#define regCP_ROQ_AVAIL_BASE_IDX 0
#define regCP_STQ_AVAIL 0x01db
#define regCP_STQ_AVAIL_BASE_IDX 0
#define regCP_ROQ2_AVAIL 0x01dc
#define regCP_ROQ2_AVAIL_BASE_IDX 0
#define regCP_MEQ_AVAIL 0x01dd
#define regCP_MEQ_AVAIL_BASE_IDX 0
#define regCP_CMD_INDEX 0x01de
#define regCP_CMD_INDEX_BASE_IDX 0
#define regCP_CMD_DATA 0x01df
#define regCP_CMD_DATA_BASE_IDX 0
#define regCP_ROQ_RB_STAT 0x01e0
#define regCP_ROQ_RB_STAT_BASE_IDX 0
#define regCP_ROQ_IB1_STAT 0x01e1
#define regCP_ROQ_IB1_STAT_BASE_IDX 0
#define regCP_ROQ_IB2_STAT 0x01e2
#define regCP_ROQ_IB2_STAT_BASE_IDX 0
#define regCP_STQ_STAT 0x01e3
#define regCP_STQ_STAT_BASE_IDX 0
#define regCP_STQ_WR_STAT 0x01e4
#define regCP_STQ_WR_STAT_BASE_IDX 0
#define regCP_MEQ_STAT 0x01e5
#define regCP_MEQ_STAT_BASE_IDX 0
#define regCP_CEQ1_AVAIL 0x01e6
#define regCP_CEQ1_AVAIL_BASE_IDX 0
#define regCP_CEQ2_AVAIL 0x01e7
#define regCP_CEQ2_AVAIL_BASE_IDX 0
#define regCP_CE_ROQ_RB_STAT 0x01e8
#define regCP_CE_ROQ_RB_STAT_BASE_IDX 0
#define regCP_CE_ROQ_IB1_STAT 0x01e9
#define regCP_CE_ROQ_IB1_STAT_BASE_IDX 0
#define regCP_CE_ROQ_IB2_STAT 0x01ea
#define regCP_CE_ROQ_IB2_STAT_BASE_IDX 0
#define regCP_INT_STAT_DEBUG 0x01f7
#define regCP_INT_STAT_DEBUG_BASE_IDX 0
#define regCP_DEBUG_CNTL 0x01f8
#define regCP_DEBUG_CNTL_BASE_IDX 0
#define regCP_PRIV_VIOLATION_ADDR 0x01fa
#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0
// addressBlock: xcd0_gc_padec
// base address: 0x8800
#define regVGT_VTX_VECT_EJECT_REG 0x022c
#define regVGT_VTX_VECT_EJECT_REG_BASE_IDX 0
#define regVGT_DMA_DATA_FIFO_DEPTH 0x022d
#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0
#define regVGT_DMA_REQ_FIFO_DEPTH 0x022e
#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0
#define regVGT_DRAW_INIT_FIFO_DEPTH 0x022f
#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0
#define regVGT_LAST_COPY_STATE 0x0230
#define regVGT_LAST_COPY_STATE_BASE_IDX 0
#define regVGT_CACHE_INVALIDATION 0x0231
#define regVGT_CACHE_INVALIDATION_BASE_IDX 0
#define regVGT_RESET_DEBUG 0x0232
#define regVGT_RESET_DEBUG_BASE_IDX 0
#define regVGT_STRMOUT_DELAY 0x0233
#define regVGT_STRMOUT_DELAY_BASE_IDX 0
#define regVGT_FIFO_DEPTHS 0x0234
#define regVGT_FIFO_DEPTHS_BASE_IDX 0
#define regVGT_GS_VERTEX_REUSE 0x0235
#define regVGT_GS_VERTEX_REUSE_BASE_IDX 0
#define regVGT_MC_LAT_CNTL 0x0236
#define regVGT_MC_LAT_CNTL_BASE_IDX 0
#define regIA_CNTL_STATUS 0x0237
#define regIA_CNTL_STATUS_BASE_IDX 0
#define regVGT_CNTL_STATUS 0x023c
#define regVGT_CNTL_STATUS_BASE_IDX 0
#define regWD_CNTL_STATUS 0x023f
#define regWD_CNTL_STATUS_BASE_IDX 0
#define regCC_GC_PRIM_CONFIG 0x0240
#define regCC_GC_PRIM_CONFIG_BASE_IDX 0
#define regGC_USER_PRIM_CONFIG 0x0241
#define regGC_USER_PRIM_CONFIG_BASE_IDX 0
#define regWD_QOS 0x0242
#define regWD_QOS_BASE_IDX 0
#define regWD_UTCL1_CNTL 0x0243
#define regWD_UTCL1_CNTL_BASE_IDX 0
#define regWD_UTCL1_STATUS 0x0244
#define regWD_UTCL1_STATUS_BASE_IDX 0
#define regIA_UTCL1_CNTL 0x0246
#define regIA_UTCL1_CNTL_BASE_IDX 0
#define regIA_UTCL1_STATUS 0x0247
#define regIA_UTCL1_STATUS_BASE_IDX 0
#define regVGT_SYS_CONFIG 0x0263
#define regVGT_SYS_CONFIG_BASE_IDX 0
#define regVGT_VS_MAX_WAVE_ID 0x0268
#define regVGT_VS_MAX_WAVE_ID_BASE_IDX 0
#define regVGT_GS_MAX_WAVE_ID 0x0269
#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0
#define regGFX_PIPE_CONTROL 0x026d
#define regGFX_PIPE_CONTROL_BASE_IDX 0
#define regCC_GC_SHADER_ARRAY_CONFIG 0x026f
#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0
#define regGC_USER_SHADER_ARRAY_CONFIG 0x0270
#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0
#define regVGT_DMA_PRIMITIVE_TYPE 0x0271
#define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0
#define regVGT_DMA_CONTROL 0x0272
#define regVGT_DMA_CONTROL_BASE_IDX 0
#define regVGT_DMA_LS_HS_CONFIG 0x0273
#define regVGT_DMA_LS_HS_CONFIG_BASE_IDX 0
#define regWD_BUF_RESOURCE_1 0x0276
#define regWD_BUF_RESOURCE_1_BASE_IDX 0
#define regWD_BUF_RESOURCE_2 0x0277
#define regWD_BUF_RESOURCE_2_BASE_IDX 0
#define regPA_CL_CNTL_STATUS 0x0284
#define regPA_CL_CNTL_STATUS_BASE_IDX 0
#define regPA_CL_ENHANCE 0x0285
#define regPA_CL_ENHANCE_BASE_IDX 0
#define regPA_CL_RESET_DEBUG 0x0286
#define regPA_CL_RESET_DEBUG_BASE_IDX 0
#define regPA_SU_CNTL_STATUS 0x0294
#define regPA_SU_CNTL_STATUS_BASE_IDX 0
#define regPA_SC_FIFO_DEPTH_CNTL 0x0295
#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0
#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0
#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1
#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2
#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
#define regPA_SC_FORCE_EOV_MAX_CNTS 0x02c9
#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0
#define regPA_SC_BINNER_EVENT_CNTL_0 0x02cc
#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0
#define regPA_SC_BINNER_EVENT_CNTL_1 0x02cd
#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0
#define regPA_SC_BINNER_EVENT_CNTL_2 0x02ce
#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0
#define regPA_SC_BINNER_EVENT_CNTL_3 0x02cf
#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0
#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0
#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0
#define regPA_SC_BINNER_PERF_CNTL_0 0x02d1
#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0
#define regPA_SC_BINNER_PERF_CNTL_1 0x02d2
#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0
#define regPA_SC_BINNER_PERF_CNTL_2 0x02d3
#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0
#define regPA_SC_BINNER_PERF_CNTL_3 0x02d4
#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0
#define regPA_SC_ENHANCE_2 0x02dc
#define regPA_SC_ENHANCE_2_BASE_IDX 0
#define regPA_SC_FIFO_SIZE 0x02f3
#define regPA_SC_FIFO_SIZE_BASE_IDX 0
#define regPA_SC_IF_FIFO_SIZE 0x02f5
#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 0
#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8
#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0
#define regPA_UTCL1_CNTL1 0x02f9
#define regPA_UTCL1_CNTL1_BASE_IDX 0
#define regPA_UTCL1_CNTL2 0x02fa
#define regPA_UTCL1_CNTL2_BASE_IDX 0
#define regPA_SIDEBAND_REQUEST_DELAYS 0x02fb
#define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0
#define regPA_SC_ENHANCE 0x02fc
#define regPA_SC_ENHANCE_BASE_IDX 0
#define regPA_SC_ENHANCE_1 0x02fd
#define regPA_SC_ENHANCE_1_BASE_IDX 0
#define regPA_SC_DSM_CNTL 0x02fe
#define regPA_SC_DSM_CNTL_BASE_IDX 0
#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff
#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0
// addressBlock: xcd0_gc_sqdec
// base address: 0x8c00
#define regSQ_CONFIG 0x0300
#define regSQ_CONFIG_BASE_IDX 0
#define regSQC_CONFIG 0x0301
#define regSQC_CONFIG_BASE_IDX 0
#define regLDS_CONFIG 0x0302
#define regLDS_CONFIG_BASE_IDX 0
#define regSQ_RANDOM_WAVE_PRI 0x0303
#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0
#define regSQ_REG_CREDITS 0x0304
#define regSQ_REG_CREDITS_BASE_IDX 0
#define regSQ_FIFO_SIZES 0x0305
#define regSQ_FIFO_SIZES_BASE_IDX 0
#define regSQ_DSM_CNTL 0x0306
#define regSQ_DSM_CNTL_BASE_IDX 0
#define regSQ_DSM_CNTL2 0x0307
#define regSQ_DSM_CNTL2_BASE_IDX 0
#define regSQ_RUNTIME_CONFIG 0x0308
#define regSQ_RUNTIME_CONFIG_BASE_IDX 0
#define regSQ_DEBUG_STS_GLOBAL 0x0309
#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
#define regSH_MEM_BASES 0x030a
#define regSH_MEM_BASES_BASE_IDX 0
#define regSQ_TIMEOUT_CONFIG 0x030b
#define regSQ_TIMEOUT_CONFIG_BASE_IDX 0
#define regSQ_TIMEOUT_STATUS 0x030c
#define regSQ_TIMEOUT_STATUS_BASE_IDX 0
#define regSH_MEM_CONFIG 0x030d
#define regSH_MEM_CONFIG_BASE_IDX 0
#define regSP_MFMA_PORTD_RD_CONFIG 0x030e
#define regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX 0
#define regSH_CAC_CONFIG 0x030f
#define regSH_CAC_CONFIG_BASE_IDX 0
#define regSQ_DEBUG_STS_GLOBAL2 0x0310
#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
#define regSQ_DEBUG_STS_GLOBAL3 0x0311
#define regSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
#define regCC_GC_SHADER_RATE_CONFIG 0x0312
#define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0
#define regGC_USER_SHADER_RATE_CONFIG 0x0313
#define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0
#define regSQ_INTERRUPT_AUTO_MASK 0x0314
#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0
#define regSQ_INTERRUPT_MSG_CTRL 0x0315
#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0
#define regSQ_DEBUG_PERFCOUNT_TRAP 0x0316
#define regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX 0
#define regSQ_UTCL1_CNTL1 0x0317
#define regSQ_UTCL1_CNTL1_BASE_IDX 0
#define regSQ_UTCL1_CNTL2 0x0318
#define regSQ_UTCL1_CNTL2_BASE_IDX 0
#define regSQ_UTCL1_STATUS 0x0319
#define regSQ_UTCL1_STATUS_BASE_IDX 0
#define regSQ_FED_INTERRUPT_STATUS 0x031a
#define regSQ_FED_INTERRUPT_STATUS_BASE_IDX 0
#define regSQ_CGTS_CONFIG 0x031b
#define regSQ_CGTS_CONFIG_BASE_IDX 0
#define regSQ_SHADER_TBA_LO 0x031c
#define regSQ_SHADER_TBA_LO_BASE_IDX 0
#define regSQ_SHADER_TBA_HI 0x031d
#define regSQ_SHADER_TBA_HI_BASE_IDX 0
#define regSQ_SHADER_TMA_LO 0x031e
#define regSQ_SHADER_TMA_LO_BASE_IDX 0
#define regSQ_SHADER_TMA_HI 0x031f
#define regSQ_SHADER_TMA_HI_BASE_IDX 0
#define regSQC_DSM_CNTL 0x0320
#define regSQC_DSM_CNTL_BASE_IDX 0
#define regSQC_DSM_CNTLA 0x0321
#define regSQC_DSM_CNTLA_BASE_IDX 0
#define regSQC_DSM_CNTLB 0x0322
#define regSQC_DSM_CNTLB_BASE_IDX 0
#define regSQC_DSM_CNTL2 0x0325
#define regSQC_DSM_CNTL2_BASE_IDX 0
#define regSQC_DSM_CNTL2A 0x0326
#define regSQC_DSM_CNTL2A_BASE_IDX 0
#define regSQC_DSM_CNTL2B 0x0327
#define regSQC_DSM_CNTL2B_BASE_IDX 0
#define regSQC_DSM_CNTL2E 0x032a
#define regSQC_DSM_CNTL2E_BASE_IDX 0
#define regSQC_EDC_FUE_CNTL 0x032b
#define regSQC_EDC_FUE_CNTL_BASE_IDX 0
#define regSQC_EDC_CNT2 0x032c
#define regSQC_EDC_CNT2_BASE_IDX 0
#define regSQC_EDC_CNT3 0x032d
#define regSQC_EDC_CNT3_BASE_IDX 0
#define regSQC_EDC_PARITY_CNT3 0x032e
#define regSQC_EDC_PARITY_CNT3_BASE_IDX 0
#define regSQ_DEBUG 0x0332
#define regSQ_DEBUG_BASE_IDX 0
#define regSQ_PERF_SNAPSHOT_CTRL 0x0334
#define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0
#define regSQ_DEBUG_FOR_INTERNAL_CTRL 0x0335
#define regSQ_DEBUG_FOR_INTERNAL_CTRL_BASE_IDX 0
#define regSQ_REG_TIMESTAMP 0x0374
#define regSQ_REG_TIMESTAMP_BASE_IDX 0
#define regSQ_CMD_TIMESTAMP 0x0375
#define regSQ_CMD_TIMESTAMP_BASE_IDX 0
#define regSQ_HOSTTRAP_STATUS 0x0376
#define regSQ_HOSTTRAP_STATUS_BASE_IDX 0
#define regSQ_IND_INDEX 0x0378
#define regSQ_IND_INDEX_BASE_IDX 0
#define regSQ_IND_DATA 0x0379
#define regSQ_IND_DATA_BASE_IDX 0
#define regSQ_CONFIG1 0x037a
#define regSQ_CONFIG1_BASE_IDX 0
#define regSQ_CMD 0x037b
#define regSQ_CMD_BASE_IDX 0
#define regSQ_TIME_HI 0x037c
#define regSQ_TIME_HI_BASE_IDX 0
#define regSQ_TIME_LO 0x037d
#define regSQ_TIME_LO_BASE_IDX 0
#define regSQ_DS_0 0x037f
#define regSQ_DS_0_BASE_IDX 0
#define regSQ_DS_1 0x037f
#define regSQ_DS_1_BASE_IDX 0
#define regSQ_EXP_0 0x037f
#define regSQ_EXP_0_BASE_IDX 0
#define regSQ_EXP_1 0x037f
#define regSQ_EXP_1_BASE_IDX 0
#define regSQ_FLAT_0 0x037f
#define regSQ_FLAT_0_BASE_IDX 0
#define regSQ_FLAT_1 0x037f
#define regSQ_FLAT_1_BASE_IDX 0
#define regSQ_GLBL_0 0x037f
#define regSQ_GLBL_0_BASE_IDX 0
#define regSQ_GLBL_1 0x037f
#define regSQ_GLBL_1_BASE_IDX 0
#define regSQ_INST 0x037f
#define regSQ_INST_BASE_IDX 0
#define regSQ_MIMG_0 0x037f
#define regSQ_MIMG_0_BASE_IDX 0
#define regSQ_MIMG_1 0x037f
#define regSQ_MIMG_1_BASE_IDX 0
#define regSQ_MTBUF_0 0x037f
#define regSQ_MTBUF_0_BASE_IDX 0
#define regSQ_MTBUF_1 0x037f
#define regSQ_MTBUF_1_BASE_IDX 0
#define regSQ_MUBUF_0 0x037f
#define regSQ_MUBUF_0_BASE_IDX 0
#define regSQ_MUBUF_1 0x037f
#define regSQ_MUBUF_1_BASE_IDX 0
#define regSQ_SCRATCH_0 0x037f
#define regSQ_SCRATCH_0_BASE_IDX 0
#define regSQ_SCRATCH_1 0x037f
#define regSQ_SCRATCH_1_BASE_IDX 0
#define regSQ_SMEM_0 0x037f
#define regSQ_SMEM_0_BASE_IDX 0
#define regSQ_SMEM_1 0x037f
#define regSQ_SMEM_1_BASE_IDX 0
#define regSQ_SOP1 0x037f
#define regSQ_SOP1_BASE_IDX 0
#define regSQ_SOP2 0x037f
#define regSQ_SOP2_BASE_IDX 0
#define regSQ_SOPC 0x037f
#define regSQ_SOPC_BASE_IDX 0
#define regSQ_SOPK 0x037f
#define regSQ_SOPK_BASE_IDX 0
#define regSQ_SOPP 0x037f
#define regSQ_SOPP_BASE_IDX 0
#define regSQ_VINTRP 0x037f
#define regSQ_VINTRP_BASE_IDX 0
#define regSQ_VOP1 0x037f
#define regSQ_VOP1_BASE_IDX 0
#define regSQ_VOP2 0x037f
#define regSQ_VOP2_BASE_IDX 0
#define regSQ_VOP3P_0 0x037f
#define regSQ_VOP3P_0_BASE_IDX 0
#define regSQ_VOP3P_1 0x037f
#define regSQ_VOP3P_1_BASE_IDX 0
#define regSQ_VOP3P_MFMA_0 0x037f
#define regSQ_VOP3P_MFMA_0_BASE_IDX 0
#define regSQ_VOP3P_MFMA_1 0x037f
#define regSQ_VOP3P_MFMA_1_BASE_IDX 0
#define regSQ_VOP3_0 0x037f
#define regSQ_VOP3_0_BASE_IDX 0
#define regSQ_VOP3_0_SDST_ENC 0x037f
#define regSQ_VOP3_0_SDST_ENC_BASE_IDX 0
#define regSQ_VOP3_1 0x037f
#define regSQ_VOP3_1_BASE_IDX 0
#define regSQ_VOPC 0x037f
#define regSQ_VOPC_BASE_IDX 0
#define regSQ_VOP_DPP 0x037f
#define regSQ_VOP_DPP_BASE_IDX 0
#define regSQ_VOP_SDWA 0x037f
#define regSQ_VOP_SDWA_BASE_IDX 0
#define regSQ_VOP_SDWA_SDST_ENC 0x037f
#define regSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0
#define regSQ_LB_CTR_CTRL 0x0398
#define regSQ_LB_CTR_CTRL_BASE_IDX 0
#define regSQ_LB_DATA0 0x0399
#define regSQ_LB_DATA0_BASE_IDX 0
#define regSQ_LB_DATA1 0x039a
#define regSQ_LB_DATA1_BASE_IDX 0
#define regSQ_LB_DATA2 0x039b
#define regSQ_LB_DATA2_BASE_IDX 0
#define regSQ_LB_DATA3 0x039c
#define regSQ_LB_DATA3_BASE_IDX 0
#define regSQ_LB_CTR_SEL 0x039d
#define regSQ_LB_CTR_SEL_BASE_IDX 0
#define regSQ_LB_CTR0_CU 0x039e
#define regSQ_LB_CTR0_CU_BASE_IDX 0
#define regSQ_LB_CTR1_CU 0x039f
#define regSQ_LB_CTR1_CU_BASE_IDX 0
#define regSQ_LB_CTR2_CU 0x03a0
#define regSQ_LB_CTR2_CU_BASE_IDX 0
#define regSQ_LB_CTR3_CU 0x03a1
#define regSQ_LB_CTR3_CU_BASE_IDX 0
#define regSQC_EDC_CNT 0x03a2
#define regSQC_EDC_CNT_BASE_IDX 0
#define regSQ_EDC_SEC_CNT 0x03a3
#define regSQ_EDC_SEC_CNT_BASE_IDX 0
#define regSQ_EDC_DED_CNT 0x03a4
#define regSQ_EDC_DED_CNT_BASE_IDX 0
#define regSQ_EDC_INFO 0x03a5
#define regSQ_EDC_INFO_BASE_IDX 0
#define regSQ_EDC_CNT 0x03a6
#define regSQ_EDC_CNT_BASE_IDX 0
#define regSQ_EDC_FUE_CNTL 0x03a7
#define regSQ_EDC_FUE_CNTL_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_CMN 0x03b0
#define regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_EVENT 0x03b0
#define regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_INST 0x03b0
#define regSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0
#define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0
#define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_ISSUE 0x03b0
#define regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_MISC 0x03b0
#define regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0
#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0
#define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0
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