/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2020 Invensense, Inc. #ifndef INV_ICM42600_H_#define INV_ICM42600_H_#include <linux/bits.h>#include <linux/bitfield.h>#include <linux/regmap.h>#include <linux/mutex.h>#include <linux/regulator/consumer.h>#include <linux/pm.h>#include <linux/iio/iio.h>#include <linux/iio/common/inv_sensors_timestamp.h>#include "inv_icm42600_buffer.h" enum inv_icm42600_chip {/* serial bus slew rates */ enum inv_icm42600_slew_rate {enum inv_icm42600_sensor_mode {/* gyroscope fullscale values */ enum inv_icm42600_gyro_fs {enum inv_icm42686_gyro_fs {/* accelerometer fullscale values */ enum inv_icm42600_accel_fs {enum inv_icm42686_accel_fs {/* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */ enum inv_icm42600_odr {enum inv_icm42600_filter {/* Low-Noise mode sensor data filter (3rd order filter by default) */ /* Low-Power mode sensor data filter (averaging) */ struct inv_icm42600_sensor_conf {int mode;int fs;int odr;int filter;#define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}struct inv_icm42600_conf {struct inv_icm42600_sensor_conf gyro;struct inv_icm42600_sensor_conf accel;bool temp_en;struct inv_icm42600_suspended {enum inv_icm42600_sensor_mode gyro;enum inv_icm42600_sensor_mode accel;bool temp;struct inv_icm42600_apex {unsigned int on;struct {bool enable;/** * struct inv_icm42600_state - driver state variables * @lock: lock for serializing multiple registers access. * @chip: chip identifier. * @name: chip name. * @map: regmap pointer. * @vdd_supply: VDD voltage regulator for the chip. * @vddio_supply: I/O voltage regulator for the chip. * @irq: chip irq, required to enable/disable and set wakeup * @orientation: sensor chip orientation relative to main hardware. * @conf: chip sensors configurations. * @suspended: suspended sensors configuration. * @indio_gyro: gyroscope IIO device. * @indio_accel: accelerometer IIO device. * @timestamp: interrupt timestamps. * @apex: APEX (Advanced Pedometer and Event detection) management * @fifo: FIFO management structure. * @buffer: data transfer buffer aligned for DMA. struct inv_icm42600_state {struct mutex lock;enum inv_icm42600_chip chip;const char *name;struct regmap *map;struct regulator *vdd_supply;struct regulator *vddio_supply;int irq;struct iio_mount_matrix orientation;struct inv_icm42600_conf conf;struct inv_icm42600_suspended suspended;struct iio_dev *indio_gyro;struct iio_dev *indio_accel;struct {struct inv_icm42600_apex apex;struct inv_icm42600_fifo fifo;/** * struct inv_icm42600_sensor_state - sensor state variables * @scales: table of scales. * @scales_len: length (nb of items) of the scales table. * @power_mode: sensor requested power mode (for common frequencies) * @filter: sensor filter. * @ts: timestamp module states. struct inv_icm42600_sensor_state {const int *scales;enum inv_icm42600_sensor_mode power_mode;enum inv_icm42600_filter filter;struct inv_sensors_timestamp ts;/* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */ /* Bank selection register, available in all banks */ #define INV_ICM42600_REG_BANK_SEL 0x76#define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0)/* User bank 0 (MSB 0x00) */ #define INV_ICM42600_REG_DEVICE_CONFIG 0x0011#define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0)#define INV_ICM42600_REG_DRIVE_CONFIG 0x0013#define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3)#define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) \#define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0)#define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) \#define INV_ICM42600_REG_INT_CONFIG 0x0014#define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5)#define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4)#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3)#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW 0x00#define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2)#define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1)#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0)#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW 0x00#define INV_ICM42600_REG_FIFO_CONFIG 0x0016#define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6)#define INV_ICM42600_FIFO_CONFIG_BYPASS \#define INV_ICM42600_FIFO_CONFIG_STREAM \#define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL \/* all sensor data are 16 bits (2 registers wide) in big-endian */ #define INV_ICM42600_REG_TEMP_DATA 0x001D#define INV_ICM42600_REG_ACCEL_DATA_X 0x001F#define INV_ICM42600_REG_ACCEL_DATA_Y 0x0021#define INV_ICM42600_REG_ACCEL_DATA_Z 0x0023#define INV_ICM42600_REG_GYRO_DATA_X 0x0025#define INV_ICM42600_REG_GYRO_DATA_Y 0x0027#define INV_ICM42600_REG_GYRO_DATA_Z 0x0029#define INV_ICM42600_DATA_INVALID -32768#define INV_ICM42600_REG_INT_STATUS 0x002D#define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6)#define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5)#define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4)#define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3)#define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2)#define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1)#define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0)/* * FIFO access registers * FIFO count is 16 bits (2 registers) big-endian * FIFO data is a continuous read register to read FIFO content #define INV_ICM42600_REG_FIFO_COUNT 0x002E#define INV_ICM42600_REG_FIFO_DATA 0x0030#define INV_ICM42600_REG_INT_STATUS2 0x0037#define INV_ICM42600_INT_STATUS2_SMD_INT BIT(3)#define INV_ICM42600_INT_STATUS2_WOM_INT GENMASK(2, 0)#define INV_ICM42600_REG_INT_STATUS3 0x0038#define INV_ICM42600_INT_STATUS3_STEP_DET_INT BIT(5)#define INV_ICM42600_INT_STATUS3_STEP_CNT_OVF_INT BIT(4)#define INV_ICM42600_INT_STATUS3_TILT_DET_INT BIT(3)#define INV_ICM42600_INT_STATUS3_WAKE_INT BIT(2)#define INV_ICM42600_INT_STATUS3_SLEEP_INT BIT(1)#define INV_ICM42600_INT_STATUS3_TAP_DET_INT BIT(0)#define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6)#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5)#define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3)#define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2)#define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1)/* default configuration: all data big-endian and fifo count in bytes */ #define INV_ICM42600_REG_INTF_CONFIG0 0x004C#define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7)#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6)#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5)#define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4)#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0)#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS \#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS \#define INV_ICM42600_REG_INTF_CONFIG1 0x004D#define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3)#define INV_ICM42600_REG_PWR_MGMT0 0x004E#define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5)#define INV_ICM42600_PWR_MGMT0_IDLE BIT(4)#define INV_ICM42600_PWR_MGMT0_GYRO(_mode) \#define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) \#define INV_ICM42600_REG_GYRO_CONFIG0 0x004F#define INV_ICM42600_GYRO_CONFIG0_FS(_fs) \#define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) \#define INV_ICM42600_REG_ACCEL_CONFIG0 0x0050#define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) \#define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) \#define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 0x0052#define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) \#define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) \#define INV_ICM42600_REG_TMST_CONFIG 0x0054#define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0)#define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4)#define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3)#define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2)#define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1)#define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0)#define INV_ICM42600_REG_SMD_CONFIG 0x0057#define INV_ICM42600_SMD_CONFIG_WOM_INT_MODE BIT(3)#define INV_ICM42600_SMD_CONFIG_WOM_MODE BIT(2)#define INV_ICM42600_SMD_CONFIG_SMD_MODE_OFF 0x00#define INV_ICM42600_SMD_CONFIG_SMD_MODE_WOM 0x01#define INV_ICM42600_SMD_CONFIG_SMD_MODE_SHORT 0x02#define INV_ICM42600_SMD_CONFIG_SMD_MODE_LONG 0x03#define INV_ICM42600_REG_FIFO_CONFIG1 0x005F#define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6)#define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5)#define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3)#define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2)#define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1)#define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0)/* FIFO watermark is 16 bits (2 registers wide) in little-endian */ #define INV_ICM42600_REG_FIFO_WATERMARK 0x0060#define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) \/* FIFO is 2048 bytes, let 12 samples for reading latency */ #define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16)#define INV_ICM42600_REG_INT_CONFIG1 0x0064#define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6)#define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5)#define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4)#define INV_ICM42600_REG_INT_SOURCE0 0x0065#define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6)#define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5)#define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4)#define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3)#define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2)#define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1)#define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0)#define INV_ICM42600_REG_INT_SOURCE1 0x0066#define INV_ICM42600_INT_SOURCE1_I3C_ERROR_INT1_EN BIT(6)#define INV_ICM42600_INT_SOURCE1_SMD_INT1_EN BIT(3)#define INV_ICM42600_INT_SOURCE1_WOM_INT1_EN GENMASK(2, 0)#define INV_ICM42600_REG_WHOAMI 0x0075#define INV_ICM42600_WHOAMI_ICM42600 0x40#define INV_ICM42600_WHOAMI_ICM42602 0x41#define INV_ICM42600_WHOAMI_ICM42605 0x42#define INV_ICM42600_WHOAMI_ICM42686 0x44#define INV_ICM42600_WHOAMI_ICM42622 0x46#define INV_ICM42600_WHOAMI_ICM42688 0x47#define INV_ICM42600_WHOAMI_ICM42631 0x5C/* User bank 1 (MSB 0x10) */ #define INV_ICM42600_REG_SENSOR_CONFIG0 0x1003#define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5)#define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4)#define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3)#define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2)#define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1)#define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0)/* Timestamp value is 20 bits (3 registers) in little-endian */ #define INV_ICM42600_REG_TMSTVAL 0x1062#define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0)#define INV_ICM42600_REG_INTF_CONFIG4 0x107A#define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6)#define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1)#define INV_ICM42600_REG_INTF_CONFIG6 0x107C#define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0)#define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4)#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3)#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2)#define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1)#define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0)/* User bank 4 (MSB 0x40) */ #define INV_ICM42600_REG_ACCEL_WOM_X_THR 0x404A#define INV_ICM42600_REG_ACCEL_WOM_Y_THR 0x404B#define INV_ICM42600_REG_ACCEL_WOM_Z_THR 0x404C#define INV_ICM42600_REG_INT_SOURCE8 0x404F#define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5)#define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4)#define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3)#define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2)#define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1)#define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0)#define INV_ICM42600_REG_OFFSET_USER0 0x4077#define INV_ICM42600_REG_OFFSET_USER1 0x4078#define INV_ICM42600_REG_OFFSET_USER2 0x4079#define INV_ICM42600_REG_OFFSET_USER3 0x407A#define INV_ICM42600_REG_OFFSET_USER4 0x407B#define INV_ICM42600_REG_OFFSET_USER5 0x407C#define INV_ICM42600_REG_OFFSET_USER6 0x407D#define INV_ICM42600_REG_OFFSET_USER7 0x407E#define INV_ICM42600_REG_OFFSET_USER8 0x407F/* Sleep times required by the driver */ #define INV_ICM42600_POWER_UP_TIME_MS 100#define INV_ICM42600_RESET_TIME_MS 1#define INV_ICM42600_ACCEL_STARTUP_TIME_MS 20#define INV_ICM42600_GYRO_STARTUP_TIME_MS 60#define INV_ICM42600_GYRO_STOP_TIME_MS 150#define INV_ICM42600_TEMP_STARTUP_TIME_MS 14#define INV_ICM42600_SUSPEND_DELAY_MS 2000typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *);extern const struct regmap_config inv_icm42600_regmap_config;extern const struct regmap_config inv_icm42600_spi_regmap_config;extern const struct dev_pm_ops inv_icm42600_pm_ops;const struct iio_mount_matrix *const struct iio_dev *indio_dev,const struct iio_chan_spec *chan);enum inv_icm42600_odr odr);int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st,struct inv_icm42600_sensor_conf *conf,unsigned int *sleep_ms);int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st,struct inv_icm42600_sensor_conf *conf,unsigned int *sleep_ms);int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable,unsigned int *sleep_ms);int inv_icm42600_enable_wom(struct inv_icm42600_state *st);int inv_icm42600_disable_wom(struct inv_icm42600_state *st);int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg,unsigned int writeval, unsigned int *readval);int inv_icm42600_core_probe(struct regmap *regmap, int chip,struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st);int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev);struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st);int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev);void inv_icm42600_accel_handle_events(struct iio_dev *indio_dev,unsigned int status2, unsigned int status3,#endif
Messung V0.5 C=96 H=100 G=97
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