/* * The OLPC XO-1.75 and XO-4 laptops do not have a hardware PS/2 controller. * Instead, the OLPC firmware runs a bit-banging PS/2 implementation on an * otherwise-unused slow processor which is included in the Marvell MMP2/MMP3 * SoC, known as the "Security Processor" (SP) or "Wireless Trusted Module" * (WTM). This firmware then reports its results via the WTM registers, * which we read from the Application Processor (AP, i.e. main CPU) in this * driver. * * On the hardware side we have a PS/2 mouse and an AT keyboard, the data * is multiplexed through this system. We create a serio port for each one, * and demultiplex the data accordingly.
*/
/* * The upper byte of SECURE_PROCESSOR_COMMAND and COMMAND_RETURN_STATUS is * used to identify which port (device) is being talked to. The lower byte * is the data being sent/received.
*/ #define PORT_MASK 0xff00 #define DATA_MASK 0x00ff #define PORT_SHIFT 8 #define KEYBOARD_PORT 0 #define TOUCHPAD_PORT 1
/* COMMAND_FIFO_STATUS */ #define CMD_CNTR_MASK 0x7 /* Number of pending/unprocessed commands */ #define MAX_PENDING_CMDS 4 /* from device specs */
if (port == priv->padio)
which = TOUCHPAD_PORT << PORT_SHIFT; else
which = KEYBOARD_PORT << PORT_SHIFT;
dev_dbg(priv->dev, "olpc_apsp_write which=%x val=%x\n", which, val); for (i = 0; i < 50; i++) {
u32 sts = readl(priv->base + COMMAND_FIFO_STATUS); if ((sts & CMD_CNTR_MASK) < MAX_PENDING_CMDS) {
writel(which | val,
priv->base + SECURE_PROCESSOR_COMMAND); return 0;
} /* SP busy. This has not been seen in practice. */
mdelay(1);
}
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.