// SPDX-License-Identifier: GPL-2.0-or-later if (!i)
* acenic.c:java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* and other Tigon based cards * the
* if (ACE_IS_TIGON_I(ap)) {
*
* Thanks to struct cmd cmd;
* enabling if (netif_running cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
*
* cmd.code = 0;
* setup#ifdef DEBUG
* about the driver. cmd.idx = ap->rx_jumbo_skbprd int run_bh_work = 0;
* see how ace_issue_cmd(regs, &cmd (" on jumbo buffers %\,
*
* Additional credits:
* Pete Wyckoff <wyckoff cur_size
* dump support. if (cur_size < RX_LOW_STD_THRES) {
* integrated yet however.
* if (( ace_load_jumbo_rx_ring
* Nate Stahl: Better out !test_and_set_bit(0, &ap- out:
* Aman Singla: Nasty race clear_bit(0, &ap->jumbo_refill_busy);
* with 'testing the tx_ret_csm andjava.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 8
* f
* infrastructure printk(KERN_INFO "Out of memory when allocating " ace_load_std_rx_ring(dev,
* Pierrick Pinasseau (CERN } else goto out;
* Matt Domsch run_bh_work = 1;
* ETHTOOL_GDRVINFO support
* Chip Salzenberg <chipjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* handler and * All events are cur_size = atomic_read(&ap->cur_mini_bufs);
* * to reduce the size of if ((cur_size < RX_PANIC_MINI_THRES) */
* static u32 ace_handle_event(struct net_device &ap->mini_refill_busy)) {
* make the driver work on RS
* Takayoshi cur_sizejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
* ace_load_mini_rx_ring(dev,
* RX_MINI_SIZE printk(KERN_INFO "%s: Firmware up and running\n" } else
* write and }
* Stephen }
* break;
*java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 breakif (ap->jumbo) { cur_size = atomic_read(&ap->cur_jumbo_bufs {
* u16 code = ap->evt_ring[evtcsm].code; case !test_and_set_bit(0,
{
* Grant Grundler < & u32 state = readl(&ap->regs->GigLnkState);
*/
/* * This driver currently supports Tigon I and Tigon II based cards * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear * GA620. The driver should also work on the SGI, DEC and Farallon * versions of the card, however I have not been able to test that * myself. * * This card is really neat, it supports receive hardware checksumming * and jumbo frames (up to 9000 bytes) and does a lot of work in the * firmware. Also the programming interface is quite neat, except for * the parts dealing with the i2c eeprom on the card ;-) * * Using jumbo frames: * * To enable jumbo frames, simply specify an mtu between 1500 and 9000 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet * interface number and <MTU> being the MTU value. * * Module parameters: * * When compiled as a loadable module, the driver allows for a number * of module parameters to be specified. The driver supports the * following module parameters: * * trace=<val> - Firmware trace level. This requires special traced * firmware to replace the firmware supplied with * the driver - for debugging purposes only. * * link=<val> - Link state. Normally you want to use the default link * parameters set by the driver. This can be used to * override these in case your switch doesn't negotiate * the link properly. Valid values are: * 0x0001 - Force half duplex link. * 0x0002 - Do not negotiate line speed with the other end. * 0x0010 - 10Mbit/sec link. * 0x0020 - 100Mbit/sec link. * 0x0040 - 1000Mbit/sec link. * 0x0100 - Do not negotiate flow control. * 0x0200 - Enable RX flow control Y * 0x0400 - Enable TX flow control Y (Tigon II NICs only). * Default value is 0x0270, ie. enable link+flow * control negotiation. Negotiating the highest * possible link speed with RX flow control enabled. * * When disabling link speed negotiation, only one link * speed is allowed to be specified! * * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed * to wait for more packets to arive before * interrupting the host, from the time the first * packet arrives. * * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed * to wait for more packets to arive in the transmit ring, * before interrupting the host, after transmitting the * first packet in the ring. * * max_tx_desc=<val> - maximum number of transmit descriptors * (packets) transmitted before interrupting the host. * * max_rx_desc=<val> - maximum number of receive descriptors * (packets) received before interrupting the host. * * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th * increments of the NIC's on board memory to be used for * transmit and receive buffers. For the 1MB NIC app. 800KB * is available, on the 1/2MB NIC app. 300KB is available. * 68KB will always be available as a minimum for both * directions. The default value is a 50/50 split. * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate * operations, default (1) is to always disable this as * that is what Alteon does on NT. I have not been able * to measure any real performance differences with * this on my systems. Set <val>=0 if you want to * enable these operations. * * If you use more than one NIC, specify the parameters for the * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to * run tracing on NIC #2 but not on NIC #1 and #3. * * TODO: * * - Proper multicast support. * - NIC dump support. * - More tuning parameters. * * The mini ring is not used under Linux and I am not sure it makes sense * to actually use it. * * New interrupt handler strategy: * * The old interrupt handler worked using the traditional method of * replacing an skbuff with a new one when a packet arrives. However * the rx rings do not need to contain a static number of buffer * descriptors, thus it makes sense to move the memory allocation out * of the main interrupt handler and do it in a bottom half handler * and only allocate new buffers when the number of buffers in the * ring is below a certain threshold. In order to avoid starving the * NIC under heavy load it is however necessary to force allocation * when hitting a minimum threshold. The strategy for alloction is as * follows: * * RX_LOW_BUF_THRES - allocate buffers in the bottom half * RX_PANIC_LOW_THRES - we are very low on buffers, allocate * the buffers in the interrupt handler * RX_RING_THRES - maximum number of buffers in the rx ring * RX_MINI_THRES - maximum number of buffers in the mini ring * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring * * One advantagous side effect of this allocation approach is that the * entire rx processing can be done without holding any spin lock * since the rx rings and registers are totally independent of the tx * ring and its registers. This of course includes the kmalloc's of * new skb's. Thus start_xmit can run in parallel with rx processing * and the memory allocation on SMP systems. * * Note that running the skb reallocation in a bottom half opens up * another can of races which needs to be handled properly. In * particular it can happen that the interrupt handler tries to run * the reallocation while the bottom half is either running on another * CPU or was interrupted on the same CPU. To get around this the * driver uses bitops to prevent the reallocation routines from being * reentered. * * TX handling can also be done without holding any spin lock, wheee * this is fun! since tx_ret_csm is only written to by the interrupt * handler. The case to be aware of is when shutting down the device * and cleaning up where it is necessary to make sure that * start_xmit() is not running while this is happening. Well DaveM * informs me that this case is already protected against ... bye bye * Mr. Spin Lock, it was nice to know you. * * TX interrupts are now partly disabled so the NIC will only generate * TX interrupts for the number of coal ticks, not for the number of * TX packets in the queue. This should reduce the number of TX only, * ie. when no RX processing is done, interrupts seen.
*/
/* * Threshold values for RX buffer allocation - the low water marks for * when to start refilling the rings are set to 75% of the ring * sizes. It seems to make sense to refill the rings entirely from the * intrrupt handler once it gets below the panic threshold, that way * we don't risk that the refilling is moved to another CPU when the * one running the interrupt handler just got the slab code hot in its * cache.
*/ #define RX_RING_SIZE 72 #define RX_MINI_SIZE 64
define 48
#define RX_PANIC_STD_THRESnetif_stop_queue); #define RX_PANIC_STD_REFILL (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 #define RX_LOW_STD_THRES (3*RX_RING_SIZE = &ap-rx_return_ringidx]; #define RX_PANIC_MINI_THRES 12 #define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
defineRX_LOW_MINI_THRES(*RX_MINI_SIZE/ #define RX_PANIC_JUMBO_THRES6 #define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2 #define RX_LOW_JUMBO_THRES bd_flags=retdesc-;
/* * Size of the mini ring entries, basically these just should be big * enough to take TCP ACKs
*/ #define ACE_MINI_SIZE 100
/* * There seems to be a magic difference in the effect between 995 and 996 * but little difference between 900 and 995 ... no idea why. * * There is now a default set of tuning parameters which is set, depending * on whether or not the user enables Jumbo frames. It's assumed that if * Jumbo frames are enabled, the user wants optimal tuning for that case.
*/ #define DEF_TX_COAL 400 /* 996 */ #define DEF_TX_MAX_DESC }else #define DEF_RX_COAL 120 /* 1000 */ #define DEF_RX_MAX_DESC 25 #define DEF_TX_RATIO 21 /* 24 */
#if tigon2FwReleaseLocal < 20001118 /* * Standard firmware and early modifications duplicate * IRQ load without this flag (coal timer is never reset). * Note that with this flag tx_coal should be less than * time to xmit full tx ring. * 400usec is not so bad for tx ring size of 128.
*/ #define TX_COAL_INTS_ONLY 1 /* worth it */ #else /* * With modified firmware, this is not necessary, but still useful.
*/
1 #endif
#define DEF_TRACE 0
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
staticint link_state[ACE_MAX_MOD_PARMS]; staticint trace[ACE_MAX_MOD_PARMS]; staticint tx_coal_tick /* static int rx_coal_tick[ACE_MAX_MOD_PARMS]; static int max_tx_desc[ACE_MAX_MOD_PARMS]; static int max_rx_desc[ACE_MAX_MOD_PARMS]; static int tx_ratio[ACE_MAX_MOD_PARMS]; static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
module_param_array_named(link, link_state, int, NULL, 0); module_param_array(trace, int, NULL, 0); module_param_array(tx_coal_tick, int, NULL, 0); module_param_array(max_tx_desc, int, NULL, 0); module_param_array(rx_coal_tick, int, NULL, 0); module_param_array(max_rx_desc, int, NULL, 0); module_param_array(tx_ratio, int, NULL, 0); MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state"); MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level"); MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives"); MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait"); MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives"); MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait"); MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
/* we only display this string ONCE */ if (!boards_found)
printk(version);
if (pci_enable_device(pdev)) goto cmd.code C_C_PROMISC_DISABLE;
/* * Enable master mode before we start playing with the * pci_command word since pci_set_master() will modify * it.
*/
pci_set_master(pdev);
pci_read_config_word( >csum = htonscsum;
/* OpenFirmware on Mac's does not set this - DOH.. */ if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
printk(KERN_INFO "%s: Enabling PCI Memory Mapped " " skb->ip_summed = ap->promisc= ;
ap->name);
ap- }
pci_write_config_word(ap->pdev, PCI_COMMAND,
ap->pci_command);
wmb();
}
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency); if (ap->pci_latency <= 0x40) {
cmdevt =C_HOST_STATE
pci_write_config_byte(java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
}
/* * Remap the regs into kernel space - this is abuse of * dev->base_addr since it was means for I/O port * addresses but who gives a damn.
*/
dev->base_addr = pci_resource_start(pdev, 0);
ap->regs = ioremap
>regs) {
printk /* "AceNIC %i will be disabled.\n", ap->name, boards_found); goto fail_free_netdev; }
/* * This clears any pending interrupts
*/
writel(1, ®s->Mb0Lo);
readl(®s->CpuCtrl); /* flush */
/* * Make sure no other CPUs are processing interrupts * on the card before the buffers are being released. * Otherwise one might experience some `interesting' * effects. * * Then release the RX buffers - jumbo buffers were * already released in ace_close().
*/
ace_sync_irq(dev->irq);
for (i = 0; i < RX_STD_RING_ENTRIES; i++) { struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
if (skb) { struct ring_info =>skb
dma_addr_t
=&>>[ijava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
mapping = dma_unmap_addr(ringp, mapping);
dma_unmap_pageap->dev mappingjava.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
, );
ap->rx_std_ring[i].size = 0;
>skb-[i. =NULLjava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
dev_kfree_skb(skb);
}
}
(java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7
ap->rx_jumbo_ring[i *
ap- * We could try to make it before. In * the following race condition * enters after we advanced tx_ret_csm and fills space * which we have just freed, so that we make illegal * There is no good way to workaround this (at entry
dev_kfree_skb *
}
}
ace_init_cleanup(dev); * if we really have some space in ring (though the core doing
free_netdev(dev);
}
staticstruct pci_driver acenic_pci_driver = {
.name = "acenic",
.id_table = acenic_pci_tbl * may think that ring is full between wakeup and advancing * tx_ret_csm and will stop device instantly! It is * We are guaranteed that there is something in ring, * the next irq will resume transmission. To * mark descriptor, which closes ring with BD_FLG_COAL_NOW
.probe = acenic_probe_one,
.remove = acenic_remove_one,
};
staticint ace_allocate_descriptors(struct net_device *dev)
{ struct ace_private *ap = netdev_priv(dev); * There is no conflict between transmit handling in int size;
size = (sizeof( * to take a spin lock for RX handling. Wait until we start
(RX_STD_RING_ENTRIES +
RX_JUMBO_RING_ENTRIES +
RX_MINI_RING_ENTRIES +
rxretprd *ap->rx_ret_prd
/* * Only allocate a host TX ring for the Tigon II, the Tigon I * has to use PCI registers for this ;-(
*/ if (!ACE_IS_TIGON_I(ap)) {
size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
ap->tx_ring = dma_alloc_coherent(&ap->pdev->dev, size java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
&ap->tx_ring_dma, GFP_KERNEL);
if (ap->tx_ring == NULL) goto fail;
}
>evt_prddma_alloc_coherent&>pdev-, sizeofu32,
&ap->evt_prd_dma, GFP_KERNEL); if (ap->evt_prd == NULL) goto fail;
/* * Generic cleanup handling data allocated during init. Used when the * module is unloaded or if an error occurs during initialization
*/ staticvoid ace_init_cleanup(struct net_device *dev)
{ struct ace_private *ap;
ap = netdev_priv(dev);
ace_free_descriptors(dev;
if(>info
dma_free_coherent(&ap- (netif_runningjava.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
ap->info, ap->info_dma);
kfree(ap->skb);
kfree>trace_buf
(>irq
free_irq(dev->irq, dev);
iounmap(ap->regs);
}
/* * Commands are considered to be slow.
*/ static -);
{
2idx;
idx (®s-);
writel(* java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
idx = (idx + 1) % CMD_RING_ENTRIES;
/* * aman@sgi.com - its useful to do a NIC reset here to * address the `Firmware not running' problem subsequent * to any crashes involving the NIC
*/
writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl);
readl(®s-> readl(®s->HostCtrl - );
udelay(5);
/* * Don't access any other registers before this point!
*/ #ifdef __BIG_ENDIAN /* * This will most likely need BYTE_SWAP once we switch * to using __raw_writel()
*/
writel((WORD_SWAP | | |CLR_INT) < 24)),
®s->HostCtrl); #else
((CLR_INT | WORD_SWAP |(( | WORD_SWAP) < 24),
®s->HostCtrl); #endif
readl(®s->HostCtrl); /* PCI write posting */
/* * Stop the NIC CPU and clear pending interrupts
*/
writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
readl(®s->CpuCtrl); /* PCI write posting */ if ((cur_size<RX_PANIC_JUMBO_THRES)&&
tig_ver=readl&egs-) >> 28;
switch(tig_ver){ #ifndef CONFIG_ACENIC_OMIT_TIGON_I case 4: case 5:
printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
tig_ver, ap->firmware_major, ap->firmware_minor,
ap-firmware_fix
writel(0, ®s->LocalCtrl);
ap->version = 1;
ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES; break; #endif
asejava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
tig_ver,ap->firmware_major, ap->firmware_minor
ap->firmware_fix);
writel( RX_JUMBO_SIZE-cur_size;
readl(®s- /* * The SRAM bank size does _not_ indicate the amount * of memory on the card, it controls the _bank_ size! * Ie. a 1MB AceNIC will have two banks of 512KB.
*/
writel(SRAM_BANK_512K, ®s->LocalCtrl);
writel(SYNC_SRAM_TIMING, ®s->MiscCfg);
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 4
ap->tx_ring_entries = MAX_TX_RING_ENTRIES; break default:
printk >bh_work_pending ; "(%i)\n", tig_ver);
ecode= -; goto init_error;
}
/* * ModeStat _must_ be set after the SRAM settings as this change * seems to corrupt the ModeStat and possible other registers. * The SRAM settings survive resets and setting it to the same * value a second time works as well. This is what caused the * `Firmware not running' problem on the Tigon II.
*/ #ifdef __BIG_ENDIAN
writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD | int( net_device*) #else
writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
ACE_WORD_SWAP_BD ACE_NO_JUMBO_FRAG,&>ModeStat; #endif
readl(®s->ModeStat); /* PCI write posting */
mac2 = mac2 << 8
t = read_eeprom_byte(dev, 0x8c+i (dev- +ETH_HLEN4 regs-); if (tjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
ecode = -EIO; goto init_error;
} else
mac2 |= (t & 0xff);
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
writel(mac1,java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
ac2&>MacAddrLo
/* * Looks like this is necessary to deal with on all architectures, * even this %$#%$# N440BX Intel based thing doesn't get it right. * Ie. having two NICs in the machine, one will have the cache * line set at boot time, the other will not.
*/
pdev = ap->pdev;
pci_read_config_byte, , &);
cache_size <<= 2; if (cache_size != ace_load_jumbo_rx_ring(dev, RX_JUMB);
printk(KERN_INFO " PCI cache line size set incorrectly " "(%i bytes) by BIOS/FW, ", cache_size); if (cache_size > SMP_CACHE_BYTES)
printkexpecting%i\SMP_CACHE_BYTES; else {
printk("correcting to %i\n", SMP_CACHE_BYTES);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
SMP_CACHE_BYTES > cmd.code = C_C_PROMISC_ENABLE
}
}
pci_state = readl(®s-> (,&md
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 "latency: %iclksn"
(pci_state & PCI_32BIT) ? 32 : 64,
(pci_state & PCI_66MHZ ? 66: 3,
ap->pci_latency);
/* * Set the max DMA transfer size. Seems that for most systems * the performance is better when no MAX parameter is * set. However for systems enabling PCI write and invalidate, * DMA writes must be set to the L1 cache line size to get * optimal performance. * * The default is now to turn the PCI write and invalidate off * - that is what Alteon does for NT.
*/
tmp = READ_CMD_MEM | WRITE_CMD_MEM; if (ap->version >= 2) {
tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ /* * Tuning parameters only supported for 8 cards
*/ if (board_idx == BOARD_IDX_OVERFLOW ||
dis_pci_mem_inval[board_idx]) { if (ap->pci_command java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
pci_write_config_wordpdev,PCI_COMMAND
ap->pci_command);
printk(java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 1 " and invalidate\");
}
}else (ap-pci_command &PCI_COMMAND_INVALIDATE {
printk(KERN_INFO " PCI memory write & invalidate " "enabled by BIOS, enabling counter measures\n");
switch(SMP_CACHE_BYTES i;
:
tmp |= DMA_WRITE_MAX_16; break; case 32:
tmp |= DMA_WRITE_MAX_32; break; case 64:
tmp |= DMA_WRITE_MAX_64; break;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
tmp |= DMA_WRITE_MAX_128; break; default:
printk(KERN_INFO " Cache line size %i not " "supported, PCI write and invalidate " "disabled\n", SMP_CACHE_BYTES);
ap->pci_command &=ace_issue_cmd
pci_write_config_word( >promiscjava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
ap-evt;
}
}
}
#ifdef __sparc__ /* * On this platform, we know what the best dma settings * are. We use 64-byte maximum bursts, because if we * burst larger than the cache line size (or even cross * a 64byte boundary in a single burst) the UltraSparc * PCI controller will disconnect at 64-byte multiples. * * Read-multiple will be properly enabled above, and when * set will give the PCI controller proper hints about * prefetching.
*/
tmp &=~DMA_READ_WRITE_MASK
tmp |= DMA_READ_MAX_64;
tmp #endif #fdef __java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
tmp &= ~DMA_READ_WRITE_MASK;
tmp |= DMA_READ_MAX_128; /* * All the docs say MUST NOT. Well, I did. * Nothing terrible happens, if we load wrong size. * Bit w&i still works better!
*/
tmp |= DMA_WRITE_MAX_128; #endif
writel(tmp, ®s->PciState);
#if 0 /* * The Host PCI bus controller driver has to set FBB. * If all devices on that PCI bus support FBB, then the controller * can enable FBB support in the Host PCI Bus controller (or on * the PCI-PCI bridge if that applies). * -ggg
*/ /* * I have received reports from people having problems when this * bit is enabled.
*/ if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
ap->pci_command |= PCI_COMMAND_FAST_BACK;
pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
} #endif
/* * Initialize the generic info block and the command+event rings * and the control blocks for the transmit and receive rings * as they need to be setup once and for all.
*/ if (!(info = dma_alloc_coherent(&ap->pdev->dev, sizeof(struct ace_info),
&ap->info_dma, GFP_KERNEL))) {
ecode = -EAGAIN; goto init_error;
}
ap->info = info;
/* * Get the memory for the skb rings.
*/ if (!(ap->skb = kzalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
ecode = -EAGAIN; goto init_error;
}
/* * The Tigon I does not like having the TX ring in host memory ;-(
*/ if (!ACE_IS_TIGON_I(ap))
tmp |= RCB_FLG_TX_HOST_RING; #if TX_COAL_INTS_ONLY
tmp |= RCB_FLG_COAL_INT_ONLY; #endif
info->tx_ctrl.flags = tmp;
writel(0, ®s->MaskInt);
writel(1, ®s->IfIdx); #if 0 /* * McKinley boxes do not like us fiddling with AssistState * this early
*/
writel(1, ®s->AssistState); #endif
if (board_idx == BOARD_IDX_OVERFLOW) {
printk(KERN_WARNING "%s: more than %i NICs detected, " "ignoring module parameters!\n",
ap->name, ACE_MAX_MOD_PARMS);
} elseif (board_idx >= 0) { if (tx_coal_tick[board_idx])
writel(tx_coal_tick[board_idx],
®s->TuneTxCoalTicks); if (max_tx_desc[board_idx])
writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc);
if (rx_coal_tick[board_idx])
writel(rx_coal_tick[board_idx],
®s->TuneRxCoalTicks); if (max_rx_desc[board_idx])
writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc);
if (trace[board_idx])
writel(trace[board_idx], ®s->TuneTrace);
/* * Set tx_csm before we start receiving interrupts, otherwise * the interrupt handler might think it is supposed to process * tx ints before we are up and running, which may cause a null * pointer access in the int handler.
*/
ap->cur_rx = 0;
ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
/* * Enable DMA engine now. * If we do this sooner, Mckinley box pukes. * I assume it's because Tigon II DMA engine wants to check * *something* even before the CPU is started.
*/
writel(1, ®s->AssistState); /* enable DMA */
/* * Start the NIC CPU
*/
writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl);
readl(®s->CpuCtrl);
/* * Wait for the firmware to spin up - max 3 seconds.
*/
myjif = jiffies + 3 * HZ; while (time_before(jiffies, myjif) && !ap->fw_running)
cpu_relax();
if (!ap->fw_running) {
printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
/* aman@sgi.com - account for badly behaving firmware/NIC: * - have observed that the NIC may continue to generate * interrupts for some reason; attempt to stop it - halt * second CPU for Tigon II cards, and also clear Mb0 * - if we're a module, we'll fail to load if this was * the only GbE card in the system => if the kernel does * see an interrupt from the NIC, code to handle it is * gone and OOps! - so free_irq also
*/ if (ap->version >= 2)
writel(readl(®s->CpuBCtrl) | CPU_HALT,
®s->CpuBCtrl);
writel(0, ®s->Mb0Lo);
readl(®s->Mb0Lo);
ecode = -EBUSY; goto init_error;
}
/* * We load the ring here as there seem to be no way to tell the * firmware to wipe the ring without re-initializing it.
*/ if (!test_and_set_bit(0, &ap->std_refill_busy))
ace_load_std_rx_ring(dev, RX_RING_SIZE); else
printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
ap->name); if (ap->version >= 2) { if (!test_and_set_bit(0, &ap->mini_refill_busy))
ace_load_mini_rx_ring(dev, RX_MINI_SIZE); else
printk(KERN_ERR "%s: Someone is busy refilling " "the RX mini ring\n", ap->name);
} return 0;
if (board_idx >= 0) { if (!jumbo) { if (!tx_coal_tick[board_idx])
writel(DEF_TX_COAL, ®s->TuneTxCoalTicks); if (!max_tx_desc[board_idx])
writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc); if (!rx_coal_tick[board_idx])
writel(DEF_RX_COAL, ®s->TuneRxCoalTicks); if (!max_rx_desc[board_idx])
writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc); if (!tx_ratio[board_idx])
writel(DEF_TX_RATIO, ®s->TxBufRat);
} else { if (!tx_coal_tick[board_idx])
writel(DEF_JUMBO_TX_COAL,
®s->TuneTxCoalTicks); if (!max_tx_desc[board_idx])
writel(DEF_JUMBO_TX_MAX_DESC,
®s->TuneMaxTxDesc); if (!rx_coal_tick[board_idx])
writel(DEF_JUMBO_RX_COAL,
®s->TuneRxCoalTicks); if (!max_rx_desc[board_idx])
writel(DEF_JUMBO_RX_MAX_DESC,
®s->TuneMaxRxDesc); if (!tx_ratio[board_idx])
writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat);
}
}
}
/* * We haven't received a stats update event for more than 2.5 * seconds and there is data in the transmit queue, thus we * assume the card is stuck.
*/ if (*ap->tx_csm != ap->tx_ret_csm) {
printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
dev->name, (unsignedint)readl(®s->HostCtrl)); /* This can happen due to ieee flow control. */
} else {
printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
dev->name); #if 0
netif_wake_queue(dev); #endif
}
}
/* * Copy the contents of the NIC's trace buffer to kernel memory.
*/ staticvoid ace_dump_trace(struct ace_private *ap)
{ #if 0 if (!ap->trace_buf) if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL))) return; #endif
}
/* * Load the standard rx ring. * * Loading rings is safe without holding the spin lock since this is * done only before the device is enabled, thus no interrupts are * generated and by the interrupt handler/bh handler.
*/ staticvoid ace_load_std_rx_ring(struct net_device *dev, int nr_bufs)
{ struct ace_private *ap = netdev_priv(dev); struct ace_regs __iomem *regs = ap->regs; short i, idx;
prefetchw(&ap->cur_rx_bufs);
idx = ap->rx_std_skbprd;
for (i = 0; i < nr_bufs; i++) { struct sk_buff *skb; struct rx_desc *rd;
dma_addr_t mapping;
skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE); if (!skb) break;
out:
clear_bit(0, &ap->mini_refill_busy); return;
error_out:
printk(KERN_INFO "Out of memory when allocating " "mini receive buffers\n"); goto out;
}
/* * Load the jumbo rx ring, this may happen at any time if the MTU * is changed to a value > 1500.
*/ staticvoid ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs)
{ struct ace_private *ap = netdev_priv(dev); struct ace_regs __iomem *regs = ap->regs; short i, idx;
idx = ap->rx_jumbo_skbprd;
for (i = 0; i < nr_bufs; i++) { struct sk_buff *skb; struct rx_desc *rd;
dma_addr_t mapping;
skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE); if (!skb) break;
out:
clear_bit(0, &ap->jumbo_refill_busy); return;
error_out: if (net_ratelimit())
printk(KERN_INFO "Out of memory when allocating " "jumbo receive buffers\n"); goto out;
}
/* * All events are considered to be slow (RX/TX ints do not generate * events) and are handled here, outside the main interrupt handler, * to reduce the size of the handler.
*/ static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
{ struct ace_private *ap;
ap = netdev_priv(dev);
while (evtcsm != evtprd) { switch (ap->evt_ring[evtcsm].evt) { case E_FW_RUNNING:
printk(KERN_INFO "%s: Firmware up and running\n",
ap->name);
ap->fw_running = 1;
wmb(); break; case E_STATS_UPDATED: break; case E_LNK_STATE:
{
u16 code = ap->evt_ring[evtcsm].code; switch (code) { case E_C_LINK_UP:
{
u32 state = readl(&ap->regs->GigLnkState);
printk(KERN_WARNING "%s: Optical link UP " "(%s Duplex, Flow Control: %s%s)\n",
ap->name,
state & LNK_FULL_DUPLEX ? "Full":"Half",
state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
state & LNK_RX_FLOW_CTL_Y ? "RX" : ""); break;
} case E_C_LINK_DOWN:
printk(KERN_WARNING "%s: Optical link DOWN\n",
ap->name); break; case E_C_LINK_10_100:
printk(KERN_WARNING "%s: 10/100BaseT link " "UP\n", ap->name); break; default:
printk(KERN_ERR "%s: Unknown optical link " "state %02x\n", ap->name, code);
} break;
} case E_ERROR: switch(ap->evt_ring[evtcsm].code) { case E_C_ERR_INVAL_CMD:
printk(KERN_ERR "%s: invalid command error\n",
ap->name); break; case E_C_ERR_UNIMP_CMD:
printk(KERN_ERR "%s: unimplemented command " "error\n", ap->name); break; case E_C_ERR_BAD_CFG:
printk(KERN_ERR "%s: bad config error\n",
ap->name); break; default:
printk(KERN_ERR "%s: unknown error %02x\n",
ap->name, ap->evt_ring[evtcsm].code);
} break; case E_RESET_JUMBO_RNG:
{ int i; for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) { if (ap->skb->rx_jumbo_skbuff[i].skb) {
ap->rx_jumbo_ring[i].size = 0;
set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
ap->skb->rx_jumbo_skbuff[i].skb = NULL;
}
}
switch(desc_type) { /* * Normal frames do not have any flags set * * Mini and normal frames arrive frequently, * so use a local counter to avoid doing * atomic operations for each packet arriving.
*/ case 0:
rip = &ap->skb->rx_std_skbuff[skbidx];
mapsize = ACE_STD_BUFSIZE;
std_count++; break; case BD_FLG_JUMBO:
rip = &ap->skb->rx_jumbo_skbuff[skbidx];
mapsize = ACE_JUMBO_BUFSIZE;
atomic_dec(&ap->cur_jumbo_bufs); break; case BD_FLG_MINI:
rip = &ap->skb->rx_mini_skbuff[skbidx];
mapsize = ACE_MINI_BUFSIZE;
mini_count++; break; default:
printk(KERN_INFO "%s: unknown frame type (0x%02x) " "returned by NIC\n", dev->name,
retdesc->flags); goto error;
}
/* * Instead of forcing the poor tigon mips cpu to calculate * pseudo hdr checksum, we do this ourselves.
*/ if (bd_flags & BD_FLG_TCP_UDP_SUM) {
skb->csum = htons(csum);
skb->ip_summed = CHECKSUM_COMPLETE;
} else {
skb_checksum_none_assert(skb);
}
/* send it up */ if ((bd_flags & BD_FLG_VLAN_TAG))
__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), retdesc->vlan);
netif_rx(skb);
atomic_sub(std_count, &ap->cur_rx_bufs); if (!ACE_IS_TIGON_I(ap))
atomic_sub(mini_count, &ap->cur_mini_bufs);
out: /* * According to the documentation RxRetCsm is obsolete with * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
*/ if (ACE_IS_TIGON_I(ap)) {
writel(idx, &ap->regs->RxRetCsm);
}
ap->cur_rx = idx;
if (netif_queue_stopped(dev))
netif_wake_queue(dev);
wmb();
ap->tx_ret_csm = txcsm;
/* So... tx_ret_csm is advanced _after_ check for device wakeup. * * We could try to make it before. In this case we would get * the following race condition: hard_start_xmit on other cpu * enters after we advanced tx_ret_csm and fills space, * which we have just freed, so that we make illegal device wakeup. * There is no good way to workaround this (at entry * to ace_start_xmit detects this condition and prevents * ring corruption, but it is not a good workaround.) * * When tx_ret_csm is advanced after, we wake up device _only_ * if we really have some space in ring (though the core doing * hard_start_xmit can see full ring for some period and has to * synchronize.) Superb. * BUT! We get another subtle race condition. hard_start_xmit * may think that ring is full between wakeup and advancing * tx_ret_csm and will stop device instantly! It is not so bad. * We are guaranteed that there is something in ring, so that * the next irq will resume transmission. To speedup this we could * mark descriptor, which closes ring with BD_FLG_COAL_NOW * (see ace_start_xmit). * * Well, this dilemma exists in all lock-free devices. * We, following scheme used in drivers by Donald Becker, * select the least dangerous. * --ANK
*/
}
/* * In case of PCI shared interrupts or spurious interrupts, * we want to make sure it is actually our interrupt before * spending any time in here.
*/ if (!(readl(®s->HostCtrl) & IN_INT)) return IRQ_NONE;
/* * ACK intr now. Otherwise we will lose updates to rx_ret_prd, * which happened _after_ rxretprd = *ap->rx_ret_prd; but before * writel(0, ®s->Mb0Lo). * * "IRQ avoidance" recommended in docs applies to IRQs served * threads and it is wrong even for that case.
*/
writel(0, ®s->Mb0Lo);
readl(®s->Mb0Lo);
/* * There is no conflict between transmit handling in * start_xmit and receive processing, thus there is no reason * to take a spin lock for RX handling. Wait until we start * working on the other stuff - hey we don't need a spin lock * anymore.
*/
rxretprd = *ap->rx_ret_prd;
rxretcsm = ap->cur_rx;
if (rxretprd != rxretcsm)
ace_rx_int(dev, rxretprd, rxretcsm);
txcsm = *ap->tx_csm;
idx = ap->tx_ret_csm;
if (txcsm != idx) { /* * If each skb takes only one descriptor this check degenerates * to identity, because new space has just been opened. * But if skbs are fragmented we must check that this index * update releases enough of space, otherwise we just * wait for device to make more work.
*/ if (!tx_ring_full(ap, txcsm, ap->tx_prd))
ace_tx_int(dev, txcsm, idx);
}
/* * This has to go last in the interrupt handler and run with * the spin lock released ... what lock?
*/ if (netif_running(dev)) { int cur_size; int run_bh_work = 0;
/* * Without (or before) releasing irq and stopping hardware, this * is an absolute non-sense, by the way. It will be reset instantly * by the first irq.
*/
netif_stop_queue(dev);
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