/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2025 Collabora Ltd * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #ifndef __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H#define __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H#include <linux/soc/mediatek/infracfg.h>#include <dt-bindings/power/mediatek,mt6893-power.h>#include "mtk-pm-domains.h" #define MT6893_TOP_AXI_PROT_EN_MCU_STA1 0x2e4#define MT6893_TOP_AXI_PROT_EN_MCU_SET 0x2c4#define MT6893_TOP_AXI_PROT_EN_MCU_CLR 0x2c8#define MT6893_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4#define MT6893_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8#define MT6893_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbb8#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbbc#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbc4#define MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1 GENMASK(21, 19)#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2 GENMASK(6, 5)#define MT6893_TOP_AXI_PROT_EN_MFG1_STEP3 GENMASK(22, 21)#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7)#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5 GENMASK(19, 17)#define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24)#define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25)#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6)#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7)#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26)#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0)#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3 BIT(27)#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4 BIT(1)#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1 GENMASK(30, 28)#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2 GENMASK(31, 29)#define MT6893_TOP_AXI_PROT_EN_MDP_STEP1 BIT(10)#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2 (BIT(2) | BIT(4) | BIT(6) | \#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3 (BIT(0) | BIT(2) | BIT(4) | \#define MT6893_TOP_AXI_PROT_EN_MDP_STEP4 BIT(23)#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5 (BIT(3) | BIT(5) | BIT(7) | \#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6 (BIT(1) | BIT(7) | BIT(9) | BIT(11))#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7 BIT(20)#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1 (BIT(0) | BIT(6) | BIT(8) | \#define MT6893_TOP_AXI_PROT_EN_DISP_STEP2 BIT(6)#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3 (BIT(1) | BIT(7) | BIT(9) | \#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4 BIT(21)#define MT6893_TOP_AXI_PROT_EN_2_ADSP BIT(3)#define MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1 BIT(1)#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2 (BIT(0) | BIT(2) | BIT(4))#define MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3 BIT(22)#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4 (BIT(1) | BIT(3) | BIT(5))#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1 BIT(18)#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2 BIT(19)#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1 BIT(20)#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2 BIT(21)#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1 BIT(22)#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2 BIT(23)/* * MT6893 Power Domain (MTCMOS) support * * The register layout for this IP is very similar to MT8192 so where possible * the same definitions are reused to avoid duplication. * Where the bus protection bits are also the same, the entire set is reused. static const struct scpsys_domain_data scpsys_domain_data_mt6893[] = {"conn" ,"mfg0" ,"mfg1" ,"mfg2" ,"mfg3" ,"mfg4" ,"mfg5" ,"mfg6" ,"isp" ,"isp2" ,"ipe" ,"vdec0" ,"vdec1" ,"venc0" ,"venc1" ,"mdp" ,"disp" ,"audio" ,"audio" ,"cam" ,"cam_rawa" ,"cam_rawb" ,"cam_rawc" ,"dp_tx" ,static const struct scpsys_soc_data mt6893_scpsys_data = {#endif /* __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H */
Messung V0.5 C=98 H=94 G=95
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