/* Max number of USB devices for any host controller - limit in section 6.1 */ #define MAX_HC_SLOTS 256 /* Section 5.3.3 - MaxPorts */ #define MAX_HC_PORTS 127
/* * xHCI register interface. * This corresponds to the eXtensible Host Controller Interface (xHCI) * Revision 0.95 specification
*/
/** * struct xhci_op_regs - xHCI Host Controller Operational Registers. * @command: USBCMD - xHC command register * @status: USBSTS - xHC status register * @page_size: This indicates the page size that the host controller * supports. If bit n is set, the HC supports a page size * of 2^(n+12), up to a 128MB page size. * 4K is the minimum page size. * @cmd_ring: CRP - 64-bit Command Ring Pointer * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer * @config_reg: CONFIG - Configure Register * @port_status_base: PORTSCn - base address for Port Status and Control * Each port has a Port Status and Control register, * followed by a Port Power Management Status and Control * register, a Port Link Info register, and a reserved * register. * @port_power_base: PORTPMSCn - base address for * Port Power Management Status and Control * @port_link_base: PORTLIn - base address for Port Link Info (current * Link PM state and control) for USB 2.1 and USB 3.0 * devices.
*/ struct xhci_op_regs {
__le32 command;
__le32 status;
__le32 page_size;
__le32 reserved1;
__le32 reserved2;
__le32 dev_notification;
__le64 cmd_ring; /* rsvd: offset 0x20-2F */
__le32 reserved3[4];
__le64 dcbaa_ptr;
__le32 config_reg; /* rsvd: offset 0x3C-3FF */
__le32 reserved4[241]; /* port 1 registers, which serve as a base address for other ports */
__le32 port_status_base;
__le32 port_power_base;
__le32 port_link_base;
__le32 reserved5; /* registers for ports 2-255 */
__le32 reserved6[NUM_PORT_REGS*254];
};
/* USBCMD - USB command - command bitmasks */ /* start/stop HC execution - do not write unless HC is halted*/ #define CMD_RUN XHCI_CMD_RUN /* Reset HC - resets internal HC state machine and all registers (except * PCI config regs). HC does NOT drive a USB reset on the downstream ports. * The xHCI driver must reinitialize the xHC after setting this bit.
*/ #define CMD_RESET (1 << 1) /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ #define CMD_EIE XHCI_CMD_EIE /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ #define CMD_HSEIE XHCI_CMD_HSEIE /* bits 4:6 are reserved (and should be preserved on writes). */ /* light reset (port status stays unchanged) - reset completed when this is 0 */ #define CMD_LRESET (1 << 7) /* host controller save/restore state. */ #define CMD_CSS (1 << 8) #define CMD_CRS (1 << 9) /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ #define CMD_EWE XHCI_CMD_EWE /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. * '0' means the xHC can power it off if all ports are in the disconnect, * disabled, or powered-off state.
*/ #define CMD_PM_INDEX (1 << 11) /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ #define CMD_ETE (1 << 14) /* bits 15:31 are reserved (and should be preserved on writes). */
/* USBSTS - USB status - status bitmasks */ /* HC not running - set to 1 when run/stop bit is cleared. */ #define STS_HALT XHCI_STS_HALT /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ #define STS_FATAL (1 << 2) /* event interrupt - clear this prior to clearing any IP flags in IR set*/ #define STS_EINT (1 << 3) /* port change detect */ #define STS_PORT (1 << 4) /* bits 5:7 reserved and zeroed */ /* save state status - '1' means xHC is saving state */ #define STS_SAVE (1 << 8) /* restore state status - '1' means xHC is restoring state */ #define STS_RESTORE (1 << 9) /* true: save or restore error */ #define STS_SRE (1 << 10) /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ #define STS_CNR XHCI_STS_CNR /* true: internal Host Controller Error - SW needs to reset and reinitialize */ #define STS_HCE (1 << 12) /* bits 13:31 reserved and should be preserved */
/* * DNCTRL - Device Notification Control Register - dev_notification bitmasks * Generate a device notification event when the HC sees a transaction with a * notification type that matches a bit set in this bit field.
*/ #define DEV_NOTE_MASK (0xffff) /* Most of the device notification types should only be used for debug. * SW does need to pay attention to function wake notifications.
*/ #define DEV_NOTE_FWAKE (1 << 1)
/* CRCR - Command Ring Control Register - cmd_ring bitmasks */ /* bit 0 - Cycle bit indicates the ownership of the command ring */ #define CMD_RING_CYCLE (1 << 0) /* stop ring operation after completion of the currently executing command */ #define CMD_RING_PAUSE (1 << 1) /* stop ring immediately - abort the currently executing command */ #define CMD_RING_ABORT (1 << 2) /* true: command ring is running */ #define CMD_RING_RUNNING (1 << 3) /* bits 63:6 - Command Ring pointer */ #define CMD_RING_PTR_MASK GENMASK_ULL(63, 6)
/* CONFIG - Configure Register - config_reg bitmasks */ /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ #define MAX_DEVS(p) ((p) & 0xff) /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ #define CONFIG_U3E (1 << 8) /* bit 9: Configuration Information Enable, xhci 1.1 */ #define CONFIG_CIE (1 << 9) /* bits 10:31 - reserved and should be preserved */
/** * struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2. * @iman: IMAN - Interrupt Management Register. Used to enable * interrupts and check for pending interrupts. * @imod: IMOD - Interrupt Moderation Register. Used to throttle interrupts. * @erst_size: ERSTSZ - Number of segments in the Event Ring Segment Table (ERST). * @erst_base: ERSTBA - Event ring segment table base address. * @erst_dequeue: ERDP - Event ring dequeue pointer. * * Each interrupter (defined by a MSI-X vector) has an event ring and an Event * Ring Segment Table (ERST) associated with it. The event ring is comprised of * multiple segments of the same size. The HC places events on the ring and * "updates the Cycle bit in the TRBs to indicate to software the current * position of the Enqueue Pointer." The HCD (Linux) processes those events and * updates the dequeue pointer.
*/ struct xhci_intr_reg {
__le32 iman;
__le32 imod;
__le32 erst_size;
__le32 rsvd;
__le64 erst_base;
__le64 erst_dequeue;
};
/* iman bitmasks */ /* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */ #define IMAN_IP (1 << 0) /* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */ #define IMAN_IE (1 << 1)
/* imod bitmasks */ /* * bits 15:0 - Interrupt Moderation Interval, the minimum interval between interrupts * (in 250ns intervals). The interval between interrupts will be longer if there are no * events on the event ring. Default is 4000 (1 ms).
*/ #define IMODI_MASK (0xffff) /* bits 31:16 - Interrupt Moderation Counter, used to count down the time to the next interrupt */ #define IMODC_MASK (0xffff << 16)
/* erst_size bitmasks */ /* bits 15:0 - Event Ring Segment Table Size, number of ERST entries */ #define ERST_SIZE_MASK (0xffff)
/* erst_base bitmasks */ /* bits 63:6 - Event Ring Segment Table Base Address Register */ #define ERST_BASE_ADDRESS_MASK GENMASK_ULL(63, 6)
/* erst_dequeue bitmasks */ /* * bits 2:0 - Dequeue ERST Segment Index (DESI), is the segment number (or alias) where the * current dequeue pointer lies. This is an optional HW hint.
*/ #define ERST_DESI_MASK (0x7) /* * bit 3 - Event Handler Busy (EHB), whether the event ring is scheduled to be serviced by * a work queue (or delayed service routine)?
*/ #define ERST_EHB (1 << 3) /* bits 63:4 - Event Ring Dequeue Pointer */ #define ERST_PTR_MASK GENMASK_ULL(63, 4)
/** * struct xhci_run_regs * @microframe_index: * MFINDEX - current microframe number * * Section 5.5 Host Controller Runtime Registers: * "Software should read and write these registers using only Dword (32 bit) * or larger accesses"
*/ struct xhci_run_regs {
__le32 microframe_index;
__le32 rsvd[7]; struct xhci_intr_reg ir_set[128];
};
/** * struct xhci_container_ctx * @type: Type of context. Used to calculated offsets to contained contexts. * @size: Size of the context data * @bytes: The raw context data given to HW * @dma: dma address of the bytes * * Represents either a Device or Input context. Holds a pointer to the raw * memory used for the context (bytes) and dma address of it (dma).
*/ struct xhci_container_ctx { unsigned type; #define XHCI_CTX_TYPE_DEVICE 0x1 #define XHCI_CTX_TYPE_INPUT 0x2
int size;
u8 *bytes;
dma_addr_t dma;
};
/** * struct xhci_slot_ctx * @dev_info: Route string, device speed, hub info, and last valid endpoint * @dev_info2: Max exit latency for device number, root hub port number * @tt_info: tt_info is used to construct split transaction tokens * @dev_state: slot state and device address * * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes * reserved at the end of the slot context for HC internal use.
*/ struct xhci_slot_ctx {
__le32 dev_info;
__le32 dev_info2;
__le32 tt_info;
__le32 dev_state; /* offset 0x10 to 0x1f reserved for HC internal use */
__le32 reserved[4];
};
/* dev_info bitmasks */ /* Route String - 0:19 */ #define ROUTE_STRING_MASK (0xfffff) /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ #define DEV_SPEED (0xf << 20) #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) /* bit 24 reserved */ /* Is this LS/FS device connected through a HS hub? - bit 25 */ #define DEV_MTT (0x1 << 25) /* Set if the device is a hub - bit 26 */ #define DEV_HUB (0x1 << 26) /* Index of the last valid endpoint context in this device context - 27:31 */ #define LAST_CTX_MASK (0x1f << 27) #define LAST_CTX(p) ((p) << 27) #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) #define SLOT_FLAG (1 << 0) #define EP0_FLAG (1 << 1)
/* dev_info2 bitmasks */ /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ #define MAX_EXIT (0xffff) /* Root hub port number that is needed to access the USB device */ #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) /* Maximum number of ports under a hub device */ #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
/* tt_info bitmasks */ /* * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub * The Slot ID of the hub that isolates the high speed signaling from * this low or full-speed device. '0' if attached to root hub port.
*/ #define TT_SLOT (0xff) /* * The number of the downstream facing port of the high-speed hub * '0' if the device is not low or full speed.
*/ #define TT_PORT (0xff << 8) #define TT_THINK_TIME(p) (((p) & 0x3) << 16) #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
/* dev_state bitmasks */ /* USB device address - assigned by the HC */ #define DEV_ADDR_MASK (0xff) /* bits 8:26 reserved */ /* Slot state */ #define SLOT_STATE (0x1f << 27) #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
/** * struct xhci_ep_ctx * @ep_info: endpoint state, streams, mult, and interval information. * @ep_info2: information on endpoint type, max packet size, max burst size, * error count, and whether the HC will force an event for all * transactions. * @deq: 64-bit ring dequeue pointer address. If the endpoint only * defines one stream, this points to the endpoint transfer ring. * Otherwise, it points to a stream context array, which has a * ring pointer for each flow. * @tx_info: * Average TRB lengths for the endpoint ring and * max payload within an Endpoint Service Interval Time (ESIT). * * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes * reserved at the end of the endpoint context for HC internal use.
*/ struct xhci_ep_ctx {
__le32 ep_info;
__le32 ep_info2;
__le64 deq;
__le32 tx_info; /* offset 0x14 - 0x1f reserved for HC internal use */
__le32 reserved[3];
};
/* ep_info bitmasks */ /* * Endpoint State - bits 0:2 * 0 - disabled * 1 - running * 2 - halted due to halt condition - ok to manipulate endpoint ring * 3 - stopped * 4 - TRB error * 5-7 - reserved
*/ #define EP_STATE_MASK (0x7) #define EP_STATE_DISABLED 0 #define EP_STATE_RUNNING 1 #define EP_STATE_HALTED 2 #define EP_STATE_STOPPED 3 #define EP_STATE_ERROR 4 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
/* Mult - Max number of burtst within an interval, in EP companion desc. */ #define EP_MULT(p) (((p) & 0x3) << 8) #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) /* bits 10:14 are Max Primary Streams */ /* bit 15 is Linear Stream Array */ /* Interval - period between requests to an endpoint - 125u increments. */ #define EP_INTERVAL(p) (((p) & 0xff) << 16) #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) #define EP_MAXPSTREAMS_MASK (0x1f << 10) #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ #define EP_HAS_LSA (1 << 15) /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
/* ep_info2 bitmasks */ /* * Force Event - generate transfer events for all TRBs for this endpoint * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
*/ #define FORCE_EVENT (0x1) #define ERROR_COUNT(p) (((p) & 0x3) << 1) #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) #define EP_TYPE(p) ((p) << 3) #define ISOC_OUT_EP 1 #define BULK_OUT_EP 2 #define INT_OUT_EP 3 #define CTRL_EP 4 #define ISOC_IN_EP 5 #define BULK_IN_EP 6 #define INT_IN_EP 7 /* bit 6 reserved */ /* bit 7 is Host Initiate Disable - for disabling stream selection */ #define MAX_BURST(p) (((p)&0xff) << 8) #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) #define MAX_PACKET(p) (((p)&0xffff) << 16) #define MAX_PACKET_MASK (0xffff << 16) #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
/** * struct xhci_input_control_context * Input control context; see section 6.2.5. * * @drop_context: set the bit of the endpoint context you want to disable * @add_context: set the bit of the endpoint context you want to enable
*/ struct xhci_input_control_ctx {
__le32 drop_flags;
__le32 add_flags;
__le32 rsvd2[6];
};
/* Represents everything that is needed to issue a command on the command ring. * It's useful to pre-allocate these for commands that cannot fail due to * out-of-memory errors, like freeing streams.
*/ struct xhci_command { /* Input context for changing device state */ struct xhci_container_ctx *in_ctx;
u32 status;
u32 comp_param; int slot_id; /* If completion is null, no one is waiting on this command * and the structure can be freed after the command completes.
*/ struct completion *completion; union xhci_trb *command_trb; struct list_head cmd_list; /* xHCI command response timeout in milliseconds */ unsignedint timeout_ms;
};
struct xhci_stream_ctx { /* 64-bit stream ring address, cycle state, and stream type */
__le64 stream_ring; /* offset 0x14 - 0x1f reserved for HC internal use */
__le32 reserved[2];
};
/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) #define CTX_TO_SCT(p) (((p) >> 1) & 0x7) /* Secondary stream array type, dequeue pointer is to a transfer ring */ #define SCT_SEC_TR 0 /* Primary stream array type, dequeue pointer is to a transfer ring */ #define SCT_PRI_TR 1 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ #define SCT_SSA_8 2 #define SCT_SSA_16 3 #define SCT_SSA_32 4 #define SCT_SSA_64 5 #define SCT_SSA_128 6 #define SCT_SSA_256 7
/* Assume no secondary streams for now */ struct xhci_stream_info { struct xhci_ring **stream_rings; /* Number of streams, including stream 0 (which drivers can't use) */ unsignedint num_streams; /* The stream context array may be bigger than * the number of streams the driver asked for
*/ struct xhci_stream_ctx *stream_ctx_array; unsignedint num_stream_ctxs;
dma_addr_t ctx_array_dma; /* For mapping physical TRB addresses to segments in stream rings */ struct radix_tree_root trb_address_map; struct xhci_command *free_streams_command;
};
/* Some Intel xHCI host controllers need software to keep track of the bus * bandwidth. Keep track of endpoint info here. Each root port is allocated * the full bus bandwidth. We must also treat TTs (including each port under a * multi-TT hub) as a separate bandwidth domain. The direct memory interface * (DMI) also limits the total bandwidth (across all domains) that can be used.
*/ struct xhci_bw_info { /* ep_interval is zero-based */ unsignedint ep_interval; /* mult and num_packets are one-based */ unsignedint mult; unsignedint num_packets; unsignedint max_packet_size; unsignedint max_esit_payload; unsignedint type;
};
/* "Block" sizes in bytes the hardware uses for different device speeds. * The logic in this part of the hardware limits the number of bits the hardware * can use, so must represent bandwidth in a less precise manner to mimic what * the scheduler hardware computes.
*/ #define FS_BLOCK 1 #define HS_BLOCK 4 #define SS_BLOCK 16 #define DMI_BLOCK 32
/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated * with each byte transferred. SuperSpeed devices have an initial overhead to * set up bursts. These are in blocks, see above. LS overhead has already been * translated into FS blocks.
*/ #define DMI_OVERHEAD 8 #define DMI_OVERHEAD_BURST 4 #define SS_OVERHEAD 8 #define SS_OVERHEAD_BURST 32 #define HS_OVERHEAD 26 #define FS_OVERHEAD 20 #define LS_OVERHEAD 128 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per * microframe ~= 24Mbps) of the HS bus as the devices can actually use because * of overhead associated with split transfers crossing microframe boundaries. * 31 blocks is pure protocol overhead.
*/ #define TT_HS_OVERHEAD (31 + 94) #define TT_DMI_OVERHEAD (25 + 12)
/* Percentage of bus bandwidth reserved for non-periodic transfers */ #define FS_BW_RESERVED 10 #define HS_BW_RESERVED 20 #define SS_BW_RESERVED 10
struct xhci_virt_ep { struct xhci_virt_device *vdev; /* parent */ unsignedint ep_index; struct xhci_ring *ring; /* Related to endpoints that are configured to use stream IDs only */ struct xhci_stream_info *stream_info; /* Temporary storage in case the configure endpoint command fails and we * have to restore the device state to the previous state
*/ struct xhci_ring *new_ring; unsignedint err_count; unsignedint ep_state; #define SET_DEQ_PENDING (1 << 0) #define EP_HALTED (1 << 1) /* For stall handling */ #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ /* Transitioning the endpoint to using streams, don't enqueue URBs */ #define EP_GETTING_STREAMS (1 << 3) #define EP_HAS_STREAMS (1 << 4) /* Transitioning the endpoint to not using streams, don't enqueue URBs */ #define EP_GETTING_NO_STREAMS (1 << 5) #define EP_HARD_CLEAR_TOGGLE (1 << 6) #define EP_SOFT_CLEAR_TOGGLE (1 << 7) /* usb_hub_clear_tt_buffer is in progress */ #define EP_CLEARING_TT (1 << 8) /* ---- Related to URB cancellation ---- */ struct list_head cancelled_td_list; struct xhci_hcd *xhci; /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue * command. We'll need to update the ring's dequeue segment and dequeue * pointer after the command completes.
*/ struct xhci_segment *queued_deq_seg; union xhci_trb *queued_deq_ptr; /* * Sometimes the xHC can not process isochronous endpoint ring quickly * enough, and it will miss some isoc tds on the ring and generate * a Missed Service Error Event. * Set skip flag when receive a Missed Service Error Event and * process the missed tds on the endpoint ring.
*/ bool skip; /* Bandwidth checking storage */ struct xhci_bw_info bw_info; struct list_head bw_endpoint_list; unsignedlong stop_time; /* Isoch Frame ID checking storage */ int next_frame_id; /* Use new Isoch TRB layout needed for extended TBC support */ bool use_extended_tbc; /* set if this endpoint is controlled via sideband access*/ struct xhci_sideband *sideband;
};
struct xhci_interval_bw { unsignedint num_packets; /* Sorted by max packet size. * Head of the list is the greatest max packet size.
*/ struct list_head endpoints; /* How many endpoints of each speed are present. */ unsignedint overhead[3];
};
struct xhci_virt_device { int slot_id; struct usb_device *udev; /* * Commands to the hardware are passed an "input context" that * tells the hardware what to change in its data structures. * The hardware will return changes in an "output context" that * software must allocate for the hardware. We need to keep * track of input and output contexts separately because * these commands might fail and we don't trust the hardware.
*/ struct xhci_container_ctx *out_ctx; /* Used for addressing devices and configuration changes */ struct xhci_container_ctx *in_ctx; struct xhci_virt_ep eps[EP_CTX_PER_DEV]; struct xhci_port *rhub_port; struct xhci_interval_bw_table *bw_table; struct xhci_tt_bw_info *tt_info; /* * flags for state tracking based on events and issued commands. * Software can not rely on states from output contexts because of * latency between events and xHC updating output context values. * See xhci 1.1 section 4.8.3 for more details
*/ unsignedlong flags; #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
/* The current max exit latency for the enabled USB3 link states. */
u16 current_mel; /* Used for the debugfs interfaces. */ void *debugfs_private; /* set if this endpoint is controlled via sideband access*/ struct xhci_sideband *sideband;
};
/* * For each roothub, keep track of the bandwidth information for each periodic * interval. * * If a high speed hub is attached to the roothub, each TT associated with that * hub is a separate bandwidth domain. The interval information for the * endpoints on the devices under that TT will appear in the TT structure.
*/ struct xhci_root_port_bw_info { struct list_head tts; unsignedint num_active_tts; struct xhci_interval_bw_table bw_table;
};
struct xhci_tt_bw_info { struct list_head tt_list; int slot_id; int ttport; struct xhci_interval_bw_table bw_table; int active_eps;
};
/** * struct xhci_device_context_array * @dev_context_ptr array of 64-bit DMA addresses for device contexts
*/ struct xhci_device_context_array { /* 64-bit device addresses; we only write 32-bit addresses */
__le64 dev_context_ptrs[MAX_HC_SLOTS]; /* private xHCD pointers */
dma_addr_t dma;
}; /* TODO: write function to set the 64-bit device DMA address */ /* * TODO: change this to be dynamically sized at HC mem init time since the HC * might not be able to handle the maximum number of devices possible.
*/
struct xhci_transfer_event { /* 64-bit buffer address, or immediate data */
__le64 buffer;
__le32 transfer_len; /* This field is interpreted differently based on the type of TRB */
__le32 flags;
};
/* Transfer event flags bitfield, also for select command completion events */ #define TRB_TO_SLOT_ID(p) (((p) >> 24) & 0xff) #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
staticinlineconstchar *xhci_trb_comp_code_string(u8 status)
{ switch (status) { case COMP_INVALID: return"Invalid"; case COMP_SUCCESS: return"Success"; case COMP_DATA_BUFFER_ERROR: return"Data Buffer Error"; case COMP_BABBLE_DETECTED_ERROR: return"Babble Detected"; case COMP_USB_TRANSACTION_ERROR: return"USB Transaction Error"; case COMP_TRB_ERROR: return"TRB Error"; case COMP_STALL_ERROR: return"Stall Error"; case COMP_RESOURCE_ERROR: return"Resource Error"; case COMP_BANDWIDTH_ERROR: return"Bandwidth Error"; case COMP_NO_SLOTS_AVAILABLE_ERROR: return"No Slots Available Error"; case COMP_INVALID_STREAM_TYPE_ERROR: return"Invalid Stream Type Error"; case COMP_SLOT_NOT_ENABLED_ERROR: return"Slot Not Enabled Error"; case COMP_ENDPOINT_NOT_ENABLED_ERROR: return"Endpoint Not Enabled Error"; case COMP_SHORT_PACKET: return"Short Packet"; case COMP_RING_UNDERRUN: return"Ring Underrun"; case COMP_RING_OVERRUN: return"Ring Overrun"; case COMP_VF_EVENT_RING_FULL_ERROR: return"VF Event Ring Full Error"; case COMP_PARAMETER_ERROR: return"Parameter Error"; case COMP_BANDWIDTH_OVERRUN_ERROR: return"Bandwidth Overrun Error"; case COMP_CONTEXT_STATE_ERROR: return"Context State Error"; case COMP_NO_PING_RESPONSE_ERROR: return"No Ping Response Error"; case COMP_EVENT_RING_FULL_ERROR: return"Event Ring Full Error"; case COMP_INCOMPATIBLE_DEVICE_ERROR: return"Incompatible Device Error"; case COMP_MISSED_SERVICE_ERROR: return"Missed Service Error"; case COMP_COMMAND_RING_STOPPED: return"Command Ring Stopped"; case COMP_COMMAND_ABORTED: return"Command Aborted"; case COMP_STOPPED: return"Stopped"; case COMP_STOPPED_LENGTH_INVALID: return"Stopped - Length Invalid"; case COMP_STOPPED_SHORT_PACKET: return"Stopped - Short Packet"; case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: return"Max Exit Latency Too Large Error"; case COMP_ISOCH_BUFFER_OVERRUN: return"Isoch Buffer Overrun"; case COMP_EVENT_LOST_ERROR: return"Event Lost Error"; case COMP_UNDEFINED_ERROR: return"Undefined Error"; case COMP_INVALID_STREAM_ID_ERROR: return"Invalid Stream ID Error"; case COMP_SECONDARY_BANDWIDTH_ERROR: return"Secondary Bandwidth Error"; case COMP_SPLIT_TRANSACTION_ERROR: return"Split Transaction Error"; default: return"Unknown!!";
}
}
/* control bitfields */ #define LINK_TOGGLE (0x1<<1)
/* Command completion event TRB */ struct xhci_event_cmd { /* Pointer to command TRB, or the value passed by the event data trb */
__le64 cmd_trb;
__le32 status;
__le32 flags;
};
/* Link TRB specific fields */ #define TRB_TC (1<<1)
/* Port Status Change Event TRB fields */ /* Port ID - bits 31:24 */ #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
#define EVENT_DATA (1 << 2)
/* Normal TRB fields */ /* transfer_len bitmasks - bits 0:16 */ #define TRB_LEN(p) ((p) & 0x1ffff) /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) /* Interrupter Target - which MSI-X vector to target the completion event at */ #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
/* Cycle bit - indicates TRB ownership by HC or HCD */ #define TRB_CYCLE (1<<0) /* * Force next event data TRB to be evaluated before task switch. * Used to pass OS data back after a TD completes.
*/ #define TRB_ENT (1<<1) /* Interrupt on short packet */ #define TRB_ISP (1<<2) /* Set PCIe no snoop attribute */ #define TRB_NO_SNOOP (1<<3) /* Chain multiple TRBs into a TD */ #define TRB_CHAIN (1<<4) /* Interrupt on completion */ #define TRB_IOC (1<<5) /* The buffer pointer contains immediate data */ #define TRB_IDT (1<<6) /* TDs smaller than this might use IDT */ #define TRB_IDT_MAX_SIZE 8
/* TRB bit mask */ #define TRB_TYPE_BITMASK (0xfc00) #define TRB_TYPE(p) ((p) << 10) #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) /* TRB type IDs */ /* bulk, interrupt, isoc scatter/gather, and control data stage */ #define TRB_NORMAL 1 /* setup stage for control transfers */ #define TRB_SETUP 2 /* data stage for control transfers */ #define TRB_DATA 3 /* status stage for control transfers */ #define TRB_STATUS 4 /* isoc transfers */ #define TRB_ISOC 5 /* TRB for linking ring segments */ #define TRB_LINK 6 #define TRB_EVENT_DATA 7 /* Transfer Ring No-op (not for the command ring) */ #define TRB_TR_NOOP 8 /* Command TRBs */ /* Enable Slot Command */ #define TRB_ENABLE_SLOT 9 /* Disable Slot Command */ #define TRB_DISABLE_SLOT 10 /* Address Device Command */ #define TRB_ADDR_DEV 11 /* Configure Endpoint Command */ #define TRB_CONFIG_EP 12 /* Evaluate Context Command */ #define TRB_EVAL_CONTEXT 13 /* Reset Endpoint Command */ #define TRB_RESET_EP 14 /* Stop Transfer Ring Command */ #define TRB_STOP_RING 15 /* Set Transfer Ring Dequeue Pointer Command */ #define TRB_SET_DEQ 16 /* Reset Device Command */ #define TRB_RESET_DEV 17 /* Force Event Command (opt) */ #define TRB_FORCE_EVENT 18 /* Negotiate Bandwidth Command (opt) */ #define TRB_NEG_BANDWIDTH 19 /* Set Latency Tolerance Value Command (opt) */ #define TRB_SET_LT 20 /* Get port bandwidth Command */ #define TRB_GET_BW 21 /* Force Header Command - generate a transaction or link management packet */ #define TRB_FORCE_HEADER 22 /* No-op Command - not for transfer rings */ #define TRB_CMD_NOOP 23 /* TRB IDs 24-31 reserved */ /* Event TRBS */ /* Transfer Event */ #define TRB_TRANSFER 32 /* Command Completion Event */ #define TRB_COMPLETION 33 /* Port Status Change Event */ #define TRB_PORT_STATUS 34 /* Bandwidth Request Event (opt) */ #define TRB_BANDWIDTH_EVENT 35 /* Doorbell Event (opt) */ #define TRB_DOORBELL 36 /* Host Controller Event */ #define TRB_HC_EVENT 37 /* Device Notification Event - device sent function wake notification */ #define TRB_DEV_NOTE 38 /* MFINDEX Wrap Event - microframe counter wrapped */ #define TRB_MFINDEX_WRAP 39 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ #define TRB_VENDOR_DEFINED_LOW 48 /* Nec vendor-specific command completion event. */ #define TRB_NEC_CMD_COMP 48 /* Get NEC firmware revision. */ #define TRB_NEC_GET_FW 49
staticinlineconstchar *xhci_trb_type_string(u8 type)
{ switch (type) { case TRB_NORMAL: return"Normal"; case TRB_SETUP: return"Setup Stage"; case TRB_DATA: return"Data Stage"; case TRB_STATUS: return"Status Stage"; case TRB_ISOC: return"Isoch"; case TRB_LINK: return"Link"; case TRB_EVENT_DATA: return"Event Data"; case TRB_TR_NOOP: return"No-Op"; case TRB_ENABLE_SLOT: return"Enable Slot Command"; case TRB_DISABLE_SLOT: return"Disable Slot Command"; case TRB_ADDR_DEV: return"Address Device Command"; case TRB_CONFIG_EP: return"Configure Endpoint Command"; case TRB_EVAL_CONTEXT: return"Evaluate Context Command"; case TRB_RESET_EP: return"Reset Endpoint Command"; case TRB_STOP_RING: return"Stop Ring Command"; case TRB_SET_DEQ: return"Set TR Dequeue Pointer Command"; case TRB_RESET_DEV: return"Reset Device Command"; case TRB_FORCE_EVENT: return"Force Event Command"; case TRB_NEG_BANDWIDTH: return"Negotiate Bandwidth Command"; case TRB_SET_LT: return"Set Latency Tolerance Value Command"; case TRB_GET_BW: return"Get Port Bandwidth Command"; case TRB_FORCE_HEADER: return"Force Header Command"; case TRB_CMD_NOOP: return"No-Op Command"; case TRB_TRANSFER: return"Transfer Event"; case TRB_COMPLETION: return"Command Completion Event"; case TRB_PORT_STATUS: return"Port Status Change Event"; case TRB_BANDWIDTH_EVENT: return"Bandwidth Request Event"; case TRB_DOORBELL: return"Doorbell Event"; case TRB_HC_EVENT: return"Host Controller Event"; case TRB_DEV_NOTE: return"Device Notification Event"; case TRB_MFINDEX_WRAP: return"MFINDEX Wrap Event"; case TRB_NEC_CMD_COMP: return"NEC Command Completion Event"; case TRB_NEC_GET_FW: return"NET Get Firmware Revision Command"; default: return"UNKNOWN";
}
}
#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) /* Above, but for __le32 types -- can avoid work by swapping constants: */ #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
cpu_to_le32(TRB_TYPE(TRB_LINK))) #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
/* * TRBS_PER_SEGMENT must be a multiple of 4, * since the command ring is 64-byte aligned. * It must also be greater than 16.
*/ #define TRBS_PER_SEGMENT 256 /* Allow two commands + a link TRB, along with any reserved command TRBs */ #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) /* TRB buffer pointers can't cross 64KB boundaries */ #define TRB_MAX_BUFF_SHIFT 16 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) /* How much data is left before the 64KB boundary? */ #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
(addr & (TRB_MAX_BUFF_SIZE - 1))) #define MAX_SOFT_RETRY 3 /* * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if * XHCI_AVOID_BEI quirk is in use.
*/ #define AVOID_BEI_INTERVAL_MIN 8 #define AVOID_BEI_INTERVAL_MAX 32
#define xhci_for_each_ring_seg(head, seg) \ for (seg = head; seg != NULL; seg = (seg->next != head ? seg->next : NULL))
struct xhci_segment { union xhci_trb *trbs; /* private to HCD */ struct xhci_segment *next; unsignedint num;
dma_addr_t dma; /* Max packet sized bounce buffer for td-fragmant alignment */
dma_addr_t bounce_dma; void *bounce_buf; unsignedint bounce_offs; unsignedint bounce_len;
};
staticinlineconstchar *xhci_ring_type_string(enum xhci_ring_type type)
{ switch (type) { case TYPE_CTRL: return"CTRL"; case TYPE_ISOC: return"ISOC"; case TYPE_BULK: return"BULK"; case TYPE_INTR: return"INTR"; case TYPE_STREAM: return"STREAM"; case TYPE_COMMAND: return"CMD"; case TYPE_EVENT: return"EVENT";
}
return"UNKNOWN";
}
struct xhci_ring { struct xhci_segment *first_seg; struct xhci_segment *last_seg; union xhci_trb *enqueue; struct xhci_segment *enq_seg; union xhci_trb *dequeue; struct xhci_segment *deq_seg; struct list_head td_list; /* * Write the cycle state into the TRB cycle field to give ownership of * the TRB to the host controller (if we are the producer), or to check * if we own the TRB (if we are the consumer). See section 4.9.1.
*/
u32 cycle_state; unsignedint stream_id; unsignedint num_segs; unsignedint num_trbs_free; /* used only by xhci DbC */ unsignedint bounce_buf_len; enum xhci_ring_type type;
u32 old_trb_comp_code; struct radix_tree_root *trb_address_map;
};
struct xhci_erst_entry { /* 64-bit event ring segment address */
__le64 seg_addr;
__le32 seg_size; /* Set to zero */
__le32 rsvd;
};
struct urb_priv { int num_tds; int num_tds_done; struct xhci_td td[] __counted_by(num_tds);
};
/* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */ #define ERST_DEFAULT_SEGS 2 /* Poll every 60 seconds */ #define POLL_TIMEOUT 60 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ #define XHCI_STOP_EP_CMD_TIMEOUT 5 /* XXX: Make these module parameters */
/* Port suspend arrays are indexed by the portnum of the fake roothub */ /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
u32 port_c_suspend;
u32 suspended_ports;
u32 port_remote_wakeup; /* which ports have started to resume */ unsignedlong resuming_ports;
};
struct xhci_interrupter { struct xhci_ring *event_ring; struct xhci_erst erst; struct xhci_intr_reg __iomem *ir_set; unsignedint intr_num; bool ip_autoclear;
u32 isoc_bei_interval; /* For interrupter registers save and restore over suspend/resume */
u32 s3_iman;
u32 s3_imod;
u32 s3_erst_size;
u64 s3_erst_base;
u64 s3_erst_dequeue;
}; /* * It can take up to 20 ms to transition from RExit to U0 on the * Intel Lynx Point LP xHCI host.
*/ #define XHCI_MAX_REXIT_TIMEOUT_MS 20 struct xhci_port_cap {
u32 *psi; /* array of protocol speed ID entries */
u8 psi_count;
u8 psi_uid_count;
u8 maj_rev;
u8 min_rev;
u32 protocol_caps;
};
struct xhci_port {
__le32 __iomem *addr; int hw_portnum; int hcd_portnum; struct xhci_hub *rhub; struct xhci_port_cap *port_cap; unsignedint lpm_incapable:1; unsignedlong resume_timestamp; bool rexit_active; /* Slot ID is the index of the device directly connected to the port */ int slot_id; struct completion rexit_done; struct completion u3exit_done;
};
/* slot enabling and address device helpers */ /* these are not thread safe so use mutex */ struct mutex mutex; /* Internal mirror of the HW's dcbaa */ struct xhci_virt_device *devs[MAX_HC_SLOTS]; /* For keeping track of bandwidth domains per roothub. */ struct xhci_root_port_bw_info *rh_bw;
/* Host controller watchdog timer structures */ unsignedint xhc_state; unsignedlong run_graceperiod; struct s3_save s3; /* Host controller is dying - not responding to commands. "I'm not dead yet!" * * xHC interrupts have been disabled and a watchdog timer will (or has already) * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code * that sees this status (other than the timer that set it) should stop touching * hardware immediately. Interrupt handlers should return immediately when * they see this status (any time they drop and re-acquire xhci->lock). * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without * putting the TD on the canceled list, etc. * * There are no reports of xHCI host controllers that display this issue.
*/ #define XHCI_STATE_DYING (1 << 0) #define XHCI_STATE_HALTED (1 << 1) #define XHCI_STATE_REMOVING (1 << 2) unsignedlonglong quirks; #define XHCI_LINK_TRB_QUIRK BIT_ULL(0) #define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */ #define XHCI_NEC_HOST BIT_ULL(2) #define XHCI_AMD_PLL_FIX BIT_ULL(3) #define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) /* * Certain Intel host controllers have a limit to the number of endpoint * contexts they can handle. Ideally, they would signal that they can't handle * anymore endpoint contexts by returning a Resource Error for the Configure * Endpoint command, but they don't. Instead they expect software to keep track * of the number of active endpoints for them, across configure endpoint * commands, reset device commands, disable slot commands, and address device * commands.
*/ #define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) #define XHCI_BROKEN_MSI BIT_ULL(6) #define XHCI_RESET_ON_RESUME BIT_ULL(7) #define XHCI_SW_BW_CHECKING BIT_ULL(8) #define XHCI_AMD_0x96_HOST BIT_ULL(9) #define XHCI_TRUST_TX_LENGTH BIT_ULL(10) /* Deprecated */ #define XHCI_LPM_SUPPORT BIT_ULL(11) #define XHCI_INTEL_HOST BIT_ULL(12) #define XHCI_SPURIOUS_REBOOT BIT_ULL(13) #define XHCI_COMP_MODE_QUIRK BIT_ULL(14) #define XHCI_AVOID_BEI BIT_ULL(15) #define XHCI_PLAT BIT_ULL(16) /* Deprecated */ #define XHCI_SLOW_SUSPEND BIT_ULL(17) #define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) /* For controllers with a broken beyond repair streams implementation */ #define XHCI_BROKEN_STREAMS BIT_ULL(19) #define XHCI_PME_STUCK_QUIRK BIT_ULL(20) #define XHCI_MTK_HOST BIT_ULL(21) #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) #define XHCI_MISSING_CAS BIT_ULL(24) /* For controller with a broken Port Disable implementation */ #define XHCI_BROKEN_PORT_PED BIT_ULL(25) #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) #define XHCI_U2_DISABLE_WAKE BIT_ULL(27) #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) #define XHCI_HW_LPM_DISABLE BIT_ULL(29) #define XHCI_SUSPEND_DELAY BIT_ULL(30) #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) #define XHCI_ZERO_64B_REGS BIT_ULL(32) #define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33) #define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) #define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35) /* Reserved. It was XHCI_RENESAS_FW_QUIRK */ #define XHCI_SKIP_PHY_INIT BIT_ULL(37) #define XHCI_DISABLE_SPARSE BIT_ULL(38) #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) #define XHCI_NO_SOFT_RETRY BIT_ULL(40) #define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41) #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) #define XHCI_TRB_OVERFETCH BIT_ULL(45) #define XHCI_ZHAOXIN_HOST BIT_ULL(46) #define XHCI_WRITE_64_HI_LO BIT_ULL(47) #define XHCI_CDNS_SCTX_QUIRK BIT_ULL(48) #define XHCI_ETRON_HOST BIT_ULL(49) #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50)
unsignedint num_active_eps; unsignedint limit_active_eps; struct xhci_port *hw_ports; struct xhci_hub usb2_rhub; struct xhci_hub usb3_rhub; /* support xHCI 1.0 spec USB2 hardware LPM */ unsigned hw_lpm_support:1; /* Broken Suspend flag for SNPS Suspend resume issue */ unsigned broken_suspend:1; /* Indicates that omitting hcd is supported if root hub has no ports */ unsigned allow_single_roothub:1; /* cached extended protocol port capabilities */ struct xhci_port_cap *port_caps; unsignedint num_port_caps; /* Compliance Mode Recovery Data */ struct timer_list comp_mode_recovery_timer;
u32 port_status_u0;
u16 test_mode; /* Compliance Mode Timer Triggered every 2 seconds */ #define COMP_MODE_RCVRY_MSECS 2000
void *dbc; /* platform-specific data -- must come last */ unsignedlong priv[] __aligned(sizeof(s64));
};
/* Platform specific overrides to generic XHCI hc_driver ops */ struct xhci_driver_overrides {
size_t extra_priv_size; int (*reset)(struct usb_hcd *hcd); int (*start)(struct usb_hcd *hcd); int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); int (*check_bandwidth)(struct usb_hcd *, struct usb_device *); void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *); int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev, struct usb_tt *tt, gfp_t mem_flags); int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
u16 wIndex, char *buf, u16 wLength);
};
#define XHCI_CFC_DELAY 10
/* convert between an HCD pointer and the corresponding EHCI_HCD */ staticinlinestruct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
{ struct usb_hcd *primary_hcd;
if (usb_hcd_is_primary_hcd(hcd))
primary_hcd = hcd; else
primary_hcd = hcd->primary_hcd;
/* * Registers should always be accessed with double word or quad word accesses. * * Some xHCI implementations may support 64-bit address pointers. Registers * with 64-bit address pointers should be written to with dword accesses by * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. * xHCI implementations that do not support 64-bit address pointers will ignore * the high dword, and write order is irrelevant.
*/ staticinline u64 xhci_read_64(conststruct xhci_hcd *xhci,
__le64 __iomem *regs)
{ return lo_hi_readq(regs);
} staticinlinevoid xhci_write_64(struct xhci_hcd *xhci, const u64 val, __le64 __iomem *regs)
{
lo_hi_writeq(val, regs);
}
/* * Reportedly, some chapters of v0.95 spec said that Link TRB always has its chain bit set. * Other chapters and later specs say that it should only be set if the link is inside a TD * which continues from the end of one segment to the next segment. * * Some 0.95 hardware was found to misbehave if any link TRB doesn't have the chain bit set. * * 0.96 hardware from AMD and NEC was found to ignore unchained isochronous link TRBs when * "resynchronizing the pipe" after a Missed Service Error.
*/ staticinlinebool xhci_link_chain_quirk(struct xhci_hcd *xhci, enum xhci_ring_type type)
{ return (xhci->quirks & XHCI_LINK_TRB_QUIRK) ||
(type == TYPE_ISOC && (xhci->quirks & (XHCI_AMD_0x96_HOST | XHCI_NEC_HOST)));
}
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