#define SPINAND_MAX_ID_LEN 5 /* * For erase, write and read operation, we got the following timings : * tBERS (erase) 1ms to 4ms * tPROG 300us to 400us * tREAD 25us to 100us * In order to minimize latency, the min value is divided by 4 for the * initial delay, and dividing by 20 for the poll delay. * For reset, 5us/10us/500us if the device is respectively * reading/programming/erasing when the RESET occurs. Since we always * issue a RESET when the device is IDLE, 5us is selected for both initial * and poll delay.
*/ #define SPINAND_READ_INITIAL_DELAY_US 6 #define SPINAND_READ_POLL_DELAY_US 5 #define SPINAND_RESET_INITIAL_DELAY_US 5 #define SPINAND_RESET_POLL_DELAY_US 5 #define SPINAND_WRITE_INITIAL_DELAY_US 75 #define SPINAND_WRITE_POLL_DELAY_US 15 #define SPINAND_ERASE_INITIAL_DELAY_US 250 #define SPINAND_ERASE_POLL_DELAY_US 50
#define SPINAND_WAITRDY_TIMEOUT_MS 400
/** * struct spinand_id - SPI NAND id structure * @data: buffer containing the id bytes. Currently 4 bytes large, but can * be extended if required * @len: ID length
*/ struct spinand_id {
u8 data[SPINAND_MAX_ID_LEN]; int len;
};
/** * struct spinand_devid - SPI NAND device id structure * @id: device id of current chip * @len: number of bytes in device id * @method: method to read chip id * There are 3 possible variants: * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately * after read_id opcode. * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after * read_id opcode + 1-byte address. * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after * read_id opcode + 1 dummy byte.
*/ struct spinand_devid { const u8 *id; const u8 len; constenum spinand_readid_method method;
};
/** * struct manufacurer_ops - SPI NAND manufacturer specific operations * @init: initialize a SPI NAND device * @cleanup: cleanup a SPI NAND device * * Each SPI NAND manufacturer driver should implement this interface so that * NAND chips coming from this vendor can be initialized properly.
*/ struct spinand_manufacturer_ops { int (*init)(struct spinand_device *spinand); void (*cleanup)(struct spinand_device *spinand);
};
/** * struct spinand_manufacturer - SPI NAND manufacturer instance * @id: manufacturer ID * @name: manufacturer name * @devid_len: number of bytes in device ID * @chips: supported SPI NANDs under current manufacturer * @nchips: number of SPI NANDs available in chips array * @ops: manufacturer operations
*/ struct spinand_manufacturer {
u8 id; char *name; conststruct spinand_info *chips; const size_t nchips; conststruct spinand_manufacturer_ops *ops;
};
/** * struct spinand_op_variants - SPI NAND operation variants * @ops: the list of variants for a given operation * @nops: the number of variants * * Some operations like read-from-cache/write-to-cache have several variants * depending on the number of IO lines you use to transfer data or address * cycles. This structure is a way to describe the different variants supported * by a chip and let the core pick the best one based on the SPI mem controller * capabilities.
*/ struct spinand_op_variants { conststruct spi_mem_op *ops; unsignedint nops;
};
/** * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND * chip * @get_status: get the ECC status. Should return a positive number encoding * the number of corrected bitflips if correction was possible or * -EBADMSG if there are uncorrectable errors. I can also return * other negative error codes if the error is not caused by * uncorrectable bitflips * @ooblayout: the OOB layout used by the on-die ECC implementation
*/ struct spinand_ecc_info { int (*get_status)(struct spinand_device *spinand, u8 status); conststruct mtd_ooblayout_ops *ooblayout;
};
/** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure * @status: status of the last wait operation that will be used in case * ->get_status() is not populated by the spinand device.
*/ struct spinand_ondie_ecc_conf {
u8 status;
};
/** * struct spinand_otp_layout - structure to describe the SPI NAND OTP area * @npages: number of pages in the OTP * @start_page: start page of the user/factory OTP area.
*/ struct spinand_otp_layout { unsignedint npages; unsignedint start_page;
};
/** * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area * @info: get the OTP area information * @read: read from the SPI NAND OTP area
*/ struct spinand_fact_otp_ops { int (*info)(struct spinand_device *spinand, size_t len, struct otp_info *buf, size_t *retlen); int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
size_t *retlen, u8 *buf);
};
/** * struct spinand_user_otp_ops - SPI NAND OTP methods for user area * @info: get the OTP area information * @lock: lock an OTP region * @erase: erase an OTP region * @read: read from the SPI NAND OTP area * @write: write to the SPI NAND OTP area
*/ struct spinand_user_otp_ops { int (*info)(struct spinand_device *spinand, size_t len, struct otp_info *buf, size_t *retlen); int (*lock)(struct spinand_device *spinand, loff_t from, size_t len); int (*erase)(struct spinand_device *spinand, loff_t from, size_t len); int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
size_t *retlen, u8 *buf); int (*write)(struct spinand_device *spinand, loff_t from, size_t len,
size_t *retlen, const u8 *buf);
};
/** * struct spinand_device - SPI NAND device instance * @base: NAND device instance * @spimem: pointer to the SPI mem object * @lock: lock used to serialize accesses to the NAND * @id: NAND ID as returned by READ_ID * @flags: NAND flags * @op_templates: various SPI mem op templates * @op_templates.read_cache: read cache op template * @op_templates.write_cache: write cache op template * @op_templates.update_cache: update cache op template * @select_target: select a specific target/die. Usually called before sending * a command addressing a page or an eraseblock embedded in * this die. Only required if your chip exposes several dies * @cur_target: currently selected target/die * @eccinfo: on-die ECC information * @cfg_cache: config register cache. One entry per die * @databuf: bounce buffer for data * @oobbuf: bounce buffer for OOB data * @scratchbuf: buffer used for everything but page accesses. This is needed * because the spi-mem interface explicitly requests that buffers * passed in spi_mem_op be DMA-able, so we can't based the bufs on * the stack * @manufacturer: SPI NAND manufacturer information * @configure_chip: Align the chip configuration with the core settings * @cont_read_possible: Field filled by the core once the whole system * configuration is known to tell whether continuous reads are * suitable to use or not in general with this chip/configuration. * A per-transfer check must of course be done to ensure it is * actually relevant to enable this feature. * @set_cont_read: Enable/disable the continuous read feature * @priv: manufacturer private data * @fact_otp: SPI NAND factory OTP info. * @user_otp: SPI NAND user OTP info. * @read_retries: the number of read retry modes supported * @set_read_retry: Enable/disable the read retry feature
*/ struct spinand_device { struct nand_device base; struct spi_mem *spimem; struct mutex lock; struct spinand_id id;
u32 flags;
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