/* Delay for the VAG ramp up */ #define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */ /* Delay for the VAG ramp down */ #define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
/* When VAG powering on to get local loop from Line-In, the sleep * is required to avoid loud pop.
*/ if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN &&
source == HP_POWER_EVENT)
msleep(SGTL5000_VAG_POWERUP_DELAY);
}
/* count dac/adc consumers unconditional */ if (ana_pwr_reg & SGTL5000_DAC_POWERUP)
consumers++; if (ana_pwr_reg & SGTL5000_ADC_POWERUP)
consumers++;
/* * If the event comes from HP and Line-In is selected, * current action is 'DAC to be powered down'. * As HP_POWERUP is not set when HP muxed to line-in, * we need to keep VAG power ON.
*/ if (source == HP_POWER_EVENT) { if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN)
consumers++;
} else { if (ana_pwr_reg & SGTL5000_HP_POWERUP)
consumers++;
}
/* * This function calls when any of VAG power consumers is disappearing. * Thus, if there is more than one consumer at the moment, as minimum * one consumer will definitely stay after the end of the current * event. * Don't clear VAG_POWERUP if 2 or more consumers of VAG present: * - LINE_IN (for HP events) / HP (for DAC/ADC events) * - DAC * - ADC * (the current consumer is disappearing right now)
*/ if (vag_power_consumers(component, ana_pwr, source) >= 2) return;
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_VAG_POWERUP, 0); /* In power down case, we need wait 400-1000 ms * when VAG fully ramped down. * As longer we wait, as smaller pop we've got.
*/
msleep(SGTL5000_VAG_POWERDOWN_DELAY);
}
/* * mic_bias power on/off share the same register bits with * output impedance of mic bias, when power on mic bias, we * need reclaim it to impedance value. * 0x0 = Powered off * 0x1 = 2Kohm * 0x2 = 4Kohm * 0x3 = 8Kohm
*/ staticint mic_bias_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event)
{ struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
switch (event) { case SND_SOC_DAPM_POST_PMU: /* change mic bias resistor */
snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
SGTL5000_BIAS_R_MASK,
sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); break;
staticint vag_and_mute_control(struct snd_soc_component *component, int event, int event_source)
{ staticconst u16 mute_mask[] = { /* * Mask for HP_POWER_EVENT. * Muxing Headphones have to be wrapped with mute/unmute * headphones only.
*/
SGTL5000_HP_MUTE, /* * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT. * Muxing DAC or ADC block have to wrapped with mute/unmute * both headphones and line-out.
*/
SGTL5000_OUTPUTS_MUTE,
SGTL5000_OUTPUTS_MUTE
};
switch (event) { case SND_SOC_DAPM_PRE_PMU:
sgtl5000->mute_state[event_source] =
mute_output(component, mute_mask[event_source]); break; case SND_SOC_DAPM_POST_PMU:
vag_power_on(component, event_source);
restore_output(component, mute_mask[event_source],
sgtl5000->mute_state[event_source]); break; case SND_SOC_DAPM_PRE_PMD:
sgtl5000->mute_state[event_source] =
mute_output(component, mute_mask[event_source]);
vag_power_off(component, event_source); break; case SND_SOC_DAPM_POST_PMD:
restore_output(component, mute_mask[event_source],
sgtl5000->mute_state[event_source]); break; default: break;
}
return 0;
}
/* * Mute Headphone when power it up/down. * Control VAG power on HP power path.
*/ staticint headphone_pga_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event)
{ struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
/* As manual describes, ADC/DAC powering up/down requires * to mute outputs to avoid pops. * Control VAG power on ADC/DAC power path.
*/ staticint adc_updown_depop(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event)
{ struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
/* custom function to fetch info of PCM playback volume */ staticint dac_info_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 2;
uinfo->value.integer.min = 0;
uinfo->value.integer.max = 0xfc - 0x3c; return 0;
}
/* * custom function to get of PCM playback volume * * dac volume register * 15-------------8-7--------------0 * | R channel vol | L channel vol | * ------------------------------- * * PCM volume with 0.5017 dB steps from 0 to -90 dB * * register values map to dB * 0x3B and less = Reserved * 0x3C = 0 dB * 0x3D = -0.5 dB * 0xF0 = -90 dB * 0xFC and greater = Muted * * register value map to userspace value * * register value 0x3c(0dB) 0xf0(-90dB)0xfc * ------------------------------ * userspace value 0xc0 0
*/ staticint dac_get_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); int reg; int l; int r;
/* * custom function to put of PCM playback volume * * dac volume register * 15-------------8-7--------------0 * | R channel vol | L channel vol | * ------------------------------- * * PCM volume with 0.5017 dB steps from 0 to -90 dB * * register values map to dB * 0x3B and less = Reserved * 0x3C = 0 dB * 0x3D = -0.5 dB * 0xF0 = -90 dB * 0xFC and greater = Muted * * userspace value map to register value * * userspace value 0xc0 0 * ------------------------------ * register value 0x3c(0dB) 0xf0(-90dB)0xfc
*/ staticint dac_put_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); int reg; int l; int r;
l = ucontrol->value.integer.value[0];
r = ucontrol->value.integer.value[1];
/* make sure userspace volume fall in (0, 0xfc-0x3c) */
l = clamp(l, 0, 0xfc - 0x3c);
r = clamp(r, 0, 0xfc - 0x3c);
/* invert it, get the value can be set to register */
l = 0xfc - l;
r = 0xfc - r;
/* shift to get the register value */
reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
/* * custom function to get AVC threshold * * The threshold dB is calculated by rearranging the calculation from the * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==> * dB = ( fls(register_value) - 14.347 ) * 6.02 * * As this calculation is expensive and the threshold dB values may not exceed * 0 to 96 we use pre-calculated values.
*/ staticint avc_get_threshold(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); int db, i;
u16 reg = snd_soc_component_read(component, SGTL5000_DAP_AVC_THRESHOLD);
/* register value 0 => -96dB */ if (!reg) {
ucontrol->value.integer.value[0] = 96;
ucontrol->value.integer.value[1] = 96; return 0;
}
/* get dB from register value (rounded down) */ for (i = 0; avc_thr_db2reg[i] > reg; i++)
;
db = i;
/* * custom function to put AVC threshold * * The register value is calculated by following formula: * register_value = 10^(dB/20) * 0.636 * 2^15 * As this calculation is expensive and the threshold dB values may not exceed * 0 to 96 we use pre-calculated values.
*/ staticint avc_put_threshold(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); int db;
u16 reg;
db = (int)ucontrol->value.integer.value[0]; if (db < 0 || db > 96) return -EINVAL;
reg = avc_thr_db2reg[db];
snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg);
/* mute the codec used by alsa core */ staticint sgtl5000_mute_stream(struct snd_soc_dai *codec_dai, int mute, int direction)
{ struct snd_soc_component *component = codec_dai->component;
u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP;
/* * During 'digital mute' do not mute DAC * because LINE_IN would be muted aswell. We want to mute * only I2S block - this can be done by powering it off
*/
snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER,
i2s_pwr, mute ? 0 : i2s_pwr);
/* * set clock according to i2s frame clock, * sgtl5000 provides 2 clock sources: * 1. sys_mclk: sample freq can only be configured to * 1/256, 1/384, 1/512 of sys_mclk. * 2. pll: can derive any audio clocks. * * clock setting rules: * 1. in slave mode, only sys_mclk can be used * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz * and above. * 3. usage of sys_mclk is preferred over pll to save power.
*/ staticint sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate)
{ struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); int clk_ctl = 0; int sys_fs; /* sample freq */
/* * sample freq should be divided by frame clock, * if frame clock is lower than 44.1 kHz, sample freq should be set to * 32 kHz or 44.1 kHz.
*/ switch (frame_rate) { case 8000: case 16000:
sys_fs = 32000; break; case 11025: case 22050:
sys_fs = 44100; break; default:
sys_fs = frame_rate; break;
}
/* set divided factor of frame clock */ switch (sys_fs / frame_rate) { case 4:
clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; break; case 2:
clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; break; case 1:
clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; break; default: return -EINVAL;
}
/* set the sys_fs according to frame rate */ switch (sys_fs) { case 32000:
clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; break; case 44100:
clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; break; case 48000:
clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; break; case 96000:
clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; break; default:
dev_err(component->dev, "frame rate %d not supported\n",
frame_rate); return -EINVAL;
}
/* * calculate the divider of mclk/sample_freq, * factor of freq = 96 kHz can only be 256, since mclk is in the range * of 8 MHz - 27 MHz
*/ switch (sgtl5000->sysclk / frame_rate) { case 256:
clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
SGTL5000_MCLK_FREQ_SHIFT; break; case 384:
clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
SGTL5000_MCLK_FREQ_SHIFT; break; case 512:
clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
SGTL5000_MCLK_FREQ_SHIFT; break; default: /* if mclk does not satisfy the divider, use pll */ if (sgtl5000->master) {
clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
SGTL5000_MCLK_FREQ_SHIFT;
} else {
dev_err(component->dev, "PLL not supported in slave mode\n");
dev_err(component->dev, "%d ratio is not supported. " "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
sgtl5000->sysclk / frame_rate); return -EINVAL;
}
}
/* if using pll, please check manual 6.4.2 for detail */ if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
u64 out, t; int div2; int pll_ctl; unsignedint in, int_div, frac_div;
if (sgtl5000->sysclk > 17000000) {
div2 = 1;
in = sgtl5000->sysclk / 2;
} else {
div2 = 0;
in = sgtl5000->sysclk;
} if (sys_fs == 44100)
out = 180633600; else
out = 196608000;
t = do_div(out, in);
int_div = out;
t *= 2048;
do_div(t, in);
frac_div = t;
pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
/* power up pll */
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
/* if using pll, clk_ctrl must be set after pll power up */
snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
} else { /* otherwise, clk_ctrl must be set before pll power down */
snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
/* power down pll */
snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
0);
}
return 0;
}
/* * Set PCM DAI bit size and sample rate. * input: params_rate, params_fmt
*/ staticint sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{ struct snd_soc_component *component = dai->component; struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); int channels = params_channels(params); int i2s_ctl = 0; int stereo; int ret;
/* sysclk should already set */ if (!sgtl5000->sysclk) {
dev_err(component->dev, "%s: set sysclk first!\n", __func__); return -EFAULT;
}
/* * set dac bias * common state changes: * startup: * off --> standby --> prepare --> on * standby --> prepare --> on * * stop: * on --> prepare --> standby
*/ staticint sgtl5000_set_bias_level(struct snd_soc_component *component, enum snd_soc_bias_level level)
{ struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component); int ret;
switch (level) { case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: case SND_SOC_BIAS_STANDBY:
regcache_cache_only(sgtl->regmap, false);
ret = regcache_sync(sgtl->regmap); if (ret) {
regcache_cache_only(sgtl->regmap, true); return ret;
}
staticbool sgtl5000_volatile(struct device *dev, unsignedint reg)
{ switch (reg) { case SGTL5000_CHIP_ID: case SGTL5000_CHIP_ADCDAC_CTRL: case SGTL5000_CHIP_ANA_STATUS: returntrue;
}
returnfalse;
}
staticbool sgtl5000_readable(struct device *dev, unsignedint reg)
{ switch (reg) { case SGTL5000_CHIP_ID: case SGTL5000_CHIP_DIG_POWER: case SGTL5000_CHIP_CLK_CTRL: case SGTL5000_CHIP_I2S_CTRL: case SGTL5000_CHIP_SSS_CTRL: case SGTL5000_CHIP_ADCDAC_CTRL: case SGTL5000_CHIP_DAC_VOL: case SGTL5000_CHIP_PAD_STRENGTH: case SGTL5000_CHIP_ANA_ADC_CTRL: case SGTL5000_CHIP_ANA_HP_CTRL: case SGTL5000_CHIP_ANA_CTRL: case SGTL5000_CHIP_LINREG_CTRL: case SGTL5000_CHIP_REF_CTRL: case SGTL5000_CHIP_MIC_CTRL: case SGTL5000_CHIP_LINE_OUT_CTRL: case SGTL5000_CHIP_LINE_OUT_VOL: case SGTL5000_CHIP_ANA_POWER: case SGTL5000_CHIP_PLL_CTRL: case SGTL5000_CHIP_CLK_TOP_CTRL: case SGTL5000_CHIP_ANA_STATUS: case SGTL5000_CHIP_SHORT_CTRL: case SGTL5000_CHIP_ANA_TEST2: case SGTL5000_DAP_CTRL: case SGTL5000_DAP_PEQ: case SGTL5000_DAP_BASS_ENHANCE: case SGTL5000_DAP_BASS_ENHANCE_CTRL: case SGTL5000_DAP_AUDIO_EQ: case SGTL5000_DAP_SURROUND: case SGTL5000_DAP_FLT_COEF_ACCESS: case SGTL5000_DAP_COEF_WR_B0_MSB: case SGTL5000_DAP_COEF_WR_B0_LSB: case SGTL5000_DAP_EQ_BASS_BAND0: case SGTL5000_DAP_EQ_BASS_BAND1: case SGTL5000_DAP_EQ_BASS_BAND2: case SGTL5000_DAP_EQ_BASS_BAND3: case SGTL5000_DAP_EQ_BASS_BAND4: case SGTL5000_DAP_MAIN_CHAN: case SGTL5000_DAP_MIX_CHAN: case SGTL5000_DAP_AVC_CTRL: case SGTL5000_DAP_AVC_THRESHOLD: case SGTL5000_DAP_AVC_ATTACK: case SGTL5000_DAP_AVC_DECAY: case SGTL5000_DAP_COEF_WR_B1_MSB: case SGTL5000_DAP_COEF_WR_B1_LSB: case SGTL5000_DAP_COEF_WR_B2_MSB: case SGTL5000_DAP_COEF_WR_B2_LSB: case SGTL5000_DAP_COEF_WR_A1_MSB: case SGTL5000_DAP_COEF_WR_A1_LSB: case SGTL5000_DAP_COEF_WR_A2_MSB: case SGTL5000_DAP_COEF_WR_A2_LSB: returntrue;
default: returnfalse;
}
}
/* * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL * The calculatation was done for all possible register values which * is the array index and the following formula: 10^((idx−15)/40) * 100
*/ staticconst u8 vol_quot_table[] = {
42, 45, 47, 50, 53, 56, 60, 63,
67, 71, 75, 79, 84, 89, 94, 100,
106, 112, 119, 126, 133, 141, 150, 158,
168, 178, 188, 200, 211, 224, 237, 251
};
/* * sgtl5000 has 3 internal power supplies: * 1. VAG, normally set to vdda/2 * 2. charge pump, set to different value * according to voltage of vdda and vddio * 3. line out VAG, normally set to vddio/2 * * and should be set according to: * 1. vddd provided by external or not * 2. vdda and vddio voltage value. > 3.1v or not
*/ staticint sgtl5000_set_power_regs(struct snd_soc_component *component)
{ int vddd; int vdda; int vddio;
u16 ana_pwr;
u16 lreg_ctrl; int vag; int lo_vag; int vol_quot; int lo_vol;
size_t i; struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
if (vdda <= 0 || vddio <= 0 || vddd < 0) {
dev_err(component->dev, "regulator voltage not set correctly\n");
return -EINVAL;
}
/* according to datasheet, maximum voltage of supplies */ if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
dev_err(component->dev, "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
vdda, vddio, vddd);
/* * Set lineout output level in range (0..31) * the same value is used for right and left channel * * Searching for a suitable index solving this formula: * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
*/
vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
lo_vol = 0; for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) { if (vol_quot >= vol_quot_table[i])
lo_vol = i; else break;
}
staticint sgtl5000_enable_regulators(struct i2c_client *client)
{ int ret; int i; int external_vddd = 0; struct regulator *vddd; struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
sgtl5000->supplies[i].supply = supply_names[i];
vddd = regulator_get_optional(&client->dev, "VDDD"); if (IS_ERR(vddd)) { /* See if it's just not registered yet */ if (PTR_ERR(vddd) == -EPROBE_DEFER) return -EPROBE_DEFER;
} else {
external_vddd = 1;
regulator_put(vddd);
}
sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
- 1 + external_vddd;
ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
sgtl5000->supplies); if (ret) return ret;
ret = regulator_bulk_enable(sgtl5000->num_supplies,
sgtl5000->supplies); if (!ret)
usleep_range(10, 20); else
regulator_bulk_free(sgtl5000->num_supplies,
sgtl5000->supplies);
/* power up sgtl5000 */
ret = sgtl5000_set_power_regs(component); if (ret) goto err;
/* enable small pop, introduce 400ms delay in turning off */
snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
SGTL5000_SMALL_POP, SGTL5000_SMALL_POP);
/* disable short cut detector */
snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0);
/* * Write all the default values from sgtl5000_reg_defaults[] array into the * sgtl5000 registers, to make sure we always start with the sane registers * values as stated in the datasheet. * * Since sgtl5000 does not have a reset line, nor a reset command in software, * we follow this approach to guarantee we always start from the default values * and avoid problems like, not being able to probe after an audio playback * followed by a system reset or a 'reboot' command in Linux
*/ staticvoid sgtl5000_fill_defaults(struct i2c_client *client)
{ struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); int i, ret, val, index;
for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
val = sgtl5000_reg_defaults[i].def;
index = sgtl5000_reg_defaults[i].reg;
ret = regmap_write(sgtl5000->regmap, index, val); if (ret)
dev_err(&client->dev, "%s: error %d setting reg 0x%02x to 0x%04x\n",
__func__, ret, index, val);
}
}
sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); if (!sgtl5000) return -ENOMEM;
i2c_set_clientdata(client, sgtl5000);
ret = sgtl5000_enable_regulators(client); if (ret) return ret;
sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); if (IS_ERR(sgtl5000->regmap)) {
ret = PTR_ERR(sgtl5000->regmap);
dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); goto disable_regs;
}
sgtl5000->mclk = devm_clk_get(&client->dev, NULL); if (IS_ERR(sgtl5000->mclk)) {
ret = PTR_ERR(sgtl5000->mclk); /* Defer the probe to see if the clk will be provided later */ if (ret == -ENOENT)
ret = -EPROBE_DEFER;
dev_err_probe(&client->dev, ret, "Failed to get mclock\n");
goto disable_regs;
}
ret = clk_prepare_enable(sgtl5000->mclk); if (ret) {
dev_err(&client->dev, "Error enabling clock %d\n", ret); goto disable_regs;
}
/* Need 8 clocks before I2C accesses */
udelay(1);
/* read chip information */
ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); if (ret) {
dev_err(&client->dev, "Error reading chip id %d\n", ret); goto disable_clk;
}
if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
SGTL5000_PARTID_PART_ID) {
dev_err(&client->dev, "Device with ID register %x is not a sgtl5000\n", reg);
ret = -ENODEV; goto disable_clk;
}
/* reconfigure the clocks in case we're using the PLL */
ret = regmap_write(sgtl5000->regmap,
SGTL5000_CHIP_CLK_CTRL,
SGTL5000_CHIP_CLK_CTRL_DEFAULT); if (ret)
dev_err(&client->dev, "Error %d initializing CHIP_CLK_CTRL\n", ret);
/* Mute everything to avoid pop from the following power-up */
ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL,
SGTL5000_CHIP_ANA_CTRL_DEFAULT); if (ret) {
dev_err(&client->dev, "Error %d muting outputs via CHIP_ANA_CTRL\n", ret); goto disable_clk;
}
/* * If VAG is powered-on (e.g. from previous boot), it would be disabled * by the write to ANA_POWER in later steps of the probe code. This * may create a loud pop even with all outputs muted. The proper way * to circumvent this is disabling the bit first and waiting the proper * cool-down time.
*/
ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value); if (ret) {
dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret); goto disable_clk;
} if (value & SGTL5000_VAG_POWERUP) {
ret = regmap_update_bits(sgtl5000->regmap,
SGTL5000_CHIP_ANA_POWER,
SGTL5000_VAG_POWERUP,
0); if (ret) {
dev_err(&client->dev, "Error %d disabling VAG\n", ret); goto disable_clk;
}
msleep(SGTL5000_VAG_POWERDOWN_DELAY);
}
/* Follow section 2.2.1.1 of AN3663 */
ana_pwr = SGTL5000_ANA_POWER_DEFAULT; if (sgtl5000->num_supplies <= VDDD) { /* internal VDDD at 1.2V */
ret = regmap_update_bits(sgtl5000->regmap,
SGTL5000_CHIP_LINREG_CTRL,
SGTL5000_LINREG_VDDD_MASK,
LINREG_VDDD); if (ret)
dev_err(&client->dev, "Error %d setting LINREG_VDDD\n", ret);
ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
dev_info(&client->dev, "Using internal LDO instead of VDDD: check ER1 erratum\n");
} else { /* using external LDO for VDDD * Clear startup powerup and simple powerup * bits to save power
*/
ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
| SGTL5000_LINREG_SIMPLE_POWERUP);
dev_dbg(&client->dev, "Using external VDDD\n");
}
ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr); if (ret)
dev_err(&client->dev, "Error %d setting CHIP_ANA_POWER to %04x\n",
ret, ana_pwr);
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.
