dnl AMD64 mpn_sbpi1_bdiv_r optimised for Intel Broadwell.
dnl Copyright 2015, 2021 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C cycles/limb mul_1 addmul_1
C AMD K8,K9 n/a n/a
C AMD K10 n/a n/a
C AMD bd1 n/a n/a
C AMD bd2 n/a n/a
C AMD bd3 n/a n/a
C AMD bd4 ? ?
C AMD zn1 ? ?
C AMD zn2 ? ?
C AMD zn3 ? ?
C AMD bt1 n/a n/a
C AMD bt2 n/a n/a
C Intel P4 n/a n/a
C Intel PNR n/a n/a
C Intel NHM n/a n/a
C Intel SBR n/a n/a
C Intel IBR n/a n/a
C Intel HWL 1.68 n/a
C Intel BWL 1.51 1.67-1.74
C Intel SKL 1.52 1.63-1.71
C Intel atom n/a n/a
C Intel SLM n/a n/a
C VIA nano n/a n/a
C The inner loops of thiscode are the result of running a code generation and
C optimisation tool suite written by David Harvey and Torbjorn Granlund.
C TODO
C * Do overlapped software pipelining.
C * Reduce register use, i.e., by combining n_neg and n_save.
C * Supporess initial store through up, it's always a zero.
C * Streamline up and dp setup.
C * When changing this, make sure the code which falls into the inner loops
C does not execute too many no-ops (for both PIC and non-PIC).
lea -8(,dn_param,8), n_neg neg n_neg mov dn_param, n_save mov R32(dn_param), R32(%rax) shr $3, n_save C loop count and $7, R32(%rax) C clear CF and OF as side-effect
L(end): adox( (up), w0)
adox( %rcx, w1) C relies on rcx = 0 mov w0, (up) adc %rcx, w1 C relies on rcx = 0 mov 8(up,n_neg), q C Compute next quotient early...
mulx( dinv, q, %r12) C ...(unused in last iteration)
bt $0, R32(%r13) adc w1, 8(up)
setc R8(%r13) dec un C clear OF as side-effect jz L(done)
lea (dp,n_neg), dp C reset dp to D[]'s beginning lea 8(up,n_neg), up C point up to U[]'s current beginning
L(outer): mov n_save, n
test %eax, %eax C clear CF and OF jmp *jaddr
L(1): mov (dp_param), %r10 xor R32(%rax), R32(%rax) mov (up), %rdx dec un mov %rdx, %r9
L(o1): mulx( dinv, %rdx, %r11) C next quotient lea 8(up), up
mulx( %r10, %rcx, %rdx) C 0 1 add %r9, %rcx C 0 adc %rax, %rdx C 1 add (up), %rdx C 1
setc R8(%rax) C 2 mov %rdx, %r9 C 1 dec un jnz L(o1) mov %r9, (up)
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