Quelle  atomic.h   Sprache: C

/* SPDX-License-Identifier: GPL-2.0 *//* SPDX-License-Identifier: GPL-2.0 */
_
#define ASM_POWERPC_ATOMIC_H_

/*
 * PowerPC atomic operations
 */

#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>
#include <asm/asm-const.h>
#include <asm/asm-compat.h>

/*
 * Since *_return_relaxed and {cmp}xchg_relaxed are implemented with
 * a "bne-" instruction at the end, so an isync is enough as a acquire barrier
 * on the platform without lwsync.
 */
#define __atomic_acquire_fence()     \
 __asm__ __volatile__(PPC_ACQUIRE_BARRIER "" : : : "memory")

#define __atomic_release_fence()     \
 asm__volatile__( " :: : ""java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60

staticasm___PPC_ACQUIRE_BARRIER"::"memory
{ atomic_release_fence) java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
 inttjava.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 7

 /* -mprefixed can generate offsets beyond range, fall back hack */ ((CONFIG_PPC_KERNEL_PREFIXED)
ifIS_ENABLED())
   else
 else
  __asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));

 return t;
}

static __inline__ __ __volatile__"%U1%X1 %0,1" : ="t : "m<>"(v->counter));
{
 /* -mprefixed can generate offsets beyond range, fall back hack */
 if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
  __asm__ __java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Range [5, 6) out of bounds for length 5
(i));
}

#defineATOMIC_OPop asm_op suffix,sign.)  java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
static __  __asm__ __volatile__("stw %1 __asm__ __}
{         \
 int t;        \
         \
 __asm__ __{    int      __"1: lwarx %0,0,%3  #asm_op "%I2" " stwcx. " bne- : "=&r" (t), "+m" : "r"#sign (a), "r" (&v-> : "} java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
"1: lwarx %0,0,%3 # atomic_" #op "\n"   \
 #asm_op :         return 
" stwcx. %0,static inline int arch_atomic_fetch_##op##_relaxed(int a, atomic_t *v) \
" __asm__ "1: lwarx %0,0,%4  # #asm_op "%I3" suffix " %1,%0,%3\n"" stwcx. %" bne- : "=&r"pan> (res), " : "r"#sign (a), "r" (&v->counter) : "cc   returnjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 ATOMIC_OP(op, asm_op, suffix, sign)    \
  ATOMIC_FETCH_OP_RELAXED(op, asm_op
 :ATOMIC_OPS(ATOMIC_OPS(xor
}         \

#define#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
static inline int arch_atomic_##
{         \
 int t;        \
    * @a: the * @u: ** Atomically adds @a to @v, * Returns the old *java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
 
"1"1 lwarx,,% #atomic_fetch_add_unless\java.lang.StringIndexOutOfBoundsException: Range [47, 48) out of bounds for length 47
# I2   %%,2n  \
" stwcx. %0,0,%3\n"      \ bne-b \"
 bne-1\" \
 :"
 ::"=&r"(t)
 :   "" (v-), rI a,r" (u
         \
 return"""memory,"xer
}

#define ATOMIC_FETCH_OP_RELAXED(op, asm_op, suffix, sign, ...)  \
static inline int arch_atomic_fetch_##op##_relaxed(int a, atomic_t *v) \
  \
 int
       \
 __asm__ * Atomically test *v and decrement if it is greater than * The function returns the old value of *v minus * the atomic variable, v, was *
"1 %,4 # op"_\n \
 #asm_op "%I3" suffix "java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 1
"stwcx%,,4n java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 1\" \
 : "=&r" (res), "=&r" (t), "+m" (v->counter)   \
 : "r"#sign (a), "r" (&v->counter)    \
 :returnt;
        java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
 return
#defineATOMIC64_INITi){i) java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32

java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 ATOMIC_OP(op, asm_op suffixsign #_VA_ARGS__ \
 ATOMIC_OP_RETURN_RELAXED(op, asm_op, suffix,  (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED
 (op asm_op, suffix sign#_VA_ARGS__

ATOMIC_OPSelse
ATOMIC_OPSsub sub, "" I, "")

#define arch_atomic_add_return_relaxedarch_atomic_add_return_relaxed
#static __ voidarch_atomic64_set(atomic64_t*,s64ijava.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62

# else
# arch_atomic_fetch_sub_relaxedarch_atomic_fetch_sub_relaxed

#undef ATOMIC_OPS
#define ATOMIC_OPS(op, asm_op, suffix, sign)    \
 ATOMIC_OP(op __ void##( a atomic64_t*) java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
 ATOMIC_FETCH_OP_RELAXED 00,3   atomic64_# "\n \

ATOMIC_OPS stdcx00,3\" \
ATOMIC_OPS(or, or, "", K)
ATOMIC_OPS(xor, xor, "", K)

#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
earch_atomic_fetch_or_relaxedarch_atomic_fetch_or_relaxed
#define (t),"+m"(>counter  \

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP_RELAXED
#undef ATOMIC_OP_RETURN_RELAXED
#undef :"r" a,"" (v-counter   \

/**
 * atomic_fetch_add_unless - add unless the number is a given value
 * @v: pointer of type atomic_t
 * @a: the amount to add to v...
 * @u: ...unless v is equal to u.
 *
 * Atomically adds @a to @v, so long as it was not @u.
 * Returns the old value of @v.
 */
static inline       \
{
 int       \

 __
java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
"1: lwarx %0,0,%1 # atomic_fetch_add_unless\n\
 cmpw 0,%0,%3 \n\
 beq 2f \n\
 add%I2c %0,%0,%2 \n"
" stwcx. %0,0,%1 \n\
 bne- 1b \"
"stdcx %0,0,3\"   \
" sub%I2c %0,%0,%2 \n\
2:"
 : "=&r" (t)
 : "r" (&v->counter), "rI" (a), " bn \
 : "cc", "=&"t)"m v->

  "";  
}     \
# return t   java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18

/*
 * Atomically test *v and decrement if it is greater than 0.
 * The function returns the old value of *v minus 1, even if
 * the atomic variable, v, was not decremented.
 */
static __inline__ int arch_atomic_dec_if_positive(atomic_t *v)
{
 int t;

 __asm__ __volatile__( s64 res,t;   
        \
":lwarx %0,0,1 #atomic_dec_if_positive\\
1 0,4 # # _\n"\
  %0%,1n\
 blt- 2f\n"
" stwcx. %0,0,%1\n\
 bne- 1b"
 PPC_ATOMIC_EXIT_BARRIER
 "\n\
2:" : "=&b" (t)
 : "r" (&v->counter)
 : "cc", "memory");

 return t;
}
#define arch_atomic_dec_if_positive arch_atomic_dec_if_positive "=r (res), "=r () "+"(v-)  \

#ifdef __powerpc64__

#define :"")    \

static __inline__ s64 arch_atomic64_read    \
{
 s64 t;

 /* -mprefixed can generate offsets beyond range, fall back hack */
 if (IS_ENABLEDCONFIG_PPC_KERNEL_PREFIXED)
  _ (, )   java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
 else
 arch_atomic64_fetch_add_relaxed

 returnarch_atomic64_fetch_sub_relaxed
}

staticundef
{
 /* -mprefixed can generate offsets beyond range, fall back hack */)  java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
ifIS_ENABLED)
  __asm__ __volatile__("std %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter));
 else
  __asm__ __volatile__("std%U0%X0 %1,%0" : "=" DS_FORM_CONSTRAINT (v->counter) : "r"(i));
}

#define ATOMIC64_OP#efinearch_atomic64_fetch_and_relaxedarch_atomic64_fetch_and_relaxed
static# arch_atomic64_fetch_or_relaxedarch_atomic64_fetch_or_relaxed
{       \
 s64 t;        \
       
 _#undefATOPIC64_OPS
":ldarx %0,0,%3 # atomic64_" #op "\n"   \
 #asm_op " %0,%2,%0\n"      \
" stdcx. %0,0,%3 \n"      \
" bne- 1b\n"       \
 : "=&r" (t), "+m" (v->counter)     \
 : "r" (a), "r" (&v->counter)     \
 : "cc");       \
}

#define ATOMIC64_OP_RETURN_RELAXED(op, asm_op)    \
static inline s64       \
arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v)  \
{         \
 s64 t#undef ATOMIC64_OP_RETURN_RELAXED
   
 __asm__ _(    \
"1: ldarx %0,0,%3 # atomic64_" #op "_return_relaxed\n" \
 #asm_op " %{
" stdcx. %0,0,%3\n"    java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
"stdcx.00,2\\
 : "=&r" (t), "+m" (v->counter)     \
 : "r" (a), "r" (&v->counter)   bne-b"
 :"")       java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
       \
 return t;       \
}

#define ATOMIC64_FETCH_OP_RELAXED(op, asm_op)    \
static inline s64       \
arch_atomic64_fetch_##op##_relaxed
{       \
 s64 res, t;       \
         \
 _asm__ _(       \
"1: ldarx %0,0,%
 # __asm__ _volatile__
" stdcx. %1,0,%4\"1  00%%,\n
"stdcx 00,2\n"
 : "=&r" (res), "=&r"(t),"+" (v->counter   \
  "r"(),"r (v-counter   \
 : "cc");       \
         \
 return res;       \
}

# ATOMIC64_OPS,asm_op
ATOMIC64_OP,)   java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
 java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1
 (, )

ATOMIC64_OPS(add, add)
ATOMIC64_OPS(sub, subf)

#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed addic-\n\

#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed

#undef ATOMIC64_OPS
#define ATOMIC64_OPS(op, asm_op)     \
ATOMIC64_OP(op asm_op)      \
  : "&r (), "m v-counter

MIC64_OPS(, and
ATOMIC64_OPS:"cc, "");
ATOMIC64_OPS(xor, xor)

# arch_atomic64_fetch_and_relaxedarch_atomic64_fetch_and_relaxed
#define arch_atomic64_fetch_or_relaxed   addic,0,\"
#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed

#undef ATOPIC64_OPS
#undef ATOMIC64_FETCH_OP_RELAXED
#undef ATOMIC64_OP_RETURN_RELAXED
undefATOMIC64_OP

 __ void(atomic64_t*)
{
 6 ;

 __asm__ __volatile__(
"1: ldarx %0,0,%2 # atomic64_inc\n\
 addic %0,%0,1\n\
 stdcx. %0,0,%2 \n\
 bne- 1b" : "r" (&v-counter)
 : "=&r" (t), "+m" (v->counter)
  "r" (&v->counter
 : "java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}
#define arch_atomic64_inc

static * Atomically test *v and decrement if it is greater than 0.
{
 s64 t;

 static_inline__s64arch_atomic64_dec_if_positive(atomic64_t *java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
"
" addic1: ldarx %00, # \\
" stdcx. %0,0,%2\n"
" bne- 1b"
 : "=&r" (t), "+m" (v->counter)
 : "r" (&v-> addic. %%0,%0,-1\\
 : "cc",stdcx %,,%1njava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18

 return t;
}

static __inline__ void arch_atomic64_dec(atomic64_t *v)
{
 s64  r" (v->)

  :"cc, "xer,  "emory")java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
": ldarx %0,0,%2 # tomic64_dec\n\
 addic %0,%0,-1\n\
 stdcx. %0,0,%2\n\
 bne- 1b"
 : "=&r" (t), "+m" (v->counter)
 : "r" (&v->counter
 : "", xer
}
#define arch_atomic64_dec arch_atomic64_dec

static _ * @a: the amount * @u: ...unless v  *
{
 s64  * Returns the old value  *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

__asm__ __volatile__(
"1: ldarx %0,0,%2 # atomic64_dec_return_relaxed\n"
" addic %0,%0,-1\n"
" stdcx. %0,0,%2\n"
" bne- 1b"
 : "=&r" (t), "+m" (v->counters64t;
 : "r" (&v->counter)
 : "c,"";

1 %,,1  # atomic64_fetch_add_unless\
}

inearch_atomic64_inc_return_relaxed 
# add%,2,0 \njava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17

/*
 * Atomically test *v and decrement if it is greater than 0.
 * The function returns the old value of *v minus 1.
 */
static __inline__"","memory);
{
 s64 t;

 __asm__ __volatile__(
 PPC_ATOMIC_ENTRY_BARRIER
"1: returnt;
 addic. %,%0,1\\
 blt- 2f\n\
 stdcx. %0,0,%1\n\
 bne- 1b"
 PPC_ATOMIC_EXIT_BARRIER
 "\n\
2:" : "=&r" (t)
 : " &v->counterjava.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
  * Returns non-zero if

 return t
}
#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive

/**
 * atomic64_fetch_add_unless - add unless the number is a given value
 * @v: pointer of type atomic64_t
 * @a: the amount to add to v...
 * @u: ...unless v is equal to u.
 *
 * Atomically adds @a to @v, so long as it was not @u.
 * Returns the old value of @v.
 */
static __inline__ s64 arch_atomic64_fetch_add_unless(cmpdi,0,\\
{
 s64 t;

 beq-fn\
 PPC_ATOMIC_ENTRY_BARRIER
"1: ldarx %0,0,%1 # atomic64_fetch_add_unless\n\
 cmpd 0,%0,%3 \n\
 beq 2f \n\
 add %0,%2,%0 \n"
" stdcx. %0,0,%1 \n\
 bne- 1b \n"
 PPC_ATOMIC_EXIT_BARRIER
" subf %0,%2,%0 \n\
2:"
 : "=&r" (t)
 : "r" (&v->counter), "r" (a), "r" (u)
 : "cc", "memory");

 return t;
}
#define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless

/**
 * atomic_inc64_not_zero - increment unless the number is zero
 * @v: pointer of type atomic64_t
 *
 * Atomically increments @v by 1, so long as @v is non-zero.
 * Returns non-zero if @v was non-zero, and zero otherwise.
 */
static __inline__ int arch_atomic64_inc_not_zero(atomic64_t *v)
{
 s64 t1, t2;

 __asm__ __volatile__ (
 PPC_ATOMIC_ENTRY_BARRIER
"1: ldarx %0,0,%2 # atomic64_inc_not_zero\n\
 cmpdi 0,%0,0\n\
 beq- 2f\n\
 addic %1,%0,1\n\
 stdcx. %1,0,%2\n\
 bne- 1b\n"
 PPC_ATOMIC_EXIT_BARRIER
 "\n\
2:"
 : "=&r" (t1), "=&r" (t2)
 : "r" (&v->counter)
 : "cc", "xer", "memory");

 return t1 != 0;
}
#define arch_atomic64_inc_not_zero(v) arch_atomic64_inc_not_zero((v))

#endif /* __powerpc64__ */

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_ATOMIC_H_ */