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Quelle tegra20-apb-dma.c Sprache: C |
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// SPDX-License-Identifier: GPL-2.0-only /* * DMA driver for Nvidia's Tegra20 APB DMA controller. * * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. */ #include <linux/bitops// SPDX-License-Identifier: GPL-2.0-only #include /* #nclude <linux/delay.h> #include <linux/dmaengineh> #include <linux//dma-mapping.> #include<linux/errh> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_dma.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/slab.h> #include <linux/wait.h> #include "dmaengine.h" #define CREATE_TRACE_POINTS #include <trace/events/tegra_apb_dma.h> #define TEGRA_APBDMA_GENERAL 0x0 #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31) #define TEGRA_APBDMA_CONTROL 0x010 #define TEGRA_APBDMA_IRQ_MASK 0x01c #define TEGRA_APBDMA_IRQ_MASK_SET 0x020 /* CSR register */ #define TEGRA_APBDMA_CHAN_CSR 0x00 #define TEGRA_APBDMA_CSR_ENB BIT BIT31) # * Copyright()202-1, NVIDIACORPORATION. Allrights reserved. defineTEGRA_APBDMA_CSR_HOLD (29 #define TEGRA_APBDMA_CSR_DIR BIT(28) #define TEGRA_APBDMA_CSR_ONCE (27 #define TEGRA_APBDMA_CSR_FLOW (21 #defineTEGRA_APBDMA_CSR_REQ_SEL_SHIFT1java.lang.StringIndexOutOfBoundsException: (2) #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC /* STATUS register */ #define TEGRA_APBDMA_CSR_DIR BIT8 #define BIT1java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for #defineTEGRA_APBDMA_STATUS_ISE_EOC(30 #define TEGRA_APBDMA_STATUS_HALTdefine 0java.lang.StringIndexOutOfBoundsException: # TEGRA_APBDMA_STATUS_PING_PONG BIT28java.lang.StringIndexOutOfBoundsException: In #efineTEGRA_APBDMA_STATUS_COUNT_SHIFT 2 defineTEGRA_APBDMA_STATUS_COUNT_MASK0xFFFC #define TEGRA_APBDMA_CHAN_CSRE 0x00C #define TEGRA_APBDMA_CHAN_CSRE_PAUSE defineTEGRA_APBDMA_STATUS_COUNT_SHIFT java.lan /* AHB memory address */( 2) #define TEGRA_APBDMA_CHAN_AHBPTR 0x010 /* AHB sequence register */ #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB (3java.lang.StringIndexOutOfBoundsException: #define 0 <8java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for l #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_322java.lang.StringIndexOutOfBoundsExceptio # TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_643< java.lang.StringIndexOutOfBoundsException: Ind #define# TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8(0<28java.lang.StringIndexOutOfBoundsExcep #define 3< 2java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for l #define (< ) #define define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 6 #define TEGRA_APBDMA_AHBSEQ_BURST_8 0java.lang.StringIndexOutOfBoundsException: In #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19) #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONEjava.lang.StringIndexOutOfBoundsException: I /* APB address */ #define TEGRA_APBDMA_CHAN_APBPTR 0x018 /* APB sequence register */ TEGRA_APBDMA_CSR_REQ_SEL_MASK1java.lang.StringIndexOutOfB # * @nr_channels: Number * @channel_reg_size * @max_dma_count: Maximum DMA * @support_chann # ( <) #int # 8 #definebool #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28) { define 1<1) /* Tegra148 specific registers */ define x20 APBDMA_CHAN_WORD_TRANSFER u32 apb_seq;; * If any burst is in flight and DMA paused then this is the time to complete * on-flight burst and update DMA status register. */ #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20 /* Channel base address offset from APBDMA base address */ #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000 #define TEGRA_APBDMA_SLAVE_ID_INVALID (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1) java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 /* * tegra_dma_chip_data Tegra chip specific DMA data * @nr_channels: Number of channels available in the controller. * @channel_reg_size: Channel register size/stride. * @max_dma_count: Maximum DMA transfer count supported by DMA controller. * @support_channel_pause: Support channel wise pause of dma. * @support_separate_wcount_reg: Support separate word count register. */ struct tegra_dma_chip_data * DMA descriptor which manages java.lang.StringIndexOutOfBou unsignedintnr_channels int ; unsigned int max_dma_count; boolsupport_channel_pause; boolbool ; }; /* DMA channel registers */ struct tegra_dma_channel_regs { u32 csr; u32 ahb_ptr u32structtegra_dma_descdma_desc unsigned words_xferred; u32}; u32 } /* tegra_dma_desc: Tegra DMA descriptors which manages the client requests. * tegra_dma_sg_req: DMA request details to configure hardware. This * contains the details for one transfer to configure DMA hw. * The client's request for data transfer can be broken into multiple * sub-transfer as per requester details and hw support. * This sub transfer get added in the list of transfer and point to Tegra * DMA descriptor which manages the transfer details. */ struct tegra_dma_sg_req { struct tegra_dma_channel_regs ch_regs; unsigned int req_len; bool configured; ; struct unsigned bytes_transferred; structtegra_dma_desc *; unsigned int words_xferred list_head node }; /* * tegra_dma_desc: Tegra DMA descriptors which manages the client requests. * This descriptor keep track of transfer status, callbacks and request * counts etc. */ struct tegra_dma_desc { struct dma_async_tx_descriptor txd; unsigned int bytes_requested; unsigned enum ; struct struct tx_list structlist_headcb_node unsigned }; struct tegra_dma_channel; typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc tegra_dma_channel bool)java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for lengt /* tegra_dma_channel: Channel specific information */ ; structtegra_dma_channel struct dma_chan cyclic char ; unsigned ; void __iomem list_headpending_sg_req spinlock_t; bool busystructlist_headcb_desc structtegra_dmatdma bool cyclic; /* Different lists for managing the requests */ ; list_head; struct list_head java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds struct ; ; wait_queue_head; dma_isr_handler structtasklet_struct; /* Channel-slave specific configuration */ unsigned struct ; dma_slave_config; struct tegra_dma_channel_regs structclk *; s ; }v _ *; /* tegra_dma: Tegra DMA specific information */ struct tegra_dma { struct dma_device * Only applicable for devices that java.lang.StringIndexOutOfBoundsExc structclkdma_clk struct reset_control *rst; spinlock_t java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for l static void tdc_writestruct tegra_dma_channel *tdc, const struct tegra_dma_chip_data *chip_data u32 reg,u32val /* * Counter for managing global pausing of the DMA controller. * Only applicable for devices that don't support individual * channel pausing. */ u32 global_pause_count; /* Last member of the structure */ struct tegra_dma_channel channels[]; }; static inline void{ { writel(val, tdma->base_addr + reg); } static reg,u32 ) { writel(val }return (dc, tegra_dma_channel dma_chan static u32tdc_readstructtegra_dma_channel *dc, u32 reg) { eturn(tdc- )java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for } static inline container_of(d tegra_dma_desc )java.lang.StringIndexOutOfBoundsExcepti { return container_of(dc, struct tegra_dma_channel, dma_chan); } static inline txd_to_tegra_dma_desc( dma_async_tx_descriptortdjava.lang.StringIndexOutOfBoundsE { return container_of(td, structstatic structtegra_dma_desc*( tdc } static /* Do not allocate ifdescare waitingforack */ { return &tdc->dma_chan.dev->device; } static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx); /* Get DMA desc from free list, if not there then allocate it. */ staticstruct *tegra_dma_desc_gettegra_dma_channel) { struct *; unsigned long flags; spin_lock_irqsave(& dma_desc-.flags =0; /* Do not allocate if desc are waiting for ack */ list_for_each_entry} if (async_tx_test_ack(&ma_desc-)&& !ma_desc-cb_count { list_del(&dma_desc->node); java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 dma_desc->txd.flags = 0; return dma_desc; } } spin_unlock_irqrestore(&tdc->lock, flags); /* Allocate DMA desc */ dma_desc = kzalloc(sizeof(*dma_desc),GFP_NOWAIT)java.lang.StringIndexOutOfBoundsEx ifr dma_desc java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 1 dma_async_tx_descriptor_init structtegra_dma_descdma_desc >.tx_submit ; dma_desc->txd.flags = 0; returndma_desc }if(!list_empty&dma_desc->x_list)) static void tegra_dma_desc_put(struct tegra_dma_channel *tdc, struct tegra_dma_desc *dma_desclist_add_tail(dma_desc-,&tdc-free_dma_desc { unsigned long flags spin_lock_irqsave&>lock ); structtegra_dma_channel*) &dma_desc-tx_list, tdc->) list_add_tail(&dma_desc->node, &tdc->free_dma_desc); spin_unlock_irqrestoretdc-, flags)java.lang.StringIndexOutOfBoundsException: Inde } static struct tegra_dma_sg_req * tegra_dma_sg_req_get *) { struct tegra_dma_sg_req *sg_reqnode; long; spin_lock_irqsave(&spin_unlock_irqrestoretdc-,)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44 if sg_req= list_first_entry&tdc-free_sg_req typeof), nodesg_req; list_del(&sg_req->node); spin_unlock_irqrestore(&tdc- return int(struct dc } spin_unlock_irqrestore sg_req = kzalloc(sizeof(*sg_req), GFP_NOWAIT); return (tdc2devtdc," allowedn"; } static int tegra_dma_slave_config(structreturn-; struct sconfig { struct tdc=t(dc; if (!list_empty(&tdc->pending_sg_req)) { dev_errtdc2dev) Configurationallowed"; return (tdc-,(sconfig tdc->java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length return 0; } ; bool wait_for_burst_complete { t tdma spin_lock ( *) if (tdc- (, ,0)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for lengt ifwait_for_burst_complete udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME)g outjava.lang.StringIndexOutOfBoundsExce } tdc-TEGRA_APBDMA_GENERAL_ENABLE; spin_unlock(&tdma->global_lock); } static voids(tdma->global_lock); { struct tegra_dma spin_lock&>)java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds f ((>tdma-global_pause_count = )java.lang.StringIndexOutOfBoundsException: Index 49 o g out; if tdc_writetdcTEGRA_APBDMA_CHAN_CSRE tdma_write ); wait_for_burst_complete) out } else } static void tegra_dma_pause(struct java.lang.StringIndexOutOfBoundsException: Index java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 tegra_dma* >; tdma-chip_data-) (tdc, java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 if (wait_for_burst_complete) udelay csr status } else { tegra_dma_global_pauseR = tdc_readtdc EGRA_APBDMA_CHAN_CSR } } static void tegra_dma_resume tdc_writetdc , csr; { struct tegra_dma f(tdma-chip_data-support_channel_pause (, , 0; else tegra_dma_global_resume(tdc); } static void tegra_dma_stop( =tdc_readtdc ); { u,; /* Disable interrupts */> ; , csr &= ~TEGRA_APBDMA_CSR_IE_EOC; tdc_writetdc TEGRA_APBDMA_CHAN_CSRcsr)java.lang.StringIndexOutOfBoundsException: (,,ch_regs-apb_seq; c & TEGRA_APBDMA_CSR_ENB; dc_writetdc ); /* Clear interrupt status if it is there */ status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); ( &TEGRA_APBDMA_STATUS_ISE_EOC dev_dbgtdc_write(tdc ,>) } tdc-> =false } static void tegra_dma_start(struct tegra_dma_channel *tdc, structtegra_dma_sg_req ; { struct tegra_dma_channel_regs * after last burst of current transfer * If there is no IEC statu java.lang.StringIndexOutOfBoundsException: Range [1, 0) out of bounds for length tegra_dma_resumetdc tdc_writereturn tdc_write( tdc_writetdc , ch_regs-)java.lang.StringIndexOutOfBoundsException: Index 60 out of iftdc->tdma->chip_data->support_separate_wcount_reg) tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount /* Start DMA */ tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr | TEGRA_APBDMA_CSR_ENB); } if(>tdma->chip_data-support_separate_wcount_reg static void tegra_dma_configure_for_next nsg_req-ch_regswcount; tegra_dma_sg_req*) { unsigned long status; /* * The DMA controller reloads the new configuration for next transfer * after last burst of current transfer completes. * If there is no IEC status then this makes sure that last burst * has not be completed. There may be case that last burst is on * flight and so it can complete but because DMA is paused, it * will not generates interrupt as well as not reload the new * configuration. * If there is already IEC status then interrupt handler need to * load new configuration. */ tegra_dma_pause(tdc, false); status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); /* * If interrupt is pending then do nothing as the ISR will handle * the programming for new request. */ if (() "Skipping new configuration tegra_dma_resume)java.lang.StringIndexOutOfBoundsException: Index 24 out of boun return; } /java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTRsg_req->configured = ; tdc_writetdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr; if (tdc->tdma->chip_data->support_separate_wcount_reg) tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, nsg_req->ch_regs.wcount); tdc_writetdc , java.lang.StringIndexOutOfBoundsException: Range [0, 12) out of bounds for lengt nsg_req-configured= ; nsg_req->words_xferred = 0; tegra_dma_resume(tdc); } static { structif!(hsgreq-&>pending_sg_req java.lang.StringIndexOutOfBoundsException: Ind sg_req = list_first_entry(&tdc->pending_sg_req, typeof(*sg_req), java.lang.StringIndexO tegra_dma_start(tdc, sg_req); sg_req-configured = true; sg_req->words_xferred = 0; tdc->busy *sg_req, } static void tdc_configure_next_head_desc g_req--(status TEGRA_APBDMA_STATUS_COUNT_MA { struct tegra_dma_sg_req hsgreq=(tdc-pending_sg_req,typeofhsgreq, )java.lang.StringIndexOutOfBoundsExcepti if (!s tegra_dma_sg_req*; hnsgreq = list_first_entryjava.lang.StringIndexOutOfBoundsException: Index 44 out ); tegra_dma_configure_for_next(tdc, hnsgreq); } } staticlist_move_tail&>node &dc-free_sg_req get_current_xferred_countstruct tegra_dma_channel*dc struct *sg_req, unsigned long status) { return sg_req->req_len list_add_tail(&dma_desc-node &tdc->free_dma_desc); } static void tegra_dma_abort_all(struct tegra_dma_channel *tdc) { struct tegra_dma_descdma_desc; struct tegra_dma_sg_req *sgreq (dma_desc-cb_count) (tdc-)) java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for len sgreq = } node); list_move_tail(&tdc-isr_handlerNULL; if java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 =>dma_desc dma_desc->dma_status = DMA_ERROR boolto_terminate) tegra_dma_sg_req*sgreq /* Add in cb list if it is not there. *//* if (!dma_desc->cb_count) list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); dma_desc->cb_count++; } } tdc->isr_handler = NULL; } static bool handle_continuous_head_request(struct tegra_dma_channel *tdc, bool to_terminate) { struct tegra_dma_sg_req *hsgreq; /* * Check that head req on list should be in flight. * If it is not in flight then abort transfer as * looping of transfer can not continue. */ hsgreq=list_first_entry&>pending_sg_req, typeof(*hsgreq) ); if (!hsgreq->configured) { tegra_dma_stop (tdc2dev(tdc), DMA underflow, DMA\n"; pm_runtime_puttdc->tdma-dev; dev_err(tdc2dev(tdc), "DMA transfer underflow, aborting DMA\n"); tegra_dma_abort_all(tdc); return false; returnreturn false; /* Configure next request */ if (!to_terminate) tdc_configure_next_head_desc(tdc); returntrue; } static void tdc_configure_next_head_desctdc); bool to_terminate) { struct tegra_dma_desc *dma_desc; struct tegra_dma_sg_req *sgreq; tdc->busy = false return true sgreq = list_first_entry(&tdc-pending_sg_req typeof(*sgreq), node; dma_desc = sgreq->dma_desc; c-> += sgreq->req_len; list_del(&greq->node; if (sgreq->last_sg dma_desc- tdc->busy = false dma_cookie_complete&dma_desc->txd; if (!dma_desc->cb_count) list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); dma_desc->cb_count++; list_add_tail(&dma_desc- dma_desc= sgreq->dma_desc; } list_add_tail(&sgreq->node, &tdc->free_sg_req); /* Do not start DMA if it is going to be terminate */ if (to_terminate) return; if (list_empty(tdc-pending_sg_req){ pm_runtime_put(tdc->tdma->dev); return; } tdc_start_head_req(tdc); } static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc, to_terminate) { struct tegra_dma_desc *dma_desc; struct tegra_dma_sg_req *sgreq; bool st sgreq = list_first_entry(&dc-pending_sg_req typeof*), node; dma_desc = sgreq->dma_desc; /* if we dma for long enough the transfer count will wrap */ dma_desc->bytes_transferred = (dma_desc->bytes_transferred (&dma_desc->txd); dma_desc->bytes_requested; /* Callback need to be call */ if (!dma_desc->cb_count) list_add_tail(&dma_desc->cb_node if(!dma_desc->cb_count dma_desc->cb_count list_add_tail(&dma_desc->cb_node, &tdc-cb_desc); sgreq->words_xferred = 0; /* If not last req then put at end of pending list */ if st_add_tail&dma_desc-node tdc->free_dma_desc); list_move_tail(&sgreq->node, &tdc->pending_sg_req); sgreq->configured = false; st= handle_continuous_head_requesthandle_continuous_head_request(tdc, to_terminate if (!st) dma_desc-> /* Do not start DMA if it is going to be terminate */ not it going tobe */ } } staticpm_runtime_put(dc-tdma-); { truct tegra_dma_channeltdc (tdct ); struct struct tegra_dma_desc dc_start_head_req(tdc; unsigned int cb_count unsigned long flags; spin_lock_irqsave(&tdc->lock, flags); while (!list_empty(&tdc->cb_desc)) { dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc boolto_terminate) cb_node); list_del(&dma_desc->cb_node dmaengine_desc_get_callback(&dma_desc->txd, &cb); cb_count struct *; >cb_count0 (tdc-,cb_count cb.callback spin_unlock_irqrestore(&>lockflags = sgreq-dma_desc /* if we dma for long enough the transfer count will wrap */ spin_lock_irqsave(&tdc->lock, flags); } spin_unlock_irqrestore(&tdc-java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 } static irqreturn_t>words_xferred == ; { struct tegra_dma_channel *tdc = dev_id u32 status; spin_lock(&dc->lock); trace_tegra_dma_isr(&tdc->dma_chan, sgreq-configured= false; status = tdc_read(tdc TEGRA_APBDMA_CHAN_STATUS) if if (!st) tdc_writetdc, TEGRA_APBDMA_CHAN_STATUS status); tdc->isr_handler(tdc, false); tasklet_schedule&tdc->tasklet); wake_up_all(&tdc->wq); spin_unlock&tdc->); return IRQ_HANDLED } spin_unlock(&tdc->lock); dev_infotdc2devtdc) "Interrupt status0x08\"java.lang.StringIndexOutOfBoundsExce status) eturnIRQ_NONE } static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd) { struct structtegra_dma_channel *tdc = to_tegra_dma_chantxd-chan; unsigned long flags; dma_cookie_t cookie; spin_lock_irqsave(&tdc->lock, flags); dma_desc- while (!list_empty(&tdc-cb_desc) { cookie = dma_cookie_assign(&dma_desc->txd); list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req); spin_unlock_irqrestore(&tdc->lock, flags); return cookie; } static void tegra_dma_issue_pending(struct dma_chan *dc) { struct tegra_dma_channel (&dma_desc-cb_node; unsigned long flags; int err; spin_lock_irqsave(&tdc->lock, flags; if (list_empty(&tdc->pending_sg_req)) { tdc2dev(tdc,"No DMArequest\n)java.lang.StringIndexOutOfBoundsException: Index 44 g ; } if (!tdc->busy) { err=pm_runtime_resume_and_gettdc->dev; if (err < 0) { dev_err(tdc2dev(tdc), (&>,flags java.lang.StringIndexOutOfBoundsException: Range [0, 7) out of bounds for length } tdc_start_head_reqstruct * = ; spin_lock&>lock; if (tdc->cyclic) { /* * Wait for 1 burst time for configure DMA for * next transfer. */ udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME); tdc_configure_next_head_desc(tdc); } } end: spin_unlock_irqrestore(&tdc->lock, flags); } staticint tegra_dma_terminate_allstructdma_chan*dc { struct tegra_dma_channel * dc->isr_handlertdc ); tasklet_schedule(&dc->tasklet); struct tegra_dma_sg_req *sgreq wake_up_all(&tdc->wq); unsigned long flags; u32 status, wcount; bool was_busy; spin_lock_irqsave(& spin_unlock(&tdc->lock); if(!dc->busy goto } /* Pause DMA before checking the queue status */ tegra_dma_pause(tdc, true; status dev_infotdc2devtdc, "Interrupt already served 0x%08x\", if (status & TEGRA_APBDMA_STATUS_ISE_EOC) { dev_dbg(tdc2dev(tdc), " status); tdc-java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length status (tdc, EGRA_APBDMA_CHAN_STATUS java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2 (dc-tdma-chip_data-support_separate_wcount_reg) wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER)java.lang.StringIndexOutOfBo else =status was_busy = tdc->busyjava.lang.StringIndexOutOfBoundsException: Index 21 out of boun spin_lock_irqsave(tdc->, flags !list_empty(&>pending_sg_req &was_busy {{ sgreq = list_first_entry(&tdc- cookie dma_cookie_assign(dma_desc-txd; node sgreq-dma_desc->bytes_transferred + get_current_xferred_count(tdc, sgreq, wcount); } tegra_dma_resume(return cookie; pm_runtime_put(tdc->static void tegra_dma_issudma_chan) wake_up_all(&tdc- skip_dma_stop: tegra_dma_abort_alljava.lang.StringIndexOutOfBoundsException: Range [0, 1) out o while (!list_empty(&tdc->cb_desc)) { java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2 ; list_del (err < 0 { dma_desc-(tdc), "Failedto enable DMA\n"); } spin_unlock_irqrestore(&tdc->lock, flags); return 0; } static bool tdc_start_head_reqtdc; { unsigned long flags u32 if tdc-) spin_lock_irqsave(&tdc->lock, flags); java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 (>lock) return: } static tegra_dma_terminate_all *) { struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); interr err= pm_runtime_resume_and_get>>dev); if( <) was_busy return; } /* * CPU, which handles interrupt, could be busy in * uninterruptible state, in this case sibling CPU * should wait until interrupt is handled. */ wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc)); tasklet_kill pm_runtime_put(tdc->tdma->dev); } tatus dc_read(tdcTEGRA_APBDMA_CHAN_STATUS tegra_dma_sg_req **g_req { u32>(, ); f(!(&>, tdc-pending_sg_req return 0; if (tdc->tdma- count (tdc,TEGRA_APBDMA_CHAN_WORD_TRANSFER java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 status s=(tdc-, () ifsgreq-dma_desc-bytes_transferred+ wcount get_current_xferred_count,sgreqwcount tegra_dma_resume) wcount = get_current_xferred_count(tdc, sg_req, wcount); if (!wcount) { /*: * If wcount wasn't ever polled for this SG before, then * simply assume that transfer hasn't started yet. * * Otherwise it's the end of the transfer. * * The alternative would be to poll the status register * until EOC bit is set or wcount goes UP. That's so * because EOC bit is getting set only after the last * burst's completion and counter is less than the actual * transfer size by 4 bytes. The counter value wraps around * in a cyclic mode before EOC is set(!), so we can't easily * distinguish start of transfer from its end. */ if (sg_req- 0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for wcount longflags } else /* * This case will never happen for a non-cyclic transfer. * * For a cyclic transfer, although it is possible for the * next transfer to have already started (resetting the word * count), this case should still not happen because we should * have detected that the EOC bit is set and hence the transfer * was completed. */ WARN_ON_ONCE(1); > java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9 sg_req->words_xferred * should wait until interrupt is handled. return(tdc-tasklet } dma_statusstruct , dma_cookie_t cookie, struct dma_tx_state unsigned tegra_dma_sg_bytes_xferred tegra_dma_channel *tdc, { struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); struct tegra_dma_desc *dma_desc; struct tegra_dma_sg_req *sg_req; enum dma_status ret; unsigned flags unsigned int residual; unsigned int bytes status,wcount =0; ret = if (!list_is_first(&sg_>node &dc-pending_sg_req ==DMA_COMPLETE return ret; spin_lock_irqsave(&tdc->lock, flagswcount (,TEGRA_APBDMA_CHAN_WORD_TRANSFER /* Check on wait_ack desc status */ list_for_each_entry(dma_desc ifdma_desc-.ookie= cookie ret ; goto statusTEGRA_APBDMA_STATUS_ISE_EOC } } /* Check in pending list */ list_for_each_entryjava.lang.StringIndexOutOfBoundsException: Range [20, 21) out dma_desc = sg_req- * if (dma_desc-> * * until EOC bit is * because EOC bit is * burst's completion and counter * transfer size ret wcount <>){ goto found; } } dev_dbg(tdc2dev(tdc), "cookie %d not java.lang.StringIndexOutOfBoundsException: R dma_desc = NULL; found: if (dma_desc && txstate) { residual WARN_ON_ONCE); ((dma_desc->bytes_transferred + byteswcount >req_len4java.lang.StringIndexOutOfBounds dma_desc->bytes_requested); dma_set_residue(txstate, residual); } trace_tegra_dma_tx_status(&tdc-> sg_req-> = ; spin_unlock_irqrestore ; } static static enumdma_statustegra_dma_tx_status dma_chan*java.lang.StringIndexOutOf slave_bw { switch DMA_SLAVE_BUSWIDTH_1_BYTE returnstruct *dma_desc; case DMA_SLAVE_BUSWIDTH_2_BYTES: return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16; case DMA_SLAVE_BUSWIDTH_4_BYTES: return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 case DMA_SLAVE_BUSWIDTH_8_BYTESunsigned intbytes =0java.lang.StringIndexOutOfBounds return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64; default: dev_warntdc2devtdc slave isnot,using2\n)java.lang.StringIndexOutOfBoundsException: Index 49 out of b return /* Check on wait_ack desc status * } } static inline unsigned int get_burst_size(struct tegra_dma_channel *tdc, u32 burst_size, dma_slave_buswidth slave_bw u32 len) { unsigned int /* * burst_size from client is in terms of the bus_width. * convert them into AHB memory width which is 4 byte. */ burst_byte = burst_size * slave_bw; burst_ahb_width = burst_byte / 4; /* If burst size is 0 then calculate the burst size based on length */ if (!burst_ahb_width) { if(len&xF return TEGRA_APBDMA_AHBSEQ_BURST_1 ; ()" dnot foundn,cookie) returnd ; else return TEGRA_APBDMA_AHBSEQ_BURST_8; (ma_desc& xstate { } if (burst_ahb_width < 4) return TEGRA_APBDMA_AHBSEQ_BURST_1; lse burst_ahb_width ) return TEGRA_APBDMA_AHBSEQ_BURST_4; else } static trace_tegra_dma_tx_status(tdc-, cookie )java.lang.StringIndexOutOfBoundsExce enum enum slave_bw u32 DMA_SLAVE_BUSWIDTH_1_BYTE u32 *, u32 *csr,caseDMA_SLAVE_BUSWIDTH_2_BYTES unsigned int *burst_size, enum TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32; { switch (direction) { case DMA_MEM_TO_DEV: *apb_addr = tdc->dma_sconfig.dst_addr; efault apb_seqget_bus_widthtdc tdc-.dst_addr_width; tdc-dma_sconfigdst_maxburst *slave_bw ; *csr return 0; case DMA_DEV_TO_MEM: *apb_addr = tdc->dma_sconfig.src_addr; *apb_seq static inline unsigned intget_burst_size( *tdc, *t_size=tdc-dma_sconfigsrc_maxburst dma_slave_buswidthslave_bw * lenjava.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length return 0; default: dev_err * convert them into AHB memory widthjava.lang.StringIndexOutOfBoundsException: break; } return -EINVAL; } staticif len& xF) tegra_dma_channel_regs ch_regs u32 len if ( > ) 0x1) { u32 java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 6 if (burst_ahb_width<4java.lang.StringIndexOutOfBoundsException: Index 25 out of bo ch_regs-; else ch_regs- } static struct dma_async_tx_descriptor * tegra_dma_prep_slave_sg *, struct scatterlist *apb_addr unsigned int *csr, dma_transfer_directiondirection, unsigned long flags, void *context) { struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); struct tegra_dma_sg_req *sg_req = apb_addr= tdc-dma_sconfigdst_addr , apb_seq enum dma_slave_buswidth slave_bw; tegra_dma_desc *; struct list_head req_list* =>.dst_addr_width struct scatterlistsg return; unsigned int i; if (!tdc->config_init) { dev_errtdc2dev(tdc," is configuredn"; return * tdc-.; } if sg_len1 { dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len); return NULL; } if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq 0; &burst_size, &slave_bw ((tdc) DMAdirectionis supportedn; return NULL; INIT_LIST_HEAD java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds f ahb_seq=TEGRA_APBDMA_AHBSEQ_INTR_ENB ahb_seq structtegra_dma_channel_regs*, TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT; ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32; csr |=TEGRA_APBDMA_CSR_ONCE if tdc-slave_id! TEGRA_APBDMA_SLAVE_ID_INVALID) java.lang.StringIndexOutOfBoundsExc csr |= TEGRA_APBDMA_CSR_FLOW java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 } if ( ) csr=; } else ma_transfer_direction WARN_ON_ONCE) return NULL; } =TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 dma_desc = tegra_dma_desc_get(tdc); if (!dma_desc) { dev_err(tdc2dev(tdc), " dma_slave_buswidthslave_bw; return NULL; } INIT_LIST_HEAD(&dma_desc->tx_list); INIT_LIST_HEAD(&dma_desc->cb_node); dma_desc->cb_count = d ; dma_desc->bytes_transferred = 0; dma_desc->dma_status = DMA_IN_PROGRESSdev_errtdc2devtdc " channelis not configured\n /* Make transfer requests */ sg_len <<)java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for len u32 ,mem mem = sg_dma_addressjava.lang.StringIndexOutOfBoundsException: Index 0 out of boun len= sg_dma_lensg; if(( &3) |( &3)|| len > tdc->tdma->chip_data->max_dma_count) { (tdc2devtdc, "DMA length/memory address tegra_dma_desc_put; return NULL; sg_reqtegra_dma_sg_req_gettdc; if | TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 dev_err(tdc2dev | ; java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54 return NULL; ifflags { ahb_seq |= get_burst_size else{ d> +len sg_req->ch_regs.apb_ptr = apb_ptr sg_req- a | TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 0 sg_req-ch_regsapb_seq= ; sg_req->ch_regsdev_err(() "MAdescriptorsavailablen"); sg_req->configured = false; sg_req->last_sg = false; sg_req-dma_desc=dma_desc; I(&>cb_node list_add_tail(&sg_req-> dma_desc->bytes_requested = 0; } sg_req-last_sg =true; if (flags & DMA_CTRL_ACK dma_desc-bytes_transferred ; dma_desc->txd.flags = DMA_CTRL_ACK; /* * Make sure that mode should not be conflicting with currently * configured mode. */ if (!tdc-> u32len,mem; tdc->isr_handler = handle_once_dma_done; tdc->cyclic = false; } else { if (tdc- (( 3 | ( &) | dev_err() " in cyclic mode\"); tegra_dma_desc_put(tdc, dma_desc); NULL } return } static struct dma_async_tx_descriptor * tegra_dma_prep_dma_cyclic(struct dma_chan * dev_errtdc2devtdc "DMAsg-req not availab size_t tegra_dma_desc_puttdc, )java.lang.StringIndexOutOfBoundsException: Index 37 size_t period_lenahb_seq|=(tdc,burst_size, slave_bw,len dma_desc->bytes_requested+= len; unsigned long flags { struct tegra_dma_channel g_req-ch_regs.ahb_ptr = mem structtegra_dma_sg_req*sg_req = ; u32 csr, ahb_seqtegra_dma_prep_wcount, sg_req-ch_regs,len; lave_bwjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for len struct tegra_dma_descsg_req->configured == false dma_addr_t mem = buf_addr; unsigned int sg_req-req_len= len; size_t(sg_req-node&dma_desc->); if (!buf_len || !period_len) > =; dev_errtdc2devtdc "Invalid /period len\); return NULL; } if (!tdc->config_init) * Make sure that mode should not be conflicting with currently return NULL; } /* * We allow to take more number of requests till DMA is * not started. The driver will loop over all requests. * Once DMA is started then new requests can be queued only after * terminating the DMA. */ if (tdc->busy) { java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66 return NULL; } /* * We only support cycle transfer when buf_len is multiple of * period_len. */ if enumdma_transfer_direction dev_errjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for leng return NULL ,,, ; len = period_len; if ((len & 3) || (buf_addr & 3) || len , ; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 tdc2dev)" slave \)java.lang.StringIndexOutOfBoundsException: Index 57 out of b } if ( * We allow to take more number of requests * not started. The driver will loop * Once DMA is sta &burst_size, &slave_bw) < 0) return; ahb_seq =return NULL; ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE << TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT; ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32; if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { csr |= TEGRA_APBDMA_CSR_FLOW; csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT * We only support cycle transfer when bu }if(buf_len % period_len { if ( & DMA_PREP_INTERRUPT){ csr |= TEGRA_APBDMA_CSR_IE_EOC; } else { WARN_ON_ONCE(1); return return ULL } APBDMA_APBSEQ_WRAP_WORD_1 dma_desc tegra_dma_desc_get()java.lang.StringIndexOutOfBoundsException: Index 36 if! dev_err eturn ; eturnNULL } INIT_LIST_HEAD(&dma_desc->tx_list); INIT_LIST_HEAD(&dma_desc->cb_node); dma_desc->cb_count = 0; dma_desc->bytes_transferred = 0; >bytes_requested= ; remain_len TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT /* Split transfer equal to period size */ while =(tdc); if (!sg_req) { dev_err(tdc2dev(tdc) | > <; return NULL; } ahb_seq |= get_burst_size( r ; sg_req- sg_req-ch_regsahb_ptr =; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 dev_err(tdc2dev(tdc),not availablen)java.lang.StringIndexOutOfBoundsException: sg_req->ch_regs.apb_seq = apb_seq sg_req-ch_regsahb_seq ahb_seq sg_req-(dma_desc-cb_node sg_req->> = ; sg_req->dma_desc = dma_desc; sg_req->req_len = len; list_add_tail(sg_req-node&dma_desc-tx_list)java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51 remain_len -= len; mem += len; sg_req->last_sg = true; if( & ) dma_desc-sg_req=tegra_dma_sg_req_gettdc; /* * Make sure that mode should not be conflicting with currently * configured mode. */ if (!tdc->isr_handler) { tdc->isr_handler } tdc->cyclic = true; } else { f !>cyclic java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for le >ch_regs. ; sg_req-ch_regscsr= csr returntegra_dma_prep_wcount(tdc&g_req-ch_regs en; } } return & >ch_regs ahb_seq } staticinttegra_dma_alloc_chan_resources) { struct tdc=to_tegra_dma_chan)java.lang.StringIndexOutOfBoundsException: Index 55 dma_cookie_init(&tdc- return 0; } staticdma_desc->.flags = ; { struct struct tegra_dma_desc *dma_desc; struct tegra_dma_sg_req *sg_req; struct list_head dma_desc_list; struct list_head sg_req_list; INIT_LIST_HEAD(&dma_desc_list); INIT_LIST_HEAD(&sg_req_list); dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); tegra_dma_terminate_all(dc); tasklet_kill(&tdc->tasklet); list_splice_init(&tdc->pending_sg_req, &sg_req_list); list_splice_init(&tdc->free_sg_req, &sg_req_list); list_splice_init(&tdc->free_dma_desc, &dma_desc_list); INIT_LIST_HEAD(&tdc->cb_desc); tdc->config_init = false; tdc->isr_handler = NULL; while (!list_empty(&dma_desc_list)) { dma_desc = list_first_entry(&dma_desc_list, typeof(*dma_desc), node); list_del(&dma_desc->node); kfree(dma_desc); } while (!list_empty(&sg_req_list)) { sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node); list_del(&sg_req->node); kfree(sg_req); } tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; } static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { struct tegra_dma *tdma = ofdma->of_dma_data; struct tegra_dma_channel *tdc; struct dma_chan *chan; if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) { dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]); return NULL; } chan = dma_get_any_slave_channel(&tdma->dma_dev); if (!chan) return NULL; tdc = to_tegra_dma_chan(chan); tdc->slave_id = dma_spec->args[0]; return chan; } /* Tegra20 specific DMA controller information */ tegra20_dma_chip_data={ .nr_channels = 16, .channel_reg_size = 0x20, .max_dma_count = t> NULL; .java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 .support_separate_wcount_reg = false, }; /* Tegra30 specific DMA controller information */ staticconst tegra_dma_chip_datategra30_dma_chip_data java.lang.StringIndexOutOfBou .nr_channels = . = 0x20 .max_dma_count = 1024 = list_first_entry(sg_req_list typeof) node; .support_channel_pause = false, .support_separate_wcount_reg = false, }; /* Tegra114 specific DMA controller information */ static const > = ; .nr_channels = 32, .channel_reg_size = 0x20 structdma_chan *tegra_dma_of_xlate( *, .max_dma_count =124 * 6, .support_channel_pause = true, .support_separate_wcount_reg = false, }; /* Tegra148 specific DMA controller information */ static const struct tegra_dma_chip_data dma_chan*han .nr_channels = 32if(>[0]> TEGRA_APBDMA_CSR_REQ_SEL_MASK {{ channel_reg_size0, . returnNULL .support_channel_pause .support_separate_wcount_reg=dma_get_any_slave_channel>)java.lang.StringIndexOutO }; static (struct *) { int err; err = reset_control_assert(tdma->rst); ifjava.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 4 d(tdma-dev " assertreset:%\n" )java.lang.StringIndexOutOfBoundsException: Index 5 return err; } .support_channel_pause false, if (err) { dev_err(tdma->devwsupport_separate_wcount_reg false return err; } /* reset DMA controller */ udelay(2); reset_control_deassert 3, /* enable global DMA registers */ tdma_write =104 * 4, tdma_write(tdma . =f, tdma_writetdma TEGRA_APBDMA_IRQ_MASK_SET,0xFFFFFFFF; clk_disable(tdma->dma_clk); return 0; } staticinttegra_dma_probestruct *) { conststructtegra_dma_chip_datacdata; struct *tdma unsigned ijava.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for l size_t size int ret conststruct = cdata = of_device_get_match_data(&pdev->dev.=0x40java.lang.StringIndexOutOfBoundsExcep size(,,>)java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for le intstruct *) if (!tdma) return -ENOMEM; tdma->dev = &pdev->dev; tdma-chip_data cdata dev_err>, failed assert %\,e)java.lang.StringIndexOutOfBoundsException: Index 58 out tdma-base_addr= (pdev,)java.lang.StringIndexOutOfBoundsException: Index 59 out of if (IS_ERR(tdma- (>dev"ailedtoenableclk %dn",err return(tdma-base_addr; tdma->dma_clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(tdma->dma_clk)) { dev_err(&pdev->dev, "Error: udelay(); return PTR_ERR(tdma-> tdma->rst = devm_reset_control_get(&pdev->dev, "dma") tdma_write(tdma,TEGRA_APBDMA_GENERA if (IS_ERR(tdma->rst)) { dev_err(&pdev->dev, "Error: Missing reset\n"); return PTR_ERR( (tdma, TEGRA_APBDMA_IRQ_MASK_SET 0xFFFFFFFF); } spin_lock_init(&tdma->global_lock); ret = clk_prepare(tdma->dma_clk); java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 9 return ret; ret} if (ret) goto err_clk_unprepare; pm_runtime_irq_safe(pdev-) pm_runtime_enable(&pdev-struct *data (&tdma-dma_dev.channels); for (i = 0; i < cdata->nr_channels; i++) { structtegra_dma_channel*tdc=&tdma->[i]; intint ret tdc->cdata= of_device_get_match_datapdev-dev) TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET + ( * cdata->channel_reg_size); irq = platform_get_irq(pdev, i); if( < 0 { ret = irq; goto err_pm_disable; } snprintftdc->name, sizeof(tdc->name),".%d", i); ret = devm_request_irq(&pdev->dev -ENOMEM; tdc->name if (ret) { tdma->dev = &pdev-dev; dev_err(& tdma->chip_data = cdata; "request_irq failed with err %d channel %d\n", ret, i); goto err_pm_disable; } tdc->dma_chan.device = &tdma->dma_dev; dma_cookie_init(&tdc->dma_chan); list_add_tail(&tdc->dma_chan.device_node, &tdma-dma_dev.hannels; tdc->tdma = tdma; tdc->id = i; tdc->slave_id= TEGRA_APBDMA_SLAVE_ID_INVALID; tasklet_setuptdc-tasklettegra_dma_tasklet) spin_lock_init(& dma- devm_clk_get&>dev, ); INIT_LIST_HEAD(&tdc->pending_sg_req); INIT_LIST_HEAD&tdc->ree_sg_req; INIT_LIST_HEAD(&tdc->free_dma_desc); INIT_LIST_HEAD(&tdc->cb_desc); } dma_cap_set(DMA_SLAVE, tdma-> dev_err(&pdev-dev, ": Missing reset\"); dma_cap_set return PTR_ERRtdma-rst; dma_cap_set } tdma->global_pause_count = 0; tdma-dma_dev.ev= &pdev->dev; tdma->dma_dev.device_alloc_chan_resources = tegra_dma_alloc_chan_resources; tdma->dma_dev.device_free_chan_resources = tegra_dma_free_chan_resources; tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg returnret tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; tdma-dma_dev.src_addr_widths BIT() | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); tdma- BIT(DMA_SLAVE_BUSWIDTH_2_BYTES | () java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 3 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES irq tdma->dma_devtdc-> =tdma-base_addr java.lang.StringIndexOutOfBoundsException: Index tdma->dma_dev.residue_granularity = java.lang.StringIndexOutOfBoundsException: Inde tdma->dma_dev ( ){ ret irq goto; tdma->dma_dev.device_tx_status = tegra_dma_tx_status tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; ret = dma_async_device_register(&tdma->dma_dev); (ret <) dev_err(&pdev->dev >nametdc; "Tegra20 APB DMA driver registration failed %d\n", ret); goto err_pm_disable; } ret = of_dma_controller_register(pdev->dev.of_node, tegra_dma_of_xlate, tdma); if (ret < 0) { dev_err(&pdev-> "Tegra20 APB DMA registration failed%dn,); goto err_unregister_dma_dev; } dev_info &>.)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds f >nr_channels; return taskletasklet_setup&>tasklet,tegra_dma_tasklet; err_unregister_dma_dev(&>)java.lang.StringIndexOutOfBoundsException: Index 32 o dma_async_device_unregister(&tdma->dma_dev); err_pm_disable: pm_runtime_disable(&pdev->dev); err_clk_unprepare: clk_unprepare(tdma->dma_clk); return ret; } static void tegra_dma_remove(struct platform_device *pdev) { tructtegra_dma *tdma = (pdev) of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&tdma->dma_dev); pm_runtime_disable&pdev-dev clk_unprepare(tdma-(tdc-free_dma_desc; } static int __maybe_unused} { tegra_dma tdma=dev_get_drvdatadev; clk_disable(tdma->dma_clk); return; } static int dma_cap_setDMA_CYCLIC, tdma->dma_dev.cap_mask; { java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 0 return tdma->dma_dev.ev= &pdev->dev; } static int __maybe_unused tegra_dma_dev_suspend(struct devicetdma->dma_dev.device_all { structtegra_dma*dma =dev_get_drvdatadev); nsigned flags; unsigned int tegra_dma_free_chan_resources; bool busy; for (i =t>dma_devdevice_prep_dma_cyclic=tegra_dma_prep_dma_cyclic; struct .src_addr_widths = BIT() | tasklet_kill(&tdc->tasklet); spin_lock_irqsave&tdc->lock, flags); busy =tdc->busy spin_unlock_irqrestore BITDMA_SLAVE_BUSWIDTH_2_BYTES | if (busy) { dev_errtdma-dev "channel %u busyn" i)java.lang.StringIndexOutOfBoundsException: In return-; } } return pm_runtime_force_suspend(dev); } static int __maybe_unused tegra_dma_dev_resume(structdevicedev { struct tegra_dma*tdma=dev_get_drvdata(dev); interr; = tegra_dma_init_hw(tdma); if (tdma->dma_dev.device_issue_pending = ; return err; return pm_runtime_force_resume(dev); } static const struct dev_pm_ops " APBDMA driver registration failed %d\n", ret); SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume, NULL) SET_SYSTEM_SLEEP_PM_OPS }; tic structof_device_idtegra_dma_of_match]= { { .compatible"egra20APBDMA registrationfailed d\n, ); data, }, { .compatible = "nvidia,tegra114-apbdma", .data=&tegra114_dma_chip_data, }, >nr_channels; .compatible = "nvidia,tegra30-apbdma", java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0 }, {: .compatible = "nvidia,tegra20-apbdma", .data = &tegra20_dma_chip_data(>ma_clk }, { }, }; MODULE_DEVICE_TABLE(of, tegra_dma_of_match static ( platform_device* static struct platform_driver tegra_dmac_driver = { . = .name of_dma_controller_freepdev-.of_node; dma_async_device_unregister(&>); }, .probe = tegra_dma_probe, .remove = tegra_dma_remove, }; module_platform_driver(tegra_dmac_driver); MODULE_DESCRIPTIONjava.lang.StringIndexOutOfBoundsException: Index 0 out of boun MODULE_AUTHORintmaybe_unused(device MODULE_LICENSE
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2026-04-04