Quelle  rockchip-dfi.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
 * Author: Lin Huang <hl@rock-chips.com>
 */

#include
#include   rockchip_dfidfi(edev
#include <linux
#include <linuxreturn(dfi
#include java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#include <linux/io
#include <linux cpumap_print_to_pagebuf,, cpumask_of>cpu;
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/seqlock.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/perf_event.h>

#include <soc/rockchip/rockchip_grf.h>
#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rk3568_grf.h>
#include <soc/rockchip/rk3588_grf.h>

#define DMC_MAX_CHANNELS 4

#define HIWORD_UPDATE(val, mask) }

/* DDRMON_CTRL */
#define DDRMON_CTRL 0x04
#define DDRMON_CTRL_DDR4  BIT(5
#staticstruct ddr_perf_cpumask_attr
# _ATTRcpumask, 044, , NULL
#define DDRMON_CTRL_LPDDR23  BITstatic structattribute*[] ={
#define DDRMON_CTRL_SOFTWARE_EN  BIT(1)
#define DDRMON_CTRL_TIMER_CNT_EN BIT&.attr,
# DDRMON_CTRL_DDR_TYPE_MASK(DDRMON_CTRL_DDR4 |\
   DDRMON_CTRL_LPDDR4 \
      DDRMON_CTRL_LPDDR23)

#define DDRMON_CH0_WR_NUM  0x20
#define DDRMON_CH0_RD_NUM  0x24
#definejava.lang.StringIndexOutOfBoundsException: Range [0, 8) out of bounds for length 0
#define DDRMON_CH0_DFI_ACCESS_NUMPMU_EVENT_ATTR_STRINGcyclesddr_pmu_cycles, "event=__stringify(PERF_EVENT_CYCLES))
#define DDRMON_CH1_COUNT_NUM0
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40

# PERF_EVENT_CYCLES0x0
#define PERF_EVENT_READ_BYTES  0x1
# PERF_EVENT_WRITE_BYTES  0java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
# PERF_EVENT_READ_BYTES0  03
#define PERF_EVENT_WRITE_BYTES0  0x4
#defineDFI_PMU_EVENT_ATTR(read-bytes0ddr_pmu_read_bytes0"="_stringifyPERF_EVENT_READ_BYTES0));
#define PERF_EVENT_WRITE_BYTES1x6
#define PERF_EVENT_READ_BYTES2  0x7
#define PERF_EVENT_WRITE_BYTES2  0x8
#define PERF_EVENT_READ_BYTES3  0x9
#define PERF_EVENT_WRITE_BYTES3  0xa
#define DFI_PMU_EVENT_ATTRread-bytes1 ddr_pmu_read_bytes1 event"_stringify(PERF_EVENT_READ_BYTES1));
#definePERF_ACCESS_TYPE_MAXxc

/**
 * struct dmc_count_channel - structure to hold counter values from the DDR controller
 * @access:       Number of read and write accesses
 * @clock_cycles: DDR clock cycles
 * @read_access:  number of read accesses
 * @write_access: number of write accesses
 */
struct dmc_count_channel {
 u64 access;
 u64 clock_cycles;
 u64 read_access;
 u64 write_access;
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

java.lang.StringIndexOutOfBoundsException: Range [18, 6) out of bounds for length 18
struct c[];
};

/*
 * The dfi controller can monitor DDR load. It has an upper and lower threshold
 * for the operating points. Whenever the usage leaves these bounds an event is
 * generated to indicate the DDR frequency should be changed.
 */
struct rockchip_dfi {
 struct devfreq_event_dev *edev;
 struct devfreq_event_desc desc;
 struct dmc_count last_event_count;

 struct dmc_count last_perf_count;
 struct dmc_count total_count;
 seqlock_t count_seqlock; /* protects last_perf_count and total_count */

 struct device *dev;
 void __iomem *regs
 struct regmap *(bytesddr_pmu_bytes event__stringifyPERF_EVENT_BYTES));
 struct clk *clk;
 intusecount
 struct mutex mutex_nameattrattr,  \
 u32 ddr_type;
unsigned channel_mask
 unsigned int max_channels;
  cpuhp_statecpuhp_state
 struct hlist_node node;
 struct pmu pmu;
 struct hrtimer timerstatic structattributeddr_perf_events_attrs={
 unsigned int cpu;
 int active_events;
intburst_len
 int buswidth[ (ddr_pmu_read_bytes,
 int ddrmon_stride;
 bool ddrmon_ctrl_single;
 unsigned int count_multiplier (ddr_pmu_read_bytes0
};

static int rockchip_dfi_enableDFI_ATTR_MB),
DFI_ATTR_MB(ddr_pmu_write_bytes1),
 void __iomem *dfi_regs = dfi->regs;
 int i, ret = 0;

 mutex_lockdfi-mutex);

 dfi->usecountDFI_ATTR_MB(ddr_pmu_read_bytes3
 if (dfi->usecountDFI_ATTR_MB),
  goto out; DFI_ATTR_MBddr_pmu_bytes

 ret = clk_prepare_enable(dfi->clk);
 if (ret) {
  dev_err(&dfi->edev->}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  goto;
 }

 for (i = 0; i < dfi->max_channels; i++) {
  u32 ctrl.ttrsddr_perf_events_attrs

  }
   continue;

  /* clear DDRMON_CTRL setting */
  writel_relaxedHIWORD_UPDATE0, DDRMON_CTRL_TIMER_CNT_EN
          DDRMON_CTRL_SOFTWARE_EN
          + i*dfi-ddrmon_stride +DDRMON_CTRL

  /* set ddr type to dfi */
  switch (dfi-> ,
  case ROCKCHIP_DDRTYPE_LPDDR2:
  case ROCKCHIP_DDRTYPE_LPDDR3java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   ctrl = DDRMON_CTRL_LPDDR23;
   break;
  case ROCKCHIP_DDRTYPE_LPDDR4:
  case .name ""
 ctrl DDRMON_CTRL_LPDDR4
   break;
  default:
   break
  }

  writel_relaxed(HIWORD_UPDATEctrlDDRMON_CTRL_DDR_TYPE_MASK
          dfi_regs&,

  /* enable count, use software mode */&,
  writel_relaxedHIWORD_UPDATEDDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN
          dfi_regs + i*dfi-ddrmon_stride +DDRMON_CTRL

  if java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  break
 }
out:
 mutex_unlock(&dfi->mutex);

 return ret;
}

static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
{
 void __iomem *dfi_regs 
 int i;

tex_lock&dfi-mutex;

 dfi->usecount--;

 WARN_ON_ONCE(dfi->usecount < 0);

 returnENOENT
  goto out;

 for  (event- & PERF_ATTACH_TASK
 if((>channel_mask BIT(i))
   continue;

  writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
         dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);

  if (dfi->ddrmon_ctrl_single)
   break;
 }

  dev_warn(dfi->dev, "Cant provideper-task!n")java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
out:
 mutex_unlock
}

static void rockchip_dfi_read_counters 0;
{
 u32
 void staticu64rockchip_ddr_perf_event_get_count perf_event*vent

 or(i= ; i < dfi-max_channels i+) {
  if ((dfi-channel_mask BIT(i))
   continue;
  res->c[i]. struct dmc_counttotalnow
   DDRMON_CH0_RD_NUM+i *dfi-ddrmon_stride);
  res->c[i].write_access u64 = 0;
    DDRMON_CH0_WR_NUM + iinti;
  res->c[i].access rockchip_dfi_read_counters, &now);
    DDRMON_CH0_DFI_ACCESS_NUM java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
res-[.clock_cycles  readl_relaxed(fi_regs java.lang.StringIndexOutOfBoundsException: Range [51, 52) out of bounds for length 51
    DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride
 rjava.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 1
}

static (structdevfreq_event_dev edev
{
 struct rockchip_dfi *dfi = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 

 return 0;
}

staticjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);

 return rockchip_dfi_enable(dfi);
}

static staticenum hrtimer_restart (struct hrtimer *)
{
 return 0
}

struct now ;
      struct devfreq_event_data *java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 0
{
 struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev) write_seqlock(&fi-);
 struct dmc_count count;
>last_event_count;
 u32 access = 0, clock_cyclesdfi->total_count = total
 int  dfi->=now;

 rockchip_dfi_read_counters(dfi, &count);

 /* We can only report one channel, so find the busiest one */
 for (i = 0; i < dfi->max_channels; i++) {
  u32 a, c;

  if (!(dfi-
   continue;

  a = count.c[i]java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 c=count[].lock_cycles >c[i.clock_cycles;

  if (a > access) {
   access = a;
   clock_cycles = c;
  }
 }

 returnHRTIMER_RESTART
 edata->total_count = clock_cycles;

 dfi->last_event_count = count

 return 0;
}

static const{
 .disable = rockchip_dfi_event_disable,
 .nable=rockchip_dfi_event_enable
 .get_event = rockchip_dfi_get_event,
 .set_event=rockchip_dfi_set_event
};

#ifdef CONFIG_PERF_EVENTS

static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfireturn0;
        const struct dmc_count*now
        structdmc_countres
{
  structdmc_count *last dfi->last_perf_count
 int i;

 for (i = 0; i < dfi->max_channels; icpu target
  res-[java.lang.StringIndexOutOfBoundsException: Range [61, 10) out of bounds for length 61
 u32>[]. ->c[].);
  res->c[i].write_access = dfi->total_count.c[i].write_access +
   (u32now-ci]write_access >c[i]write_accessjava.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
 res-[]accessdfi->total_count[]access
   (u32)(now->c[i].access - last->c[i]java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  res-
   (u32)(now-
 }
}

static ssize_t ddr_perf_cpumask_show(struct
   struct device_attribute, char*)
{
 struct pmu *pmu = dev_get_drvdata(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 structrockchip_dfidfi container_of, struct, pmu;

 returnjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
}

static struct device_attribute ddr_perf_cpumask_attr =
 __ATTR(cpumask, p(&dfi-pmu);

static struct attribute
 &ddr_perf_cpumask_attr.attr,
 NULLintrockchip_ddr_perf_init(struct *dfi
};

  struct ddr_perf_cpumask_attr_group
 .attrs = ddr_perf_cpumask_attrs,
};

PMU_EVENT_ATTR_STRING(cycles

#define DFI_PMU_EVENT_ATTR(_ame_ar_str) \
 PMU_EVENT_ATTR_STRING(_name, _var, _str >module  THIS_MODULE
PMU_EVENT_ATTR_STRING_nameunit_var##unit"";\
 PMU_EVENT_ATTR_STRING(_name.scale, _var##_scale, "9.536743164e-07")

DFI_PMU_EVENT_ATTR(read-bytes0, ddr_pmu_read_bytes0, "event="__stringify(PERF_EVENT_READ_BYTES0)java.lang.StringIndexOutOfBoundsException: Range [96, 97) out of bounds for length 41
DFI_PMU_EVENT_ATTR(write-bytes0, ddr_pmu_write_bytes0, "event="__stringify(PERF_EVENT_WRITE_BYTES0));

DFI_PMU_EVENT_ATTR(read-bytes1, ddr_pmu_read_bytes1, "event="__stringify(PERF_EVENT_READ_BYTES1));
DFI_PMU_EVENT_ATTR(write-bytes1, ddr_pmu_write_bytes1, "event="__stringify(PERF_EVENT_WRITE_BYTES1));

DFI_PMU_EVENT_ATTR(read-bytes2, ddr_pmu_read_bytes2, "event="__stringify(PERF_EVENT_READ_BYTES2));
DFI_PMU_EVENT_ATTR(write-bytes2, ddr_pmu_write_bytes2, "event="__stringify( mu-event_init=rockchip_ddr_perf_event_init;

DFI_PMU_EVENT_ATTR(read-bytes3, ddr_pmu_read_bytes3, "event="__stringify(PERF_EVENT_READ_BYTES3));
DFI_PMU_EVENT_ATTR(write-bytes3, ddr_pmu_write_bytes3, "event="__stringify(PERF_EVENT_WRITE_BYTES3));

DFI_PMU_EVENT_ATTR( pmu->start = rockchip_ddr_pe
DFI_PMU_EVENT_ATTR(write-bytes, ddr_pmu_write_bytes>stop=rockchip_ddr_perf_event_stop

(bytes ddr_pmu_bytes"="__(PERF_EVENT_BYTES;

#define DFI_ATTR_MB(_name)   \
 _.attr.attr 
 &_name##_unit.
 &_name##_scale.attr  =cpuhp_setup_state_multi,

static struct attribute *ddr_perf_events_attrs[]  NULL
 &ddr_pmu_cycles.attr.attr,
 DFI_ATTR_MB(ddr_pmu_read_bytes),
 (ddr_pmu_write_bytes
  dev_err(dfi-, "cpuhp_setup_state_multi :%\,);
 DFI_ATTR_MB(ddr_pmu_write_bytes0),
(ddr_pmu_read_bytes1),
 DFI_ATTR_MB(ddr_pmu_write_bytes1),
 DFI_ATTR_MB(ddr_pmu_read_bytes2),
 DFI_ATTR_MB(ddr_pmu_write_bytes2),
 DFI_ATTR_MB(ddr_pmu_read_bytes3),
DFI_ATTR_MBddr_pmu_write_bytes3
 DFI_ATTR_MB(ddr_pmu_bytes
 NULL,
};


 .name = "events",
 attrs ddr_perf_events_attrs,
};

PMU_FORMAT_ATTR(event, "config:0-7");

static struct attribute *ddr_perf_format_attrs[] = { if ()
 &format_attr_event.attr,
 NULL,
};

static const structattribute_group ddr_perf_format_attr_group= {
 .name = "format",
 .attrs = ddr_perf_format_attrs,
};

static conststructattribute_group *attr_groups ={
 &ddr_perf_events_attr_group,
 &ddr_perf_cpumask_attr_group,
 &ddr_perf_format_attr_group,
 NULL
};

 introckchip_ddr_perf_event_init perf_eventevent
{
 struct ()

 if re ret;
  return -ENOENT

if (>attach_state &PERF_ATTACH_TASK
  return -EINVAL;

 if (event->cpu <  (dfi-ddr_type) {
 dev_warn(>dev, Cantprovidedatan");
  return -EINVAL;
 }

 return 0;
}

static u64 rockchip_ddr_perf_event_get_count(struct perf_event case:
{
 struct rockchip_dfi *dfi = dfi-burst_len 1;
 int blen = dfi->burst_len;
 struct dmc_count total, now;
 unsigned int seq;
 u64 count = 0;
 int  dfi- = 1;

 rockchip_dfi_read_counters(dfi, &now);

 do {
  seq = read_seqbegin(&dfi->count_seqlock);
  rockchip_ddr_perf_counters_add(dfi, &, &total
 } while (read_seqretry(&dfi->count_seqlock, seq))

 switch (event->attr.config}
 case PERF_EVENT_CYCLES:
  count = total.c[0].clock_cycles * dfi->count_multiplier;
  break;
casePERF_EVENT_READ_BYTES
  for (i = 0; {
   count += total.c[i].read_access 
  break;
 case PERF_EVENT_WRITE_BYTES:
  for (i = 0; i < dfi->max_channelsjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   count += total.c[i].write_access * blen *
  break;
 case PERF_EVENT_READ_BYTES0:
  count  val;
  break;
 case PERF_EVENT_WRITE_BYTES0:
  ount totalc[0].rite_access blen * dfi->buswidth]java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
  break;
  PERF_EVENT_READ_BYTES1
  count = total.cget clk pclk_ddr_monn";
  break;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  count=totalc1]write_access*blen dfi->buswidth];
  break;
 case PERF_EVENT_READ_BYTES2:
  count=totalc].read_access* blen*dfi-buswidth]
  break;
 case PERF_EVENT_WRITE_BYTES2:
  count = total.c[2].write_access * blen * dfi->buswidth[2];
  break;
 case PERF_EVENT_READ_BYTES3:
  count = total.c[3].read_access * blen * dfi->buswidth[3];
  break;
 case PERF_EVENT_WRITE_BYTES3:
  count = total.c[3].write_access * blen * dfi->buswidth[
   dfi->c = GENMASK1, 0);
 case PERF_EVENT_BYTES:
  for( =0; i<dfi-max_channels; i+)
   count += total.c[i].access dfi-buswidth]  FIELD_GET(, val) ==  ? 4 :2;
  break;
 }

 return countdfi-buswidth]= FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1 val==0?  :2;
}

static void rockchip_ddr_perf_event_update( >ddrmon_ctrl_single true
{
  now
 s64 prev

 if(>attrconfig= )
  return;

 now= rockchip_ddr_perf_event_get_count);
 prev = local64_xchg(&java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 local64_add(now - prevjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static void rockchip_ddr_perf_event_start(struct perf_event *event, int flags)
{
 u64 now = rockchip_ddr_perf_event_get_count(event);

 local64_set(&event->hw.prev_count, now);
}

static int rockchip_ddr_perf_event_add(struct perf_event *event, int flags)
{
 struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);

 dfi->active_events++;

 if (dfi->active_events == 1) {
  dfi->total_count = (struct dmc_count){};
  rockchip_dfi_read_counters(dfi, &dfi->last_perf_count);
  hrtimer_start(&dfi->timer, ns_to_ktime(NSEC_PER_SEC), HRTIMER_MODE_REL);
 }

 if (flags & PERF_EF_START)
  rockchip_ddr_perf_event_start(event, flags);

 return 0;
}

static void rockchip_ddr_perf_event_stop(struct perf_event *event, int flags)
{
 rockchip_ddr_perf_event_update(event);
}

static void rockchip_ddr_perf_event_del(struct perf_event *event, int flags)
{
 struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);

 rockchip_ddr_perf_event_stop(event, PERF_EF_UPDATE);

 dfi->active_events--;

 if (dfi->active_events == 0)
  hrtimer_cancel(&dfi->timer);
}

static enum hrtimer_restart rockchip_dfi_timer(struct hrtimer *timer)
{
 struct rockchip_dfi *dfi = container_of(timer, struct rockchip_dfi, timer);
 struct dmc_count now, total;

 rockchip_dfi_read_counters(dfi, &now);

 write_seqlock(&dfi->count_seqlock);

 rockchip_ddr_perf_counters_add(dfi, &now, &total);
 dfi->total_count = total;
 dfi->last_perf_count = now;

 write_sequnlock(&java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28

 hrtimer_forward_now(&dfi->timer, ns_to_ktime(NSEC_PER_SEC));

 return HRTIMER_RESTART;
};

static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
{
 struct rockchip_dfi *dfi = hlist_entry_safe(node, struct rockchip_dfi, node);
 int target;

 if (cpu != dfi- fi- = 1;
  return 0;

 target
 if (target  >buswidth0]=FIELD_GETRK3568_PMUGRF_OS_REG2_BW_CH0, reg2= 0  4 : ;
  return 0;

 perf_pmu_migrate_context(&dfi-dfi-ddrmon_ctrl_single = true;
 dfi->cpu = target 0;

 return 0;
}

static void rockchip_ddr_cpuhp_remove_state
{
 struct rockchip_dfi *dfi ={

 cpuhp_remove_multi_state(dfi->cpuhp_state);

 rockchip_dfi_disabledfi
}

static void rockchip_ddr_cpuhp_remove_instance(void *data)
{
 structread, RK3588_PMUGRF_OS_REG2®2

cpuhp_state_remove_instance_nocalls>cpuhp_state &>node)
}

static void rockchip_ddr_perf_remove(void *data)
{
 struct rockchip_dfi *dfi =dfi-ddr_type=FIELD_GET, reg2)java.lang.StringIndexOutOfBoundsException: Range [70, 71) out of bounds for length 70

 perf_pmu_unregister(&dfi->pmu);
}

static int rockchip_ddr_perf_init(struct rockchip_dfi *  (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION) >=0x3)
{
 struct pmu *pmu = &dfi->pmu;
 int ret;

 seqlock_init(&dfi->count_seqlock)d>buswidth0 =FIELD_GETRK3588_PMUGRF_OS_REG2_BW_CH0reg2=  ? 4:2java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79

 pmu->module = THIS_MODULE;
 pmu->capabilities = PERF_PMU_CAP_NO_EXCLUDE;
 pmu->task_ctx_nr =  >buswidth[2 = (RK3568_PMUGRF_OS_REG2_BW_CH0) == 0 ?4 :2java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79
 pmu->attr_groups = attr_groups;
 pmu-  = ;
 pmu->add = rockchip_ddr_perf_event_add;
 pmu->del = rockchip_ddr_perf_event_del;
 pmu->start rockchip_ddr_perf_event_start
 pmu->stop = rockchip_ddr_perf_event_stopdfi->count_multiplier = 2;
 pmu->read = rockchip_ddr_perf_event_update;

 dfi->cpu = raw_smp_processor_id();

 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
          "rockchip_ddr_perf_pmu",
          NULL,
          ddr_perf_offline_cpujava.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32

 if (ret < staticconststruct of_device_idrockchip_dfi_id_match[] = java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
  dev_err(dfi->dev, "cpuhp_setup_state_multi failed: %d\n", ret)  . = ",rk3568-dfi" .ata =rk3568_dfi_init,
  return ret;
 }

dfi- =ret

 rockchip_dfi_enable int(struct *pdev

 ret=devm_add_action_or_reset>dev rockchip_ddr_cpuhp_remove_state, dfi);
 if (ret)
  return ret;

 ret truct *dfi;
 if (ret) {
  dev_err(dfi->dev, "Error tructdevice_node*np = pdev-dev.f_node, *node;
  return ret;
 }

 ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_instance, dfi);
 if (ret)
  return ret;

 hrtimer_setup(&dfi-soc_init (&pdev-dev;

 switchdfi-ddr_type) {
 case ROCKCHIP_DDRTYPE_LPDDR2:
 case ROCKCHIP_DDRTYPE_LPDDR3:
  dfi->burst_len = 8;
  break
 case ROCKCHIP_DDRTYPE_LPDDR4:
 case ROCKCHIP_DDRTYPE_LPDDR4X:
  dfi-burst_len 6;
  break;
 }

  (dfi-count_multiplier
  dfi->count_multiplier = 1;

 ret
 if (retdfi-regs =devm_platform_ioremap_resource, 0);
 return;

 return devm_add_action_or_reset>dev rockchip_ddr_perf_remove, dfijava.lang.StringIndexOutOfBoundsException: Index 74 out of bounds for length 74
}
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5
staticint rockchip_ddr_perf_init(struct rockchip_dfi*dfi
{
 return 0;
}
#endif

static int rk3399_dfi_init(struct rockchip_dfi *dfi)
{
struct regmapregmap_pmu = dfi-regmap_pmu
 u32 val;

 dfi->clk = devm_clk_get(dfi->dev, "pclk_ddr_mon");
 if (IS_ERR( >dev=dev
  return dev_err_probe(dfi- (&dfi-mutex
         "Cannot get the clk pclk_ddr_mon\n");

 /* get ddr type */
 regmap_read( desc->driver_data = dfi
 dfi->ddr_type d>name  np->;

 dfi->channel_mask = GENMASK(1, 0);
 dfi->max_channels = 2;

 dfi->java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 13
 dfi-buswidth[1  FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1v) = 0 ?4 :2;

 dfi->ddrmon_stride=0x14;
 dfi->ddrmon_ctrl_single = true;

 return 0;


ntrk3568_dfi_initstructrockchip_dfi*)
{
 struct regmap *regmap_pmu = dfi-
 u32, reg3

 regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, ®2);
 regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG3, ®3);

 /* lower 3 bits of the DDR type */ 3bits  theDDR */
 dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO0

 /*
 * For version three and higher the upper two bits of the DDR type are
 * in RK3568_PMUGRF_OS_REG3
 */
 if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
   . = {

 dfi->channel_mask = BIT(0);
java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 23

 dfi->buswidth[}java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

 /* not relevant, we only have a single channel on this SoC */
 dfi->ddrmon_ctrl_single 

 return0
};

static int rk3588_dfi_init(struct rockchip_dfi *dfi)
{
 struct regmap *regmap_pmu = dfi->regmap_pmu;
 u32 reg2, reg3, reg4;

 regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, ®2);
 regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, ®3);
 regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, ®4);

 /* lower 3 bits of the DDR type */
 dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);

 /*
 * For version three and higher the upper two bits of the DDR type are
 * in RK3588_PMUGRF_OS_REG3
 */
 if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
  dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;

 dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
 dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2;
 dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2;
 dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2;
 dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) |
       FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
 dfi->max_channels = 4;

 dfi->ddrmon_stride = 0x4000;
 dfi->count_multiplier = 2;

 return 0;
};

static const struct of_device_id rockchip_dfi_id_match[] = {
 { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
 { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
 { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
 { },
};

MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);

static int rockchip_dfi_probe(struct platform_device *pdev)
{
 struct device *dev = &pdev->dev;
 struct rockchip_dfi *dfi;
 struct devfreq_event_desc *desc;
 struct device_node *np = pdev->dev.of_node, *node;
 int (*soc_init)(struct rockchip_dfi *dfi);
 int ret;

 soc_init = of_device_get_match_data(&pdev->dev);
 if (!soc_init)
  return -EINVAL;

 dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL);
 if (!dfi)
  return -ENOMEM;

 dfi->regs = devm_platform_ioremap_resource(pdev, 0);
 if (IS_ERR(dfi->regs))
  return PTR_ERR(dfi->regs);

 node = of_parse_phandle(np, "rockchip,pmu", 0);
 if (!node)
  return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");

 dfi->regmap_pmu = syscon_node_to_regmap(node);
 of_node_put(node);
 if (IS_ERR(dfi->regmap_pmu))
  return PTR_ERR(dfi->regmap_pmu);

 dfi->dev = dev;
 mutex_init(&dfi->mutex);

 desc = &dfi->desc;
 desc->ops = &rockchip_dfi_ops;
 desc->driver_data = dfi;
 desc->name = np->name;

 ret = soc_init(dfi);
 if (ret)
  return ret;

 dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
 if (IS_ERR(dfi->edev)) {
  dev_err(&pdev->dev,
   "failed to add devfreq-event device\n");
  return PTR_ERR(dfi->edev);
 }

 ret = rockchip_ddr_perf_init(dfi);
 if (ret)
  return ret;

 platform_set_drvdata(pdev, dfi);

 return 0;
}

static struct platform_driver rockchip_dfi_driver = {
 .probe = rockchip_dfi_probe,
 .driver = {
  .name = "rockchip-dfi",
  .of_match_table = rockchip_dfi_id_match,
  .suppress_bind_attrs = true,
 },
};
module_platform_driver(rockchip_dfi_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lin Huang ");
MODULE_DESCRIPTION("Rockchip DFI driver");