// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Driver for the Apple SoC PWM controller * * Copyright The Asahi Linux Contributors * * Limitations: * - The writes to cycle registers are shadowed until a write to * the control register. * - If both OFF_CYCLES and ON_CYCLES are set to 0, the output * is a constant off signal. * - When APPLE_PWM_CTRL is set to 0, the output is constant low
*/
chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*fpwm)); if (IS_ERR(chip)) return PTR_ERR(chip);
fpwm = to_apple_pwm(chip);
fpwm->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(fpwm->base)) return PTR_ERR(fpwm->base);
clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(clk)) return dev_err_probe(&pdev->dev, PTR_ERR(clk), "unable to get the clock");
/* * Uses the 24MHz system clock on all existing devices, can only * happen if the device tree is broken * * This check is done to prevent an overflow in .apply
*/
fpwm->clkrate = clk_get_rate(clk); if (fpwm->clkrate > NSEC_PER_SEC) return dev_err_probe(&pdev->dev, -EINVAL, "pwm clock out of range");
chip->ops = &apple_pwm_ops;
ret = devm_pwmchip_add(&pdev->dev, chip); if (ret < 0) return dev_err_probe(&pdev->dev, ret, "unable to add pwm chip");
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