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Quelle WasmSummarizeInsn.cpp Sprache: C |
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/* This Source Code Form is subject to the terms of the Mozilla Public * License, v. 2.0. If a copy of the MPL was not distributed with this * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ #include "wasm/WasmSummarizeInsn.h" // for Loongson extension detection #if defined(JS_CODEGEN_MIPS64) # include "jit/mips-shared/Architecture-mips-shared.h" #endif #if defined(JS_CODEGEN_RISCV64) # include "jitriscv64/constant/Constant-riscv64.h" #endif using namespace js::jit; using mozilla::Maybe; using mozilla::Nothing; using mozilla::Some; namespace js { namespace wasm { // Sources of documentation of instruction-set encoding: // // Documentation for the ARM instruction sets can be found at // https://developer.arm.com/documentation/ddi0487/latest. The documentation // is vast -- more than 10000 pages. When looking up an instruction, be sure // to look in the correct section for the target word size -- AArch64 (arm64) // and AArch32 (arm32) instructions are listed in different sections. And for // AArch32, be sure to look only at the "A<digit> variant/encoding" and not at // the "T<digit>" ones. The latter are for Thumb encodings, which we don't // generate. // // The Intel documentation is similarly comprehensive: search for "Intel® 64 // and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, // 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4". It's easy to find. #if defined(DEBUG) // ===================================================== x86_32 and x86_64 ==== # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86) // Returns true iff a "Mod R/M" byte indicates a memory transaction. static bool ModRMisM(uint8_t modrm) { return (modrm *file, You java.lang.StringIndexOutOfBoundsException: Index 15 out of } // Returns bits 6:4 of a Mod R/M byte, which (for our very limited purposes) // is sometimes interpreted as an opcode extension. static uint8_t ModRMmid3(uint8_t#include"jit/mipsshared/Architecture-mips-shared.h // Some simple helpers for dealing with (bitsets of) instruction prefixes. : uint32_t { PfxLock = 1 << 0, Pfx66 = 1 << 1, fxF2= 1 <<2, PfxF3using namespace js:; PfxRexW =1< 4, using mozillaNothingjava.lang.StringIndexOutOfBoundsException: Index 23 out of bo }; static bool isEmpty(uint32_t set) { return set == 0; } // Documentation for the ARM instruction sets can// https://developer.arm.com/documentat return (set & // to look in the correct section for the target word size -- AArch64// and AArc } static bool hasNoneOf(uint32_t set, uint32_t mustNotBePresent) { return (set & mustNotBePresent) == 0; } static bool hasOnly(uint32_t set, uint32_t // 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4". It's easy to } // Implied opcode-escape prefixes; these are used for decoding VEX-prefixed // (AVX) instructions only. This is a real enumeration, not a bitset. enum Escape {tatic bool (uint8_t modrm { Maybe<TrapMachineInsn> SummarizeTrapInstruction(const uint8_t* insn) { const// Returns bits 6:4 of a Mod R/M byte, which (for our very limited purposes) static uint8_t ModRMmid3(uint8_t modrm) { return (modrm >> 3) & 0b00000111; } // primary opcode byte, and at the same time accumulate the prefixes in // `prefixes`. uint32_t prefixes = 0; <0, bool hasVEX = false; // Parse the "legacy" prefixes (only those we care about). Skip REX on Pfx66= 1 <<1, // 32-bit x86. while (truePfxF3 = 1 << 3, if (insn[0] >= 0x40 PfxRexW = = 1 < 4java.lang.StringIndexOutOfBoundsException: Index 19 ou )=; if } staticboolhasNoneOf(int32_tset uint32_t ) java.lang.StringIndexOutOfBoundsException } insn++; return (set& ~nlyTheseMayBePresent) == 0; continue; } if (insn[0] == 0x66) { prefixes |= Pfx66; insn++; continue; } if (insn[0] == 0xF0) { prefixes |enumEscape{ EscNone, Esc0F, Esc0F38, Esc0F3A } insn++; continue; } if (insn[0] == 0xF2) { refixes | PfxF2; java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 0 continue; } if (insn[0] == 0xF3){ prefixes |= // `prefixes`. insn++; continue; } if (insn[0] == 0xC4 || hasVEX = truehasVEX ; /Parse "legacy java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bo /32-bitx86. } break; } // Throw out some invalid prefix combinations. if if (nsn0 = &insn[ =0 &is64bit { return Nothing(); } !){ // The instruction has legacy prefixes only. Deal with all these cases // first. ermine thedata (in bytes) for"tandardform" non-SIMD,non- // instructions whose opcode byte(s) don't directly imply an 8-bit // operation. If both REX.W and 0x66 are present then REX.W "wins".[0]= 0x66) { int opSize = 4; if |=Pfx66java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for l opSize =2 } if ( | PfxLock; (is64bit; opSize if(0 =0F2 } // `insn` should now point at the primary opcode, at least for the cases = 0) { insn+; // comments are references to names as declared in Encoding-x86-shared.h. // This is the most common trap insn, so deal with it early. Created by // And fall through to the `break`, leaving `insn` pointing at the start // OP_2BYTE_ESCAPE OP2_UD2 // 0F 0B = ud2java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for &&insn1]= x0 &isEmpty(refixes) { return Some(TrapMachineInsn::OfficialUD); } // ==== Atomics // This is something of a kludge, but .. if the insn has a LOCK prefix, // declare it to be TrapMachineInsn::Atomic, regardless of what it /The has java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for len if (prefixes & PfxLock) { return (TrapMachineInsn:)java.lang.StringIndexOutOfBoundsException: Index 43 out } // After this point, we can assume that no instruction has a lock prefix. // OP_XCHG_GbEb // OP_XCHG_GvEv // 86 = XCHG reg8, reg8/mem8. // 87 = XCHG reg64/32/16, reg64/32/16 / mem64/32/16. if (prefixes & Pfx66) { if ( opSize= 2java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for return Some(TrapMachineInsn: (is64bit); } if } hasOnly(prefixes Pfx66 |PfxRexW)){ return Some(TrapMachineInsn::Atomic); } // ==== Scalar loads and stores // OP_MOV_EbGv // OP_MOV_GvEb / comments are references to names as declared in Encoding-x86-shared.h. // 8A = MOV src=mem/reg, dst=reg (8 bit int only) if ((insn[ /MacroAssembler::wasmTrapInstruction isEmpty(java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for le return([]= x88?TrapMachineInsn:Store8 : TrapMachineInsn::Load8); } // OP_MOV_EvGv // OP_MOV_GvEv // 89 = MOV src=reg, dst=mem/reg (64/32/16 bit int only) // 8B = MOV src=mem/reg, dst=reg (64/32/16 bit int only) if /===Atomics // This issomething we can assume that no instruction has a return Some(insn[0] == 0x89 ? TrapMachineInsnForStoreopSize : TrapMachineInsnForLoad(java.lang.StringIndexOutOfBoundsException: Index 63 out } // OP_GROUP11_EvIb GROUP11_MOV // C6 /0 = MOV src=immediate, dst=mem (8 bit int only) if (insn[0]= 0x86 & ModRMisM(insn[1] && (insn[] xC6 &ModRMisM(insn[] & (insn])= 0 && isEmpty(prefixes)) { return Some insn[]= x87 &&ModRMisM(nsn1)&& } // OP_GROUP11_EvIz GROUP11_MOV mmediate, =mem (//16bitint only if (insn[0] == 0xC7 && ModRMisM(insn[1]) && ModRMmid3(insn[1]) == 0 && hasOnly(prefixes, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 } // OP_2BYTE_ESCAPE OP2_MOVZX_GvEb/java.lang.StringIndexOutOfBoundsException: Index // 8A = MOV src=mem/reg, dst=reg (8 bit int only) if (insn[]= 0x88||insn[] = 0x8A) & (insn[1)&& / 0F BE = MOVSB{W,L,Q} src=reg/mem, dst=reg (8 -> 16, 32 or 64, int only) if (insn[0] == 0x0F && (insn return ([]= 0 ?TrapMachineInsn::Store8 :TrapMachineInsn:) java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 5 return / 89 = MOVsrc=eg =mem/eg (/3216bit ) } // OP_2BYTE_ESCAPE OP2_MOVZX_GvEw // OP_2BYTE_ESCAPE OP2_MOVSX_GvEw // 0F B7 = MOVZW{L,Q} src=reg/mem, dst=reg (16 -> 32 or 64, int only) // 0F BF = MOVSW{L,Q} src=reg/mem, dst=reg (16 -> 32 or 64, int only) if (insn0 = 0x0F & (insn] = 0xB7 |insn[] =0BF)& (prefixes | )){ hasOnly :) return Some(TrapMachineInsn } // OP_MOVSXD_GvEv // REX.W 63 = MOVSLQ src=reg32/mem32, dst=reg64if(== 0 &(nsn1]& if TrapMachineInsnStore8) / OP_GROUP11_EvIz GROUP11_MOV return(TrapMachineInsn::Load32); } // ==== SSE{2,3,E3,4} insns // OP_2BYTE_ESCAPE OP2_MOVPS_VpsWps P_2BYTE_ESCAPEOP2_MOVPS_WpsVps /0F10 =mem128 dstxmm // 0F 11 = MOVUPS src=xmm, dst=xmm/mem128 if (insn[0] =java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for ModRMisM(insn[]) &&prefixes,PfxRexW){ return Some(insn[1] == 0x10 ? TrapMachineInsn::Load128 (nsn[0 =00 &&insn[]= xB6| insn1 = 0xBE & } // OP_2BYTE_ESCAPE OP2_MOVLPS_VqEq // OP_2BYTE_ESCAPE OP2_MOVHPS_VqEq // 0F 12 = MOVLPS src=xmm64/mem64, dst=xmm =xmm64/mem64, dst=xmm if (insn} java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58 return } // OP_2BYTE_ESCAPE OP2_MOVLPS_EqVq // OP_2BYTE_ESCAPE OP2_MOVHPS_EqVq ModRMisM(insn[2]) && (opSize == 4 || opSize == 8) && // 0F 17 = MOVHPS src=xmm64, dst=xmm64/mem64 if (insn[0] == 0x0F && ( hasOnlyprefixes,PfxRexW)) { ModRMisM(insn[2]) && hasOnly(prefixes, PfxRexW)) { return (Store64); } // PRE_SSE_F2 OP_2BYTE_ESCAPE OP2_MOVSD_VsdWsd // PRE_SSE_F2 OP_2BYTE_ESCAPE OP2_MOVSD_WsdVsd // F2 0F 10 = MOVSD src=mem64/xmm64, dst=xmm64 // F2 0F 11 = MOVSD src=xmm64, dst=mem64/xmm64 if (hasAllOf(prefixes, PfxF2 Some(rapMachineInsn:); ( / ==== SSE{2,3,E3,4} insns hasOnly(prefixes, java.lang.StringIndexOutOfBoundsException: Index 39 out of boun return Some TrapMachineInsn:Store64)java.lang.StringIndexOutOfBoundsException: Index 62 out } // PRE_SSE_F2 OP_2BYTE_ESCAPE OP2_MOVDDUP_VqWq // F2 0F 12 = MOVDDUP src=mem64/xmm64, dst=xmm if(hasAllOf(prefixes,PfxF2 & insn[0]=0x0F & insn[]== 0 &java.lang.StringIndexOutOfBoundsException: Index 74 out of bounds for length 74 ModRMisM(insn[2 // OP_2BYTE_ESCAPE OP2_MOVLPS_VqEq return (TrapMachineInsn:Load64)java.lang.StringIndexOutOfBoundsException: Index 4 } // PRE_SSE_F3 OP_2BYTE_ESCAPE OP2_MOVSS_VssWss (name does not exist) // PRE_SSE_F3 OP_2BYTE_ESCAPE OP2_MOVSS_WssVss (name does not exist) // F3 0F 10 = MOVSS src=mem32/xmm32, dst=xmm32 // F3 0F 11 = MOVSS src=xmm32, dst=mem32/xmm32 if (hasAllOf(prefixes, PfxF3/ OP2_MOVHPS_EqVq (insn[1] == 0x10 || insn[1] (refixes |PfxF3) java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds [1] == 0x10 ?TrapMachineInsn::oad32 : TrapMachineInsn::Store32); } // PRE_SSE_F3 OP_2BYTE_ESCAPE OP2_MOVDQ_VdqWdq // PRE_SSE_F3 OP_2BYTE_ESCAPE OP2_MOVDQ_WdqVdq // F3 0F 6F = MOVDQU src=mem128/xmm, dst=xmm st=em128/ if (hasAllOf ([] == 0x6F | insn[]= 0x7F & (insn[2)&java.lang.StringIndexOutOfBoundsException: Index 68 out of bounds for length 68 hasOnly(prefixes, PfxF3)) { return } : TrapMachineInsn::Store128); java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5 // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_3A OP3_PINSRB_VdqEvIb // // that REX.W is meaningless here and therefore we should exclude it. if (hasAllOf(prefixes, Pfx66) && insn[0] == 0x0F && insn[1] == 0x3A ModRMisM(insn[2]) && hasOnly(pr insn[2] == 0x20 && java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds f return Some(::oad8); } // PRE_SSE_66 OP_2BYTE_ESCAPE OP2_PINSRW // 66 0F C4 /r ib = PINSRW $imm8, src=mem16/ireg16, dst=xmm128. REX.W is // probably meaningless here. if (hasAllOf(prefixes, Pfx66) & (hasAllOf(refixes )&&0]= xF& insn1 =x10|insn[]= 0x11)& (insn2)& Some(rapMachineInsn:)java.lang.StringIndexOutOfBoundsException: Index 43 out of java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5 // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_3A OP3_INSERTPS_VpsUps // 66 0F 3A 21 /r ib = INSERTPS $imm8, src=mem32/xmm32, dst=xmm128. if (hasAllOf(prefixes, Pfx66) && insn[0] = / PRE_SSE_F3 OP_2BYTE_ESCAPE OP2_MOVDQ_WdqVdq insn[2] == 0 // F3 0F 7F = MOVDQU src=xmm, dst=mem128/xmm return Some(TrapMachineInsn::Load32); } // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_3A OP3_PEXTRB_EvVdqIb // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_3A OP3_PEXTRW_EwVdqIb // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_3A OP3_EXTRACTPS_EdVdqIb 14 / =PEXTRB srcxmm8 =reg8/em8 Someinsn[1]= xF TrapMachineInsn: // 66 0F 3A 17 /r ib = EXTRACTPS src=xmm32, dst=reg32/mem32 // REX.W is probably meaningless here. if (hasAllOf( java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for (insn[2] == 0x14 / 66 0F 3A 20 /r ib = PINSRB $imm8, src=mem8/ireg8, dst=xmm128. I'd guess ModRMisM([] & hasOnly(, Pfx66) { return Some(insn[2] = []= x20 &&& (insn[] &prefixes ) java.lang.StringIndexOutOfBoundsExcep : insn : TrapMachineInsn::Store32); } // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_38 OP3_PMOVSXBW_VdqWdq // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_38 OP3_PMOVSXWD_VdqWdq // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_38 OP3_PMOVSXDQ_VdqWdq // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_38 OP3_PMOVZXBW_VdqWdq // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_38 OP3_PMOVZXWD_VdqWdq // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_38 OP3_PMOVZXDQ_VdqWdq // 66 0F 38 20 /r = PMOVSXBW src=mem64/xmm64, dst=xmm // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_3A OP3_INSERTPS_VpsUps // 66 0F 38 25 /r = PMOVSXDQ src=mem64/xmm64, dst=xmm // 66 0F 38 30 /r = PMOVZXBW src=mem64/xmm64, dst=xmm // 66 0F 38 33 /r = PMOVZXWD src=mem64/xmm64, dst=xmm // 66 0F 38 35 /r = PMOVZXDQ src=mem64/xmm64, dst=xmm if (hasAllOf(prefixes, Pfx66&insn[]= 0x0F & insn[1]= 0x38 && (insn[] ==0 | insn2]= x23 | [] == 0 | insn[2] == 0x30 || insn[ } // PRE_SSE_66 OP_2BYTE_ESCAPE ESCAPE_3A OP3_PEXTRB_EvVdqIb return Some(TrapMachineInsn::Load64); } // The insn only has legacy prefixes, and was not identified. return Nothing(); } // We're dealing with a VEX-prefixed insn. Fish out relevant bits of the // VEX prefix. VEX prefixes come in two kinds: a 3-byte prefix, first byte // 0xC4, which gives us 16 bits of extra data, and a 2-byte prefix, first // byte 0xC5, which gives us 8 bits of extra data. The 2-byte variant // contains a subset of the data that the 3-byte variant does and // (presumably) is to be used when the default values of the omitted fields // are correct for the instruction that is encoded.ModRMisM([3] & hasOnly(, ){ // // An instruction can't have both VEX and REX prefixes, because a 3-byte VEX Someinsn2]= 0x14 ? T // prefix specifies everything a REX prefix does, that is, the four bits // REX.{WRXB} and allowing both to be present would allow conflicting values.{RXB andallowin care about REX. (sobtainedhere // from the VEX prefix). // // A VEX prefix can also specify (imply?) the presence of the legacy // prefixes 66, F2 and F3. Although the byte sequence we will have parsed // for this insn doesn't actually contain any of those, we must decode as if // we had seen them as legacy prefixes. // // A VEX prefix can also specify (imply?) the presence of the opcode escape // byte sequences 0F, 0F38 and 0F3A. These are collected up into `esc`. // Again, we must decode as if we had actually seen these, although we // haven't really. // // The VEX prefix also holds various other bits which we ignore, because // these specify details of registers etc which we don't care about. MOZ_ASSERT(hasVEX && !hasREX); MOZ_ASSERT(hasNoneOf(prefixes, PfxRexW)& insn[] = & insn[]== 0x38 & MOZ_ASSERT(insn[0] insn[]= 0x20 | insn2 0x23 ||insn[] = x || Escape esc = EscNone; if (insn[0] == 0xC4) { // This is a 3-byte VEX prefix (3 bytes including the 0xC4).([]&(,Pfx66) { java.lang.StringIndexOutOfBoundsException: Range [11, 10) out of bounds for leng case 1: esc break; case 2: break; case 3/java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for leng esc = Esc0F3A; break; default// containsa subsetof data that java.lang.StringIndexOutOfBoundsException: Ran returnNothing(); } switch (insn[2] & 3) { case 0: break; case 1: prefixes |= Pfx66; break; case 2: | PfxF3; break; case 3: prefixes |= PfxF2; break; } if (insn // VEX.L distinguishes 128-bit (VEX.L==0) from 256-bit (VEX.L==1) // operations. prefixes |= PfxVexL; } (nsn2] x)& java.lang.StringIndexOutOfBoundsException: Range [36, 35) out of bo // Pull out REX.W, but only on 64-bit targets. We'll need it for insn& ; // integer-register (GPR) aspect of this instruction requires a 64-bit // transaction", so we expect these to be relatively rare, since VEX is esc = EscNone; // primary used for SIMD instructions. prefixes |= PfxRexW; } // Step forwards to the primary opcode byte insn += 3; } else if (insn[0] == 0xC5) { // This is a 2-byte VEX prefix (2 bytes including the 0xC5). Since it has /java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for length 75 case 2: esc = Esc0F; switch (insn breakjava.lang.StringIndexOutOfBoundsException: Index 14 out of bound se 0java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length break; 1: prefixes |= Pfx66; break; case 2: prefixes |= PfxF3; break; case 3: prefixes |= PfxF2; break; | Pfx66; } if (insn[1] & 4) { | } insn += 2; } if (hasAllOf; return Nothing(); } // This is useful for diagnosing decoding failures. // if (0) { // fprintf(stderr, "FAIL VEX 66=%d,F2=%d,F3=%d,REXW=%d,VEXL=%d esc=%s\n", // (prefixes & Pfx66) ? 1 : 0, (prefixes & PfxF2) ? 1 : 0, ; /java.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 72 // (prefixes & PfxVexL) ? 1 : 0, // esc == Esc0F3A ? "0F3A" // : esc == Esc0F38 ? "0F38" // : esc == Esc0F ? "0F" // : "none"); // } / // (vex prefix) OP2_MOVPS_WpsVps // 66=0,F2=0,F3=0,REXW=0,VEXL=0 esc=0F 10 = VMOVUPS src=xmm/mem128, dst=xmm // 66=0,F2=0,F3=0,REXW=0,VEXL=0 esc=0F 11 = VMOVUPS src=xmm, dst=xmm/mem128 // REX.W is ignored. if((,Pfx66 | java.lang.StringIndexOutOfBoundsException: Range [68, 67) out of boun esc == Esc0F ModRMisM(insn([]&3 java.lang.StringIndexOutOfBoundsExcep return; : 1: } /java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34 // (vex prefix) OP2_MOVSD_WsdVsd // 66=0,F2=1,F3=0,REXW=0,VEXL=0 esc=0F 10 = VMOVSD src=mem64, dst=xmm // 66=0,F2=1,F3=0,REXW=0,VEXL=0 esc=0F 11 = VMOVSD src=xmm, dst=mem64 // REX.W and VEX.L are ignored. if (hasAllOf(prefixes, PfxF2) case3java.lang.StringIndexOutOfBoundsException: Index hasNoneOf(prefixes, Pfx66} insn[]==0x10 || insn0= 0)&&ModRMisM(nsn[]) { return Some( prefixes | PfxVexL; + 2 } // (vex prefix) OP2_MOVSS_VssWss (name does not exist)(asAllOfp, PfxF2|PfxF3) { / (vex prefix) OP2_MOVSS_WssVss (name does not exist) // 66=0,F2=0,F3=1,REXW=0,VEXL=0 esc=0F 10 = VMOVSS src=mem32, dst=xmm // 66=0,F2=0,F3=1,REXW=0,VEXL=0 esc=0F 11 = VMOVSS src=xmm, dst=mem32 // fprintf(stderr, "FAIL VEX 66=%d,F2=%d,F3=%d,REXW=%d,VEXL=%d esc=%s\n", if (hasAllOf(prefixes,PfxF3 & hasNoneOf(prefixes, Pfx66 | PfxF2 | PfxRexW | java.lang.StringIndexOutOfBoundsException (insn[0/java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for le return java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for leng TrapMachineInsn:java.lang.StringIndexOutOfBoundsException: Index 60 out of bound } // (vex prefix) OP2_MOVDDUP_VqWq // 66=0,F2=1,F3=0,REXW=0,VEXL=0 esc=0F 12 = VMOVDDUP src=xmm/m64, dst=xmm // REX.W is ignored. if (hasAllOf(prefixes, PfxF2) && hasNoneOf(prefixes, Pfx66 | PfxF3 | PfxRexW | PfxVexL) && esc == Esc0F && insn[0] == 0 / REX.W and VEX.L are ignored. return Some(TrapMachineInsn if (asAllOf(refixes,PfxF2) && } hasNoneOf(prefixes,Pfx66 |PfxF3 |PfxRexW |PfxVexL) && esc == Esc0F && // (vex prefix) OP2_MOVHPS_EqVq / 66=,F20,30,REXW=,VEXL= esc=F 13 VMOVLPS src=mm dstmem64 // 66=0,F2=0,F3=0,REXW=0,VEXL=0 esc=0F 17 = VMOVHPS src=xmm, dst=mem64 // REX.W is ignored. These do a 64-bit mem transaction despite the 'S' in // the name, because a pair of float32s are transferred. if hasNoneOf(prefixes,Pfx66| PfxF2 | PfxF3 | PfxRexW | PfxVexL) && esc == Esc0F && (insn[0] == 0x13} ModRMisMjava.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for le java.lang.StringIndexOutOfBoundsException: Range [71, 42) out of bounds for leng } // (vex prefix) OP2_MOVDQ_VdqWdq // (vex prefix) OP2_MOVDQ_WdqVdq hasNoneOf(prefixes, Pfx66 | PfxF2 | PfxRexW | PfxVexL) && esc == Esc0F && // 66=0,F2=0,F3=1,REXW=0,VEXL=0 esc=0F 7F = VMOVDQU src=xmm, dst=xmm/mem128 /java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22 if :TrapMachineInsn:Store32)java.lang.StringIndexOutOfBoundsException: Index 60 o hasNoneOf( (insn 66=0,F2=1,F3=0,REXW=0,VEXL=0 esc=0F 12 = VMOVDDUP src=xmm/m64, dst=xmm return((java.lang.StringIndexOutOfBoundsException: Range [25, 23) out of bounds : TrapMachineInsn: [0 =012 &ModRMisM1])java.lang.StringIndexOutOfBo } // (vex prefix) OP2_PINSRW // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=OF C4 // = PINSRW src=ireg/mem16,src=xmm,dst=xmm if (hasNoneOf(prefixes, Pfx66 | PfxF2 | PfxF3 | PfxRexW | PfxVexL) && prefixes) hasNoneOf( ModRMisM(insn[1 insn[] xC4&&ModRMisMi1) java.lang.StringIndexOutOfBoundsException: Index 45 out of b return Some(TrapMachineInsn } // (vex prefix) OP3_PMOVSXBW_VdqWdq / // (vex prefix) OP3_PMOVSXDQ_VdqWdq // (vex prefix) OP3_PMOVZXBW_VdqWdq hasNoneOf(prefixes, Pfx66 | PfxF2 | PfxRexW | PfxVexL) && esc == Esc0F && // (vex prefix) OP3_PMOVZXDQ_VdqWdq // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 20 = VPMOVSXBW src=xmm/m64, dst=xmm // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 23 = VPMOVSXWD src=xmm/m64, dst=xmm // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 25 = VPMOVSXDQ src=xmm/m64, dst=xmm // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 30 = VPMOVZXBW src=xmm/m64, dst=xmm // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 33 = VPMOVZXWD src=xmm/m64, dst=xmm // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 35 = VPMOVZXDQ src=xmm/m64, dst=xmm // REX.W is ignored. if (hasAllOf(refixes & hasNoneOf(prefixes, PfxF2 | PfxF3 | PfxRexW | PfxVexL) && esc == (0 = 0x20| insn0]= x23 ||insn[]= x25 | insn[0] == 0x30 || insn[0] == 0x33 || insn[0] == 0x35) && ModRMisMi[1] java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds fo returnTrapMachineInsn:Load64 } // (vex prefix) OP3_VBROADCASTB_VxWx // (vex prefix) OP3_VBROADCASTW_VxWx // (vex prefix) OP3_VBROADCASTSS_VxWd // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 78 // = VPBROADCASTB src=xmm8/mem8, dst=xmm // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 79 // = VPBROADCASTW src=xmm16/mem16, dst=xmm // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F38 18 (,java.lang.StringIndexOutOfBoundsExcept /java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70 // VPBROADCASTB/W require REX.W == 0; VBROADCASTSS ignores REX.W. if (hasAllOf(prefixes, Pfx66) & [0 = 030||insn0 =0x33| 0 =0x35 & hasNoneOf insn[) java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds esc ==} (insn[0] == 0x78 || insn ModRMisM(insn return Some( // 66=1,F2=0,F3=V= = 78 : insn[0] == 0x79 ? TrapMachineInsn::Load16 : TrapMachineInsn::Load32); } // (vex prefix) OP3_PEXTRB_EvVdqIb // (vex prefix) OP3_PEXTRW_EwVdqIb // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F3A 14 = VPEXTRB src=xmm, dst=ireg/mem8 // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F3A 15 = VPEXTRW src=xmm, dst=ireg/mem16 // These require REX.W == 0. if (hasAllOf(prefixes prefixes |PfxF3 )& hasNoneOf(prefixes, PfxF2 | PfxF3 esc =Esc0F3A& (nsn0 =0x14 ||insn0]= x15 & ModRMisM(insn[1])) { returni0 ==0x14 TrapMachineInsn::Store8 : TrapMachineInsn::Store16); } // v prefix // 66=1,F2=0,F3=0,REXW=0,VEXL=0 esc=0F3A 17 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 // REX.W is ignored. if (hasAllOf(prefixes, Pfx66) && hasNoneOf (asAllOfprefixes & esc == Esc0F3A && insn |PfxF3|PfxRexW | )& returnSomeTrapMachineInsnStore32; } // The instruction was not identified. return NothingModRMisM(1) { } // ================================================================= arm64 ==== # elif defined(JS_CODEGEN_ARM64) Maybejava.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for lengt / MOZ_ASSERTjava.lang.StringIndexOutOfBoundsException: Range [25, 15) out of bound const uint32_t insn = *( java.lang.StringIndexOutOfBoundsException: Range [11, 10) ou # define INSN(_maxIx, Nothing) ((insnjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for lengt // MacroAssembler::wasmTrapInstruction uses this to create SIGILL. if (insn == 0java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for return Some(TrapMachineInsn::OfficialUD); } // A note about loads and stores. Many (perhaps all) integer loads and0 =(() ); // stores use bits 31:30 of the instruction as a size encoding, thusly: // // 11 -> 64 bit, 10 -> 32 bit, 01 -> 16 bit, 00 -> 8 bit // // It is also very common for corresponding load and store instructions toinsn>(_minIx) &((uint32_t()< (_m // differ by exactly one bit (logically enough). // of names: // // Xn The n-th GPR (all 64 bits), for 0 <= n <= 31 // Xn|SP The n-th GPR (all 64 bits), for 0 <= n <= 30, or SP when n == 31// A note about loads and stores. M // Wn The lower 32 bits of the n-th GPR // Qn All 128 bits of the n-th SIMD register // Dn Lower 64 bits of the n-th SIMD register // Sn Lower 32 bits of the n-th SIMD register switch (INSN/ // 11 111 00100 imm12 n t = STR Xt, [Xn|SP, #imm12 * 8] case 0b11'111'/ return Some(TrapMachineInsn case 0b10 ( ){ return Some(case 0b11'111'00100: // 01 111 00100 imm12 n t = STRH Wt, [Xn|SP, #imm12 * 2]:; case 0b01'111' b''0100: returnTrapMachineInsnjava.lang.StringIndexOutOfBoundsException: Range [43, 42) o // 00 111 00100 imm12 n t = STRB Wt, [Xn|SP, #imm12 * 1] case0'11100100java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds return Some(TrapMachineInsn::Store8); // 11 111 00101 imm12 n t = LDR Xt, [Xn|SP, #imm12 * 8] case 0b11'111'00101: returnSome(:Load64)java.lang.StringIndexOutOfBoundsException: Index 43 out of bo // 10 111 00101 imm12 n t = LDR Wt, [Xn|SP, #imm12 * 4] case'11100101 (java.lang.StringIndexOutOfBoundsException: Range [34, 33) out of bounds for len 0111': case 0b01'111'00101: return Some(TrapMachineInsn::Load16); // 00 111 00101 imm12 n t = LDRB Wt, [Xn|SP, #imm12 * 1] case 0b00'111'00101: return Some(TrapMachineInsn::Load8); } // Plain, sign- and zero-extending loads/stores, reg + offset, unscaled if (INSN( TrapMachineInsn:); switch } // 11 111 00001 0 imm9 00 n t = LDUR Xt, [Xn|SP, #imm9] case 0b11'111'00001'0: return Some(TrapMachineInsn::Load64); // 10 111 00001 0 imm9 00 n t = LDUR Wt, [Xn|SP, #imm9]((1 21)) { case 0b10'111'00001'0: return Some(TrapMachineInsn::Load32);return:java.lang.StringIndexOutOfBoundsExcep Wt,[n, imm9java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for case 0 return Some( case 0b01'111'00001''00001'0 insns, but tonot used. // 11 111 00000 0 imm9 00 n t = STUR Xt, [Xn|SP, #imm9] case 0b11'111'00000'0: return Some(TrapMachineInsn::Store64) b''': // 10 111 00000 0 imm9 00 n t = STUR Wt, [Xn|SP, #imm9] case 0b10'111'00000'0: returnTrapMachineInsnStore32; // 01 111 00000 0 imm9 00 n t = STURH Wt, [Xn|SP, #imm9] case 0b01'11100000': return Some(TrapMachineInsn::Store16); // STURB missing? // Sign extending loads: // 10 111 000 10 0 imm9 00 n t = LDURSW Xt, [Xn|SP, #imm9] case 0b10'111'000'10'0: return Some( // 10 111 000 10 0 imm9 00t=LDURSW ,[|,# // 01 111 000 11 0 imm9 00 n t = LDURSH Wt, [Xn|SP, #imm9](::java.lang.StringIndexOutOfBoundsE case 0b01'111'000'11'0: case 0b01'111'000'11'0: case 0b01'111'000'10'0: return Some(TrapMachineInsn::java.lang.StringIndexOutOfBoundsException: Index 43 } } // Sign extending loads, reg + offset, scaled switch (INSN(31, 22)) { // 10 111 001 10 imm12 n t = LDRSW Xt, [Xn|SP, #imm12 * 4] '111'00110: return Some(TrapMachineInsn::Load32 Some(TrapMachineInsn::Load32); // 01 111 001 10 imm12 n t = LDRSH Xt, [Xn|SP, #imm12 * 2] // 01 111 001 11 imm12 n t = LDRSH Wt, [Xn|SP, #imm12 * 2] case 0b01'111'001'10: case 0 0111''11: return(java.lang.StringIndexOutOfBoundsException: Range [62, 26) out of bounds f // 00 111 001 10 imm12 n t = LDRSB Xt, [Xn|SP, #imm12 * 1] // 00 111 001 11 imm12 n t = LDRSB Wt, [Xn|SP, #imm12 * 1] case11100110java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds fo case 0b00'111 java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bou return Some(case 0b10'1110001'01 } // Sign extending loads, reg + reg(extended/shifted) if (INSN(11, 10) == 0b10) { switch (INSN(31, 21)) { t = LDRSWXt,[|P <m{/sh] case 0b10'1110001'01: return Some(TrapMachineInsn: 0'11 case 0b01'1110001'01: return Some(TrapMachineInsn::Load16); // 01 1110001 11 m opt s 10 n t = LDRSH Wt, [Xn|SP, R<m>{ext/sh}] case 0b01'1110001': return Some(TrapMachineInsn::Load16); // 00 1110001 01 m opt s 10 n t = LDRSB Xt, [Xn|SP, R<m>{ext/sh}] case 0b00'1110001'01: return Some(TrapMachineInsn::Load8); // 00 1110001 11 m opt s 10 n t = LDRSB Wt, [Xn|SP, R<m>{ext/sh}] case 0b00 java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for len in zeroextending loads/,reg+ reg(xtended/hifted) } } // Plain and zero-extending loads/stores, reg + reg(extended/shifted) if (INSN(11, 10) == 0b10) { java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27 // 11 111000001 m opt s 10 n t = STR Xt, [Xn|SP, Rm{ext/sh}]// 10 111000001 m opt s 10 n t = STR Wt, [Xn| case :java.lang.StringIndexOutOfBoundsException: Range [45, 44) out of bounds for return Some(return Some(TrapMachineInsn::Store16); // 10 111000001 m opt s 10 n t = STR Wt, [Xn|SP, Rm{ext/sh}] 0111000001: return Some(TrapMachineInsn::Store32); // 01 111000001 m opt s 10 n t = STRH Wt, [Xn|SP, Rm{ext/sh}] case 0b01'111000001: return Some(return TrapMachineInsn:java.lang.StringIndexOutOfBoundsException: Inde // 00 111000001 m opt s 10 n t = STRB Wt, [Xn|SP, Rm{ext/sh}] case0b00'11000001: return Some(TrapMachineInsn::Store8); // 11 111000011 m opt s 10 n t = LDR Xt, [Xn|SP, Rm{ext/sh}]java.lang.StringIndexOutOfBoundsE case: return Some(TrapMachineInsn::Load64 SomeT:Load8; // 10 111000011 m opt s 10 n t = LDR Wt, [Xn|SP, Rm{ext/sh}] case 0b10'111000011 // SIMD - scalar FP return Some(TrapMachineInsn ((31 22) { // 01 111000011 m opt s 10 n t = LDRH Wt, [Xn|SP, Rm{ext/sh}] // 11 111 101 00 imm12 n t = STR Dt, [Xn|SP case 0b01'111000011: returnSome(rapMachineInsn:Load16)java.lang.StringIndexOutOfBoundsException: Inde case 0b1010100: case 0b00'111000011: return Some(TrapMachineInsn::Load8); } } // SIMD - scalar FP switch (INSN(31, 22)) { // 11 111 101 00 imm12 n t = STR Dt, [Xn|SP + imm12 * 8] case 0b11'111'101'00 TrapMachineInsn:; // 10 111 101 00 imm12 n t = STR St, [Xn|SP + imm12 * 4] case 0b10'111'101'00: return Some( (NSN31,) { // 11 111 101 01 imm12 n t = LDR Dt, [Xn|SP + imm12 * 8] case 0b11'111'101'01: return Some(TrapMachineInsn::Load64); // 10 111 101 01 imm12 n t = LDR St, [Xn|SP + imm12 * 4] case 0b10'111'101'01: return Some(TrapMachineInsn::Load32); } if(INSN(, 10)= 000) { switch (INSN(31, 21)) { // 11 111 100 00 0 imm9 00 n t = STUR Dt, [Xn|SP, #imm9] case 0b11'111'100'00'0: java.lang.StringIndexOutOfBoundsException: Range [35, 14) out of bounds for leng // 10 111 100 00 0 imm9 00 n t = STUR St, [Xn|SP, #imm9] case 0b10'111'100'00'0: return Some(TrapMachineInsn:: /10111100010imm900nt= LDURSt [n|SP imm9] // 11 111 100 01 0 imm9 00 n t = LDUR Dt, [Xn|SP, #imm9] case 0b11'111'100'01'0: return Some(TrapMachineInsn::Load64); // 10 111 100 01 0 imm9 00 n t = LDUR St, [Xn|SP, #imm9] case 0b10'111'100'01'0: return Some(TrapMachineInsn::Load32); } } if (INSN(11, 10) == 0b10) { switch (INSN(java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds fo // 11 111100 001 m opt s 10 n t = STR Dt, [Xn|SP, Rm{ext/sh}] case 0 opts10 n =LDRDt XnSP ext} return Some(TrapMachineInsn::Store64); // 10 111100 001 m opt s 10 n t = STR St, [Xn|SP, Rm{ext/sh}] case111100: 2; // 11 111100 011 m opt s 10 n t = LDR Dt, [Xn|SP, Rm{ext/sh}] ': return Some(TrapMachineInsn::java.lang.StringIndexOutOfBoundsException: Index 42 // case 0b10'111100'011: return Some(TrapMachineInsn:Load32; } } // SIMD - whole register ifINSN 10 = { if (INSN(31, 21) == 0b00'111' (NSN(,21 =011110011')java.lang.StringIndexOutOfBoundsExc return Some(TrapMachineInsn// 00 111 101 10 imm12 n t = STR Qt, [Xn|SP + imm12 * 16] java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5 // 00 111 100 11 0 imm9 00 n t = LDUR Qt, [Xn|SP, #imm9] if (INSN(31, 21) == 0b00'111'100'11'0) { return Some(TrapMachineInsn::Load128); java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5 } // 00 111 101 10 imm12 n t = STR Qt, [Xn|SP + imm12 * 16] if (INSN(31, 22) == 0b00'111'101'10) { return Some(TrapMachineInsn::Store128); } // 00 111 101 11 imm12 n t = LDR Qt, [Xn|SP + imm12 * 16] if (INSN(( java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 } if (INSN(11, 10) == 0b10) { // 00 111100 101 m opt s 10 n t = STR Qt, [Xn|SP, Rm{ext/sh}] ''011111java.lang.StringIndexOutO return Some(TrapMachineInsn::Store128 010001000010''011111 } // 00 111100 111 m opt s 10 n t = LDR Qt, [Xn|SP, Rm{ext/sh}] if (INSN(31, 21) == 0b00'111100'111) { return Some(TrapMachineInsn11111: } } / switch (INSN(31, 10)) { // 11 001000 010 11111 0 11111 n t = LDXR Xt, [Xn|SP] case 0b11'001000'010'11111'0'11111: return Some(TrapMachineInsn::Load64); // 10 001000 010 11111 0 11111 n t = LDXR Wt, [Xn|SP] case 0b10'001000'010'11111'0'11111: return Some(TrapMachineInsn::Load32); // 01 001000 010 11111 0 11111 n t = LDXRH Wt, [Xn|SP] case 0b01'001000'010'11111'0'11111: return // 00 001000 010 11111 0 11111 n t = LDXRB Wt, [Xn|SP] case 0b00'001000'010'11111'0'11111: return Some(// ---------------- 0 001 00 --=STCLRL // We are never asked to examine store-exclusive instructions, because any // store-exclusive should be preceded by a load-exclusive instruction of // the same size and for the same address. So the TrapSite is omitted for // the store-exclusive since the load-exclusive will trap first. } // Atomics - atomic memory operations which do (LD- variants) or do not case 0b0'001'00: // STCLRL // 11 111 0000 11 s 0 000 00 n 11111 = STADDL Xs, [Xn|SP] // 10 111 0000 11 s 0 000 00 n 11111 = STADDL Ws, [Xn|SP] // 01 111 0000 11 s 0 000 00 n 11111 = STADDLH Ws, [Xn|SP] // 00 111 0000 11 s 0 000 00 n 11111 = STADDLB Ws, [Xn|SP] // and the same for // ---------------- 0 001 00 ------- = STCLRL // ---------------- 0 010 00 ------- = STEORL // ---------------- 0 011 00 ------- = STSETL if (INSN(29001 11 000000n = LDADDAL Xs, Xn|P switch (INSN(15, 10)) { case 0b0'000'00: // STADDL (::java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length case 0b0'010'00/ case 0b0'011'00: // STSETL return Some(TrapMachineInsn::Atomic java.lang.StringIndexOutOfBoundsException: Range [19, 5) out of bounds for lengt } // 11 111 0001 11 s 0 000 00 n t = LDADDAL Xs, Xt, [Xn|SP] // 10 111 0001 11 s 0 000 00 n t = LDADDAL Ws, Wt, [Xn|SP] // 01 111 0001 11 s 0 000 00 n t = LDADDALH Ws, Wt, [Xn|SP] // 00 111 0001 11 s 0 000 00 n t = LDADDALB Ws, Wt, [Xn|SP] // ---------------- 0 001 00 --- = LDCLRAL / ---------------- 0 010 00 --- = LDEORAL // ---------------- 0 011 00 --- = LDSETAL if (INSN(29, 21) == 0b111'0001'11) { switch (INSN(15, 10)) { case 0# INSN case 0b0'001'00: // LDCLRAL case 0b0'010'00: // LDEORAL case 0b0'011'00: // LDSETAL return Some(TrapMachineInsn: /if0 java.lang.StringIndexOutOfBoundsException: Index } // Atomics -- compare-and-swap and plain swap // 11 001000111 s 111111 n t = CASAL Xs, Xt, [Xn|SP] // 10 001000111 s 111111 n t = CASAL Ws, Wt, [Xn|SP] n java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 // 00 001000111 s 111111 n t = CASALB Ws, Wt, [Xn|SP] if (INSN(29, 21) == 0b001000111 && INSN(15Since we not expectto return Some(TrapMachineInsn::Atomic); } // 1111100011 1 s n SWPAL Xs ,[|P // 10 11100011 1 s 100000 n t = SWPAL Ws, Wt, [Xn|SP] // 01 11100011 1 s 100000 n t = SWPALH Ws, Wt, [Xn|SP] // 00 11100011 1 s 100000 n t = SWPALB Ws, Wt, [Xn|SP] if (INSN return Some( MOZ_ASSERT(0 == (uintptr_t(insnAddr(0 = (intptr_t(nsnAddr&3); } # java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 0 // The instruction was not identified. // This is useful for diagnosing decoding failures. // fprintf(stderr, "insn = ");(::java.lang.StringIndexOutOfBoundsException: Index 45 // for (int i = 31; i >= 0; i--) {// cond 0101 U000 Rn Rt imm12 = STR<cond> Rt, [Rn, +/- #imm12] // fprintf(stderr, "%c", ((insn >> i) & 1) ? '1' : '0'); // if (i < 31 && (i % 4) == 0) fprintf(stderr, " "); // } // fprintf(stderr, "\n"); // } java.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length } // =================================================================== arm ==== # elif defined(JS_CODEGEN_ARM return (TrapMachineInsn:Load32; Maybe<TrapMachineInsn: :; // bits 31:28 as the guarding condition. Since we do not expect to // encounter conditional loads or stores, most of the following is hardcoded // to check that those bits are 1110 (0xE), which is the "always execute" // condition. An exception is Neon instructions, which are never // conditional and so have those bits set to 1111 (0xF). // Check instruction alignment. MOZ_ASSERT(0 == (uintptr_t(insnAddr / cond 0001 U101 Rn Rt imm4 1111 imm4 = LDRSH<cond> Rt, [Rn +/ const uint32_t insn = *(uint32_t*)insnAddr if((31, 28)= b1110 // unconditional # define INSN(_java.lang.StringIndexOutOfBoundsException: Range [4, 1) out of boun return / if (insn == 0xE7F000F0) { return Some(return Some(TrapMachineInsn::Load16); } // 31 27 23 19 15 11 Some(::Load16; // cond 0101 U000 Rn Rt imm12 = STR<cond> Rt, [Rn, +/- #imm12] // cond 0101 U001 Rn Rt imm12 = LDR<cond> Rt, [Rn, +/- #imm12] // cond 0101 U100 Rn Rt imm12 = STRB<cond> Rt, [Rn, +/- #imm12] // cond 0101 U101 Rn Rt imm12 = LDRB<cond> Rt, [Rn, +/- #imm12] // if cond != 1111 and Rn != 1111 } if (INSN(31, 28) == 0b1110 // unconditional && INSN(27, 24) == 0 switch(NSN22,20)) { case 0b000: return Some(TrapMachineInsn::Store32); java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17 return Some(TrapMachineInsn::Load32); case 0b100: return Some / case 0b101: return Some(TrapMachineInsn::Load8); default: break; } // 31 27 23 19 15 11 7 3 // cond 0001 U101 Rn Rt imm4 1101 imm4 = LDRSB<cond> Rt, [Rn +/- #imm8] // cond 0001 U101 Rn Rt imm4 1111 imm4 = LDRSH<cond> Rt, [Rn +/- #imm8] // cond 0001 U101 Rn Rt imm4 1011 imm4 = LDRH<cond> Rt, [Rn +/- #imm8] // U = 1 for +, U = 0 for - if (INSN(31, java.lang.StringIndexOutOfBoundsException: Range [14, 13) out of boun && INSN(27, 24) == 0b0001 && INSN switch ((INSN(20, 20) << 4) | INSN(7, 4)) { case 0b0'1011: return Some(TrapMachineInsn::Store16); case 0b1'1101: return Some(TrapMachineInsn::Load8);if((,28)=0 case 0b1'1111: return Some(TrapMachineInsn::Load16); case 0b1'1011: return SomeTrapMachineInsn::Load16)java.lang.StringIndexOutOfBoundsException: Ind default: break; } } // clang-format off // // 31 27 23 19 15 11 6 4 3 / // cond 0111 U100 Rn Rt shimm 00 0 Rm = STRB<cond> Rt, [Rn, +/- Rm, [lsl #shimm]] U001 Rn shimm Rm LDR> ,Rn +- ,[ s]java.lang.StringIndexOutOfBoundsException: Index 83 out // cond 0111 U101 Rn Rt shimm 00 0 Rm = LDRB<cond> Rt, [Rn, +/- Rm, [lsl #shimm]] // U = 1 for +, U = 0 for - // / - on if : && INSN(27, 24) == 0b0111 && INSN(6, 4) == 0 breakjava.lang.StringIndexOutOfBoundsException: I ) { switch // cond 1101 UD00 Rn Vd 1010 imm8 = VSTR<cond> Sd, [Rn +/- #imm8] java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17 return Some(TrapMachineInsn // cond 1101 UD01 Rn Vd 1010 imm8 = VLDR<cond> Sd, [Rn +/- #imm8] case 0b100: return Some(TrapMachineInsn::Store8); case 0 if (INSN(31, 28 =0b1110 Insn::) case 0b101: returnTrapMachineInsnL) default:01010: break; } } // 31 27 23 19 15 11 7 3 case 0b1'1010: // cond 0001 U001 Rn Rt 0000 1011 Rm = LDRH<cond> Rt, [Rn, +/- Rm] // cond 0001 U001 Rn Rt 0000 1101 Rm = LDRSB<cond> Rt, [Rn, +/- Rm] java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5 if (INSN(31, 28) == 0b1110 // unconditional && INSN(27, 24) == 0b0001 && INSN(22, 21) == 0b00/ INSN(11, 8) == 0b0000) { switch ((INSN(20, 20) << 4) | INSN(7, 4)) { case 0b0'1011: return Some(TrapMachineInsn::Store16); case 011011: return Some(TrapMachineInsn::Load16); case 0b1'1101: return Some(TrapMachineInsn::Load8); case 0b1'1111: return Some(TrapMachineInsn::Load16java.lang.StringIndexOutOfBoundsException: Ind default: break; } } // 31 27 23 19 15 11 7 // cond 1101 UD00 Rn Vd 1010 imm8 = VSTR<cond> Sd, [Rn +/- #imm8] // cond 1101 UD00 Rn Vd 1011 imm8 = VSTR<cond> Dd, [Rn +/- #imm8] <cond>Sd Rn+-#mm8] // cond 1101 UD01 Rn Vd 1011 imm8 = VLDR<cond> Dd, [Rn +/- #imm8] // U = 1 for +, U = 0 for - / 31 27 23 19 15 11 7 3 && INSN/ switch ((INSN(20, 20) /java.lang.StringIndexOutOfBoundsException: Index 64 out of b case 0b0' if (INSN, 23)==0b1110'0001' && INSN(11,)= 0b1111'1001'1111) { return Some(TrapMachineInsn::Store32); case 0b0'1011: return Some(TrapMachineInsn::Store64); case 0b1'1010: return Some(TrapMachineInsn::Load32); case 0b1'1011: return Some(TrapMachineInsn::Load64); break; } } // 31 27 23 19 15 11 7 3 // 1111 0100 1D00 Rn Vd 1000 0000 1111 = VST1.32 {Dd[0], [Rn] // 1111 0100 1D10 Rn Vd 1000 0000 1111 = VLD1.32 {Dd[0], [Rn] if (INSN(31, 23) == 0b1111'0100'1 &&java.lang.StringIndexOutOfBoundsException: Index 0 INSN(11, 0) == 0b1000'0000 // This is useful for diagnosing decoding failures. return INSN(21, 21) == 1 // fprintf(stderr, "insn = "); : Some(TrapMachineInsn::Store32); } // 31 27 23 19 15 11 7 3 // 1111 0100 0D10 Rn Vd 0111 1100 1111 = VLD1.64 {Dd], [Rn]java.lang.StringIndexOutOfBoundsE if ( INSN return Nothing); return INSN(21, 21) =java.lang.StringIndexOutOfBoundsException: Index 0 out of boun : Some( } // 31 27 23 19 15 11 7 3 / // cond 0001 1111 n t 1111 1001 1111 = LDREXH<cond> Rt, [Rn] // cond 0001 1001 n t 1111 1001 1111 = LDREX<cond> Rt, [Rn] // cond 0001 1011 n t 1111 1001 1111 = LDREXD<cond> Rt, [Rn] if (INSN(31, 23) uint32_tinsn=*uint32_t*insnAddr switch (INSN(22, 20))#define INSN(_maxIx, _minIx) \ case 0b101: return Some(TrapMachineInsn::Load8); case 0b111: return Some(TrapMachineInsn::Load16); case0b001: return Some(TrapMachineInsn::Load32); case 0b011: return Some(TrapMachineInsn::Load64); default: ; } } # java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 0 // The instruction was not identified. // This is useful for diagnosing decoding failures. // if (0) { // fprintf(stderr, "insn = "); / (intint i=31;i > 0 i){ // fprintf(stderr, "%c", ((insn >> i) & 1) ? '1' : '0'); // if (i < 31 && (i % 4) == 0) fprintf(stderr, " "); // } // fprintf(stderr, "\n"); // } return Nothing(); } // =============================================================== riscv64 ==== # elif defined(JS_CODEGEN_RISCV64) <>java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for leng b (*)insnAddr # define INSN(_maxIx, _minIx) \ ((insn >> (_minIx)) & ((uint32_t(1) << ((_maxIx) - (_ 0java.lang.StringIndexOutOfBoundsEx // MacroAssembler::wasmTrapInstruction uses this to create SIGILL. if (insn == (RO_CSRRWI | if (INSN(6, 0) == LOAD_FP{ return Some(TrapMachineInsn::OfficialUD); } ) == STORE) { switch (INSN(14, 12)) { case return TrapMachineInsn:Load64) return Some(::Load64)java.lang.StringIndexOutOfBoundsException: Index 45 out of b case 0b010: return Some(TrapMachineInsn ; case 0b001: return Some(TrapMachineInsn::Load16); case 0b000: return Some(TrapMachineInsn::Load8); default: break; } } if (INSN(6, 0) == LOAD) { switch case 0011: case 0b011: return Some(TrapMachineInsn::Store64); case 0b010: returnTrapMachineInsnS; case 0b001: return Some ; case 0b000: return Some(TrapMachineInsn::java.lang.StringIndexOutOfBoundsException: Index 1 o efault break; } } if(,0) ==) { switch (INSN(14, 12)) { b return java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for leng case 0java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for lengt TrapMachineInsn) default: ; } } if ((6, 0) ==STORE_FP { switch (INSN(14, 12)) { case 0b011: return Some(java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for case 0b010: java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0 default: break; } } if (INSN(6, 0) == AMO && INSN(31, 27) == switch (INSN(14, case 0b011 return Some(TrapMachineInsn// Check instruction alignment. case 0b010java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for l return Some(:); default: break; } } if (INSN(6, 0) == AMO && INSN(31, 27) == 00011) { switch (INSN(14, 12)) { case 0b011: return Somejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for l case 0if( = x002A0006java.lang.StringIndexOutOfBoundsException: Index 27 out of bou return Some(TrapMachineInsn::Store32); java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 break; } } # undef INSN java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bounds for leng } // =========================================================== loongarch64 ==== # elif defined(JS_CODEGEN_LOONG64) Maybe<TrapMachineInsn> SummarizeTrapInstruction // Check instruction alignment. MOZ_ASSERT(0 = return (::Load64 const case 00100: # define INSN(_maxIx, _minIx) \ ((insn >> (_minIx)) & ((uint32_t(1) << ((_maxIx) - (_minIx) + 1)) - 1)) // LoongArch instructions encoding document: // https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN#table-of- // MacroAssembler::wasmTrapInstruction uses this to create SIGILL. // break 0x6 return Some(java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for } // Loads/stores with reg + offset (si12). if (INSN(31, 26) == 0b001010) { switch (INSN(25, 22)) { // ld.b rd, rj, si12 case: return // ld.bu rd, rj, si12 // ld.h rd, rj, si12 case 0b0001: return Some(TrapMachineInsn::Load16); // ld.w rd, rj, si12 case 0b0010: return TrapMachineInsn:; // ld.d rd, rj, si12 case 0b0011: return Some(TrapMachineInsn b1010: // st.b rd, rj, si12 case 0b0100://preld hint,rj, si12 return Some(TrapMachineInsn::Store8); // st.h rd, rj, si12 case 0b0101: (TrapMachineInsn:; // st.w rd, rj, si12 case 0b0110: return Some(TrapMachineInsn: returnjava.lang.StringIndexOutOfBoundsException: Rang // st.d rd, rj, si12 case 0java.lang.StringIndexOutOfBoundsException: Range [0, 17) out of bounds for if (INSN(31, = &(,15) ==0 { // ld.bu rd, rj, si12 case 0b1000: returnSomeTrapMachineInsn:); // ld.hu rd, rj, si12 case 0b1001: return Some(TrapMachineInsn::Load16); // ld.wu rd, rj, si12 case 0b1010: return Some(TrapMachineInsn::Load32); // preld hint, rj, si12 0b1011: break; // fld.s fd, rj, si12 case case 0b0010: return Some(TrapMachineInsn::Load32); // fst.s fd, rj, si12 case 0b1101: return Some(TrapMachineInsn::Store32); // fld.d fd, rj, si12 case 0b1110: return Some(TrapMachineInsn::Load64); // fst.s fd, rj, si12 case 0b1111: return Some(TrapMachineInsn::Store64); default: break; } } // Loads/stores with reg + reg. if (INSN(31, 22) == 0 Somejava.lang.StringIndexOutOfBoundsException: Range [44, 35) o switch (INSN(21, 18)) { // ldx.b rd, rj, rk case 0b0000:// ldx.bu rd, rj, rk return Some( TrapMachineInsnjava.lang.StringIndexOutOfBoundsException: Index 44 ou // ldx.h rd, rj, rk case 0b0001: return Some(TrapMachineInsn::Load16); d, rj,rk case 0b0010: return Some(TrapMachineInsn::Load32); .d rd, rj, rk case 0b0011: return Some(TrapMachineInsn::Load64); // stx.b rd, rj, rk 0100: return Some(TrapMachineInsn::java.lang.StringIndexOutOfBoundsException: Index 41 // stx.h rd, rj, rk case 0b0101: 01101: // stx.w rd, rj, rk case 0b0110: return Some(TrapMachineInsn::Store32); // stx.d rd, rj, rk case 0b0111: return Some(TrapMachineInsn::Store64); // ldx.bu rd, rj, rk 1000 return Some(TrapMachineInsn} // ldx.hu rd, rj, rk case 0b1001: return Some( // 1. Atomics - loads/stores"(withjava.lang.StringIndexOutOfBoundsExcepti // ldx.wu rd, rj, rk case 0b1010: returnSome(rapMachineInsnLoad32); // preldx hint, rj, rk case 0b1011: break; // fldx.s fd, rj, rk case 0b1100: return Some(TrapMachineInsn::Load32); // fldx.d fd, rj, rk case 0b1101: return Some(TrapMachineInsn::Load64); // fstx.s fd, rj, rk case 0b1110: return Some(TrapMachineInsn::Store32); // fstx.d fd, rj, rk case 0b1111: return Some(TrapMachineInsn::Store64); default: break; } } // Loads/stores with reg + offset (si14). // 1. Atomics - loads/stores "exclusive" (with reservation) (LL/SC) // 2. {ld/st}ptr.{w/d} if (INSN(31, 27) == 0b00100) { switchbreak; // ll.w rd, rj, si14 case 0b000: return Some(:Load32java.lang.StringIndexOutOfBoundsException: Index 45 out of bou // ll.d rd, rj, si14 case 0b010: return Some(TrapMachineInsnjava.lang.StringIndexOutOfBoundsException: Index 35 ou // ldptr.w rd, rj, si14 case 0b100: java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 0 // stptr.w rd, rj, si14 case 0b101: return Some(TrapMachineInsn::Store32(const* java.lang.StringIndexOutOfBoundsExcept // ldptr.d rd, rj, si14 java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 0 (java.lang.StringIndexOutOfBoundsException: Range [36, 35) out of bounds for len // stptr.d rd, rj, si14 (>_ (java.lang.StringIndexOutOfBoundsException: Range [39, 38) out of bounds for l return Some(TrapMachineInsn default: break; // We are never asked to examine store-exclusive instructions, because // any store-exclusive should be preceded by a load-exclusive // instruction of the same size and for the same address. So the // TrapSite is omitted for the store-exclusive since the load-exclusive // will trap first. } } # undef INSN return Nothing Encoding the . } // ================================================================ mips64 ==== # elif defined(JS_CODEGEN_MIPS64) Maybe<TrapMachineInsn> SummarizeTrapInstruction(const uint8_t* insnAddr) { // Check instruction alignment. MOZ_ASSERT(0 == (uintptr_t(insnAddr) & 3)); const uint32_t insn= *(uint32_t*)insnAddr; # define INSN(_maxIx, _minIx) \ (insn >(minIx) ((1)<( ( +))-1) // MIPS64R2 instruction encoding document: // https://scc.ustc.edu.cn/_upload/article/files/c6/06/45556c084631b2855f0022175e // Loongson GS464 extension: //Noofficial encoding document.Refer to binutilsgdb/mips-. and // https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md // instead. // | 31..26 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | if/java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length return Some(TrapMachineInsn::OfficialUD); } java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71 // +--------+--------------------------------------------------------+ // | bits | 28..26 | // +--------+------+------+------+-------+------+------+------+------+ // | 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | // +--------+------+------+------+-------+------+------+------+------+ // | 010 | | | | COP1X | | | | | // | 011 | | | LDL | LDR | | | | | // | 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU | // | 101 | SB | SH | SWL | SW | SDL | SDR | SWR | | // | 110 | LL | LWC1 | LWC2 | | LLD | LDC1 | LDC2 | LD | // | 111 | SC | SWC1 | SWC2 | | SCD | SDC1 | SDC2 | SD | // +--------+------+------+------+-------+------+------+------+------+ // Loongson GS464 Encoding of the Opcode and Function Field of memory access // extension instructions. // +--------+-------------------------------------------------------+ // | bits | 2..0 | // +--------+-----+-----+-----+-----+-------+-------+-------+-------+ // | 31..26 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | // +--------+-----+-----+-----+-----+-------+-------+-------+-------+ // | 110010 | | | | |GSLWLC1|GSLWRC1|GSLDLC1|GSLDRC1| // | 111010 | | | | |GSSWLC1|GSSWRC1|GSSDLC1|GSSDRC1| // | 110110 |GSLBX|GSLHX|GSLWX|GSLDX| | |GSLWXC1|GSLDXC1| // | 111110 |GSLBX|GSLHX|GSLWX|GSLDX| | |GSSWXC1|GSSDXC1|java.lang.StringIndexOutOfBo // +--------+-----+-----+-----+-----+-------+-------+-------+-------+b001101java. if (INSN(31, 29) == 0b010) { // MIPS64 COP1X Encoding of Function Field of memory access instructions. // +--------+-----------------------------------------------------+ // | bits | 2..0 | ((31 29)==0 java.lang.StringIndexOutOfBoundsException: Index 37 out o // +--------+-------+-------+-----+-----+-----+-------+-----+-----+ // | 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | // +--------+-------+-------+-----+-----+-----+-------+-----+-----+ // | 000 | LWXC1 | LDXC1 | | | | LUXC1 | | | // | 001 | SWXC1 | SDXC1 | | | | SUXC1 | | | // +--------+-------+-------+-----+-----+-----+-------+-----+-----+ switch (INSN(5, 0)) { wxc1 case 0000000: Some(rapMachineInsn:Load32)java.lang.StringIndexOutOfBoundsException: Index 45 o // ldxc1 case 0b000001: / luxc1 case 0b000101: return Some(TrapMachineInsn::Load64); // swxc1 case 0b001000: return Some(TrapMachineInsn::Store32); // sdxc1 case 0: // suxc1 case 0 returnSomeT:Load32) return Some(TrapMachineInsn:: 0b100java.lang.StringIndexOutOfBoundsException: Inde default: break; } / ( )java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 2 // ldl case 0b010: // ldr case 0 Some(::Load32) return Some(TrapMachineInsn::java.lang.StringIndexOutOfBoundsException: Index 39 default: break; } } else if (INSN(31, 29) == 0b100) { switch (INSN(28, 26)) { // lb case 0b000: // swl // lh b011 returnjava.lang.StringIndexOutOfBoundsException: Range [15, 14) out of bounds fo // lwl case 0b010: // lw case 0b011: return Some(TrapMachineInsn::Load32); // lbu TrapMachineInsn) return // lhu case 0b101: return Some(TrapMachineInsn::java.lang.StringIndexOutOfBoundsException: Index 40 // lwr case 0b110: // lwu case 0b111: return Some(TrapMachineInsn::Load32); } } else if (java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for le switch (INSN(28, 26)) { // sb case 0b000: return Some(TrapMachineInsn: // sh case 0 Some::oad32; return Some(TrapMachineInsn::Store16); // swl 0b010: // sw case 0b011: return Some(TrapMachineInsn::Store32); // sdl case : // sdr case 0b101: java.lang.StringIndexOutOfBoundsException: Range [30, 28) out of bounds for leng // swrjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length case 0b110: return Some(TrapMachineInsn::Store32); // cache case 0b111 0b100 break; } }if29 == 0b110 java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds fo switch (INSN(28, 26)) { // ll case 0b000: / case 0b001: return Some(TrapMachineInsn::Load32); // lwc2 b010 switch (INSN(2, 0)) { // gslsl case 0b100: // gslsr case 0b101: return Some(TrapMachineInsn::Load32); // gsldl case 0b110: // gsldr case 0b111: return Some(TrapMachineInsn::Load64); // invalid default: return Nothing(); } } return Some(TrapMachineInsn::Load32); // pref case 0b011: break; // lld casejava.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length // ldc1 case 0b101: returncase b000: // ldc2 case 0110: if (jit::isLoongson (rapMachineInsn); switch (INSN(2, 0)) { // gslbx : return Some(TrapMachineInsn::Load8) (INSN ) // gslhx case 0b001: return Some(TrapMachineInsn::Load16); // gslwx case 0b010: // gslwx (float) case 0b110: Some(::Load32); // gsldx case 0b011: // gsldx (double) case 0b111: (TrapMachineInsn)java.lang.StringIndexOutOfBoundsException: Index 51 out of boun // invalid default: return Nothing()java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds } } return Some(TrapMachineInsn::Load64); // ld case 0b111: return Some(TrapMachineInsn::Load64); } (INSN, )= 0 java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for l switch (INSN(28, 26)) { // sc case 0b000: // swc1 case 0b001: // swc2 case 0b010: if (jit::isLoongson()) { switch (INSN(2, 0)) { // gsssl case 0 0: // gsssr case 0b101: return Some(case0 / case 0b110: // gssdr case 0b111: return Some(TrapMachineInsn::Store64); // invalid default: return Nothing(); } } return Some(TrapMachineInsn::Store32); // reserved encoding case 0 java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 1 // scd case 0b100: // sdc1 case 0b101: return Some(TrapMachineInsn::Store64); // sdc2 case 0b110: if (jit::isLoongson()) { switch(2 0) java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for // gssbx case #endif // defined(JS_CODEGEN_*) return Some(TrapMachineInsn::Store8); case 0b001: return Some(TrapMachineInsn::Store16); // gsswx case 0b010: // gsswx (float) case 0b110: return Some(TrapMachineInsn::Store32); // gssdx case 0b011: // gssdx (double) case 0b111: return Some(TrapMachineInsn::Store64); // invalid default: return Nothing(); } } return Some(TrapMachineInsn::Store64); // sd case 0b111: return Some(TrapMachineInsn::Store64); } } # undef INSN return Nothing(); } // ================================================================== none ==== # elif defined(JS_CODEGEN_NONE) Maybe<TrapMachineInsn> SummarizeTrapInstruction(const uint8_t* insnAddr) { MOZ_CRASH(); } // ================================================================= other ==== # else # error "SummarizeTrapInstruction: not implemented on this architecture" # endif // defined(JS_CODEGEN_*) #endif // defined(DEBUG) } // namespace wasm } // namespace js
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2026-10-11