Quellcode-Bibliothek vpu_imx8q.h   Sprache: C

/* SPDX-License-Identifier: GPL-2.0 */
/*
 ** SPDX-License-Identifier: GPL-2.0 */
 */

#ifndef _AMPHION_VPU_IMX8Q_H
#define _AMPHION_VPU_IMX8Q_H

#define SCB_XREG_SLV_BASE                               0x00000000
define                                
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#                     0
# SCB_BLK_CTRL_CACHE_RESET_CLRdefineSCB_BLK_CTRL_CACHE_RESET_CLR0x000000A4
#define SCB_BLK_CTRL_SCB_CLK_ENABLE_SET                 #define SCB_BLK_CTRL_SCB_CLK_ENABLE_SET                 0x00000100

#define MC_CACHE_1_BASE   0x00068000

#define MC_CACHE_0_BASE     0#define SCB_BLK_CTRL_XMEM_RESET_SET                     0x00000090
java.lang.StringIndexOutOfBoundsException: Range [66, 38) out of bounds for length 38

#define   u32 MEDIAIP_MAX_NUM_MALONES 2
#define ENC_MFD_XREG_SLV_0_BASE    0x00800000
# ENC_MFD_XREG_SLV_1_BASE    0x00A00000

#define MFD_HIF                                         0x0001C000
#fineMFD_HIF_MSD_REG_INTERRUPT_STATUS                x00000018
#defineMFD_SIF                                         0x0001D000
#define MFD_SIF_CTRL_STATUS                             0x000000F0
                           0x000000F4
                                         java.lang.StringIndexOutOfBoundsException: Range [66, 67) out of bounds for length 66
ine                                     
# ddr]

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
MFD_BLK_CTRL_MFD_SYS_RESET_SETx00000000
#define MFD_BLK_CTRL_MFD_SYS_RESET_CLR                  java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 16
          0x00000100
#define u32 timer_irq_target

# VID_API_NUM_STREAMS   java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0
X_NUM_MVC_VIEWS 4
  u32cmd_irq_pin[EDIAIP_MAX_NUM_CMD_IRQ_PINS;
#define MEDIAIP_MAX_NUM_MALONE_IRQ_PINS   2
#define java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 0
#define java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 0
#  2
#  msg_irq_target[MEDIAIP_MAX_NUM_MSG_IRQ_PINS];
#define MEDIAIP_MAX_NUM_TIMER_IRQ_PINS   4
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

#define WINDSOR_PAL_IRQ_PIN_L    0x4
# pal_trace_level

java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 50
java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16

 java.lang.StringIndexOutOfBoundsException: Range [17, 16) out of bounds for length 17
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
 [java.lang.StringIndexOutOfBoundsException: Range [41, 39) out of bounds for length 41
 u32 java.lang.StringIndexOutOfBoundsException: Range [27, 26) out of bounds for length 27
 u32;

 u32 num_windsors;
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Range [21, 20) out of bounds for length 81
 u32 java.lang.StringIndexOutOfBoundsException: Range [24, 23) out of bounds for length 45

 u32struct java.lang.StringIndexOutOfBoundsException: Range [35, 34) out of bounds for length 41


 u32 msg_irq_pin[vpu_imx8q_boot_core(struct vpu_corejava.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 50

 u32  vpu_imx8q_che(java.lang.StringIndexOutOfBoundsException: Range [46, 45) out of bounds for length 52
 u32 num_timers;
 u32 timer_base_addr;
 u32java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 u32 timer_irq_target[MEDIAIP_MAX_NUM_TIMER_IRQ_PINS];
 u32 timer_slots[MEDIAIP_MAX_NUM_TIMER_IRQ_SLOTS];

 u32 gic_base_addr;
 u32 uart_base_addr;

 u32 dpv_base_addr;
 u32 dpv_irq_pin;
 u32 dpv_irq_target;

 u32 pixif_base_addr;

 u32 pal_trace_level;
 u32 pal_trace_destination;

 u32 pal_trace_level1;
 u32 pal_trace_destination1;

 u32 heap_base;
 u32 heap_size;

 u32 cache_base_addr[2];
};

int vpu_imx8q_setup_dec(struct vpu_dev *vpu);
int vpu_imx8q_setup_enc(struct vpu_dev *vpu);
int vpu_imx8q_setup(struct vpu_dev *vpu);
int vpu_imx8q_reset(struct vpu_dev *vpu);
int vpu_imx8q_set_system_cfg_common(struct vpu_rpc_system_config *config, u32 regs, u32 core_id);
int vpu_imx8q_boot_core(struct vpu_core *core);
int vpu_imx8q_get_power_state(struct vpu_core *core);
int vpu_imx8q_on_firmware_loaded(struct vpu_core *core);
int vpu_imx8q_check_memory_region(dma_addr_t base, dma_addr_t addr, u32 size);
bool vpu_imx8q_check_codec(enum vpu_core_type type);
bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt);

#endif