| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/arch/arm64/boot/dts/hisilicon/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 31 kB |
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Quelle hi3660.dtsi Sprache: unbekannt |
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// SPDX-License-Identifier: GPL-2.0
/* * dts file for Hisilicon Hi3660 SoC * * Copyright (C) 2016, HiSilicon Ltd. */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/hi3660-clock.h> #include <dt-bindings/thermal/thermal.h> / { compatible = "hisilicon,hi3660"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; psci { compatible = "arm,psci-0.2"; method = "smc"; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; }; cluster1 { core0 { cpu = <&cpu4>; }; core1 { cpu = <&cpu5>; }; core2 { cpu = <&cpu6>; }; core3 { cpu = <&cpu7>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; dynamic-power-coefficient = <110>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A53_L2>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <592>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; }; cpu4: cpu@100 { compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; dynamic-power-coefficient = <550>; }; cpu5: cpu@101 { compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; }; cpu6: cpu@102 { compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; }; cpu7: cpu@103 { compatible = "arm,cortex-a73"; device_type = "cpu"; reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&A73_L2>; cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x0010000>; entry-latency-us = <400>; exit-latency-us = <650>; min-residency-us = <1500>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x1010000>; entry-latency-us = <500>; exit-latency-us = <1600>; min-residency-us = <3500>; }; CPU_SLEEP_1: cpu-sleep-1 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x0010000>; entry-latency-us = <400>; exit-latency-us = <550>; min-residency-us = <1500>; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x1010000>; entry-latency-us = <800>; exit-latency-us = <2900>; min-residency-us = <3500>; }; }; A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; }; A73_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; cache-unified; }; }; cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <533000000>; opp-microvolt = <700000>; clock-latency-ns = <300000>; }; opp01 { opp-hz = /bits/ 64 <999000000>; opp-microvolt = <800000>; clock-latency-ns = <300000>; }; opp02 { opp-hz = /bits/ 64 <1402000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; }; opp03 { opp-hz = /bits/ 64 <1709000000>; opp-microvolt = <1000000>; clock-latency-ns = <300000>; }; opp04 { opp-hz = /bits/ 64 <1844000000>; opp-microvolt = <1100000>; clock-latency-ns = <300000>; }; }; cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp10 { opp-hz = /bits/ 64 <903000000>; opp-microvolt = <700000>; clock-latency-ns = <300000>; }; opp11 { opp-hz = /bits/ 64 <1421000000>; opp-microvolt = <800000>; clock-latency-ns = <300000>; }; opp12 { opp-hz = /bits/ 64 <1805000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; }; opp13 { opp-hz = /bits/ 64 <2112000000>; opp-microvolt = <1000000>; clock-latency-ns = <300000>; }; opp14 { opp-hz = /bits/ 64 <2362000000>; opp-microvolt = <1100000>; clock-latency-ns = <300000>; }; }; gic: interrupt-controller@e82b0000 { compatible = "arm,gic-400"; reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ <0x0 0xe82b2000 0 0x2000>, /* GICC */ <0x0 0xe82b4000 0 0x2000>, /* GICH */ <0x0 0xe82b6000 0 0x2000>; /* GICV */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; a53-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; a73-pmu { compatible = "arm,cortex-a73-pmu"; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; crg_ctrl: crg_ctrl@fff35000 { compatible = "hisilicon,hi3660-crgctrl", "syscon"; reg = <0x0 0xfff35000 0x0 0x1000>; #clock-cells = <1>; }; crg_rst: crg_rst_controller { compatible = "hisilicon,hi3660-reset"; #reset-cells = <2>; hisi,rst-syscon = <&crg_ctrl>; }; pctrl: pctrl@e8a09000 { compatible = "hisilicon,hi3660-pctrl", "syscon"; reg = <0x0 0xe8a09000 0x0 0x2000>; #clock-cells = <1>; }; pmuctrl: crg_ctrl@fff34000 { compatible = "hisilicon,hi3660-pmuctrl", "syscon"; reg = <0x0 0xfff34000 0x0 0x1000>; #clock-cells = <1>; }; sctrl: sctrl@fff0a000 { compatible = "hisilicon,hi3660-sctrl", "syscon"; reg = <0x0 0xfff0a000 0x0 0x1000>; #clock-cells = <1>; }; iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3660-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; #clock-cells = <1>; }; iomcu_rst: reset { compatible = "hisilicon,hi3660-reset"; hisi,rst-syscon = <&iomcu>; #reset-cells = <2>; }; mailbox: mailbox@e896b000 { compatible = "hisilicon,hi3660-mbox"; reg = <0x0 0xe896b000 0x0 0x1000>; interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <3>; }; stub_clock: stub_clock@e896b500 { compatible = "hisilicon,hi3660-stub-clk"; reg = <0x0 0xe896b500 0x0 0x0100>; #clock-cells = <1>; mboxes = <&mailbox 13 3 0>; }; dual_timer0: timer@fff14000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xfff14000 0x0 0x1000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_OSC32K>, <&crg_ctrl HI3660_OSC32K>, <&crg_ctrl HI3660_OSC32K>; clock-names = "timer1", "timer2", "apb_pclk"; }; i2c0: i2c@ffd71000 { compatible = "snps,designware-i2c"; reg = <0x0 0xffd71000 0x0 0x1000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; resets = <&iomcu_rst 0x20 3>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; status = "disabled"; }; i2c1: i2c@ffd72000 { compatible = "snps,designware-i2c"; reg = <0x0 0xffd72000 0x0 0x1000>; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; resets = <&iomcu_rst 0x20 4>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; status = "disabled"; }; i2c3: i2c@fdf0c000 { compatible = "snps,designware-i2c"; reg = <0x0 0xfdf0c000 0x0 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; resets = <&crg_rst 0x78 7>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; status = "disabled"; }; i2c7: i2c@fdf0b000 { compatible = "snps,designware-i2c"; reg = <0x0 0xfdf0b000 0x0 0x1000>; interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; resets = <&crg_rst 0x60 14>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; status = "disabled"; }; uart0: serial@fdf02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf02000 0x0 0x1000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; status = "disabled"; }; uart1: serial@fdf00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf00000 0x0 0x1000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; dmas = <&dma0 2 &dma0 3>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, <&crg_ctrl HI3660_CLK_GATE_UART1>; clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; status = "disabled"; }; uart2: serial@fdf03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf03000 0x0 0x1000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; dmas = <&dma0 4 &dma0 5>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; status = "disabled"; }; uart3: serial@ffd74000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xffd74000 0x0 0x1000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_FACTOR_UART3>, <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; status = "disabled"; }; uart4: serial@fdf01000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf01000 0x0 0x1000>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; dmas = <&dma0 6 &dma0 7>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, <&crg_ctrl HI3660_CLK_GATE_UART4>; clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; status = "disabled"; }; uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; dma-names = "rx", "tx"; dmas = <&dma0 8 &dma0 9>; clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; status = "disabled"; }; uart6: serial@fff32000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfff32000 0x0 0x1000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_UART6>, <&crg_ctrl HI3660_PCLK>; clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; status = "disabled"; }; dma0: dma@fdf30000 { compatible = "hisilicon,k3-dma-1.0"; reg = <0x0 0xfdf30000 0x0 0x1000>; #dma-cells = <1>; dma-channels = <16>; dma-requests = <32>; dma-channel-mask = <0xfffe>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; dma-no-cci; dma-type = "hi3660_dma"; }; asp_dmac: dma-controller@e804b000 { compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; reg = <0x0 0xe804b000 0x0 0x1000>; #dma-cells = <1>; dma-channels = <16>; dma-requests = <32>; interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "asp_dma_irq"; }; rtc0: rtc@fff04000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x0 0Xfff04000 0x0 0x1000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; }; gpio0: gpio@e8a0b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0b000 0 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 1 0 7>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; clock-names = "apb_pclk"; }; gpio1: gpio@e8a0c000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0c000 0 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 1 7 7>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; clock-names = "apb_pclk"; }; gpio2: gpio@e8a0d000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0d000 0 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 14 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; clock-names = "apb_pclk"; }; gpio3: gpio@e8a0e000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0e000 0 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 22 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; clock-names = "apb_pclk"; }; gpio4: gpio@e8a0f000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0f000 0 0x1000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 30 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; clock-names = "apb_pclk"; }; gpio5: gpio@e8a10000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a10000 0 0x1000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 38 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; clock-names = "apb_pclk"; }; gpio6: gpio@e8a11000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a11000 0 0x1000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 46 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; clock-names = "apb_pclk"; }; gpio7: gpio@e8a12000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a12000 0 0x1000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 54 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; clock-names = "apb_pclk"; }; gpio8: gpio@e8a13000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a13000 0 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 62 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; clock-names = "apb_pclk"; }; gpio9: gpio@e8a14000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a14000 0 0x1000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 70 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; clock-names = "apb_pclk"; }; gpio10: gpio@e8a15000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a15000 0 0x1000>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 78 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; clock-names = "apb_pclk"; }; gpio11: gpio@e8a16000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a16000 0 0x1000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 86 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; clock-names = "apb_pclk"; }; gpio12: gpio@e8a17000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a17000 0 0x1000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; clock-names = "apb_pclk"; }; gpio13: gpio@e8a18000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a18000 0 0x1000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 102 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; clock-names = "apb_pclk"; }; gpio14: gpio@e8a19000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a19000 0 0x1000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 110 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; clock-names = "apb_pclk"; }; gpio15: gpio@e8a1a000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a1a000 0 0x1000>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx0 0 118 6>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; clock-names = "apb_pclk"; }; gpio16: gpio@e8a1b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a1b000 0 0x1000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; clock-names = "apb_pclk"; }; gpio17: gpio@e8a1c000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a1c000 0 0x1000>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; clock-names = "apb_pclk"; }; gpio18: gpio@ff3b4000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xff3b4000 0 0x1000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx2 0 0 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; clock-names = "apb_pclk"; }; gpio19: gpio@ff3b5000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xff3b5000 0 0x1000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx2 0 8 4>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; clock-names = "apb_pclk"; }; gpio20: gpio@e8a1f000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a1f000 0 0x1000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pmx1 0 0 6>; interrupt-controller; #interrupt-cells = <2>; clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; clock-names = "apb_pclk"; }; gpio21: gpio@e8a20000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a20000 0 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&pmx3 0 0 6>; clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; clock-names = "apb_pclk"; }; gpio22: gpio@fff0b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xfff0b000 0 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; /* GPIO176 */ gpio-ranges = <&pmx4 2 0 6>; interrupt-controller; #interrupt-cells = <2>; clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; clock-names = "apb_pclk"; }; gpio23: gpio@fff0c000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xfff0c000 0 0x1000>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; /* GPIO184 */ gpio-ranges = <&pmx4 0 6 7>; interrupt-controller; #interrupt-cells = <2>; clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; clock-names = "apb_pclk"; }; gpio24: gpio@fff0d000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xfff0d000 0 0x1000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; /* GPIO192 */ gpio-ranges = <&pmx4 0 13 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; clock-names = "apb_pclk"; }; gpio25: gpio@fff0e000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xfff0e000 0 0x1000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; /* GPIO200 */ gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; interrupt-controller; #interrupt-cells = <2>; clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; clock-names = "apb_pclk"; }; gpio26: gpio@fff0f000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xfff0f000 0 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; /* GPIO208 */ gpio-ranges = <&pmx4 0 28 8>; interrupt-controller; #interrupt-cells = <2>; clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; clock-names = "apb_pclk"; }; gpio27: gpio@fff10000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xfff10000 0 0x1000>; interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; /* GPIO216 */ gpio-ranges = <&pmx4 0 36 6>; interrupt-controller; #interrupt-cells = <2>; clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; clock-names = "apb_pclk"; }; gpio28: gpio@fff1d000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xfff1d000 0 0x1000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; clock-names = "apb_pclk"; }; spi2: spi@ffd68000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xffd68000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; num-cs = <1>; cs-gpios = <&gpio27 2 0>; status = "disabled"; }; spi3: spi@ff3b3000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xff3b3000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; num-cs = <1>; cs-gpios = <&gpio18 5 0>; status = "disabled"; }; pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xf5000000 0x0 0x2000>; reg-names = "dbi", "apb", "phy", "config"; bus-range = <0x0 0xff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>; num-lanes = <1>; #interrupt-cells = <1>; interrupts = <0 283 4>; interrupt-names = "msi"; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, <&crg_ctrl HI3660_ACLK_GATE_PCIE>; clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; reset-gpios = <&gpio11 1 0 >; }; /* UFS */ ufs: ufs@ff3b0000 { compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; /* 0: HCI standard */ /* 1: UFS SYS CTRL */ reg = <0x0 0xff3b0000 0x0 0x1000>, <0x0 0xff3b1000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; freq-table-hz = <0 0>, <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; }; /* SD */ dwmmc1: dwmmc1@ff37f000 { compatible = "hisilicon,hi3660-dw-mshc"; reg = <0x0 0xff37f000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, <&crg_ctrl HI3660_HCLK_GATE_SD>; clock-names = "ciu", "biu"; clock-frequency = <3200000>; resets = <&crg_rst 0x94 18>; reset-names = "reset"; hisilicon,peripheral-syscon = <&sctrl>; card-detect-delay = <200>; status = "disabled"; }; /* SDIO */ dwmmc2: dwmmc2@ff3ff000 { compatible = "hisilicon,hi3660-dw-mshc"; reg = <0x0 0xff3ff000 0x0 0x1000>; #address-cells = <0x1>; #size-cells = <0x0>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; clock-names = "ciu", "biu"; resets = <&crg_rst 0x94 20>; reset-names = "reset"; card-detect-delay = <200>; status = "disabled"; }; watchdog0: watchdog@e8a06000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a06000 0x0 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_OSC32K>, <&crg_ctrl HI3660_OSC32K>; clock-names = "wdog_clk", "apb_pclk"; }; watchdog1: watchdog@e8a07000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a07000 0x0 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_OSC32K>, <&crg_ctrl HI3660_OSC32K>; clock-names = "wdog_clk", "apb_pclk"; }; tsensor: tsensor@fff30000 { compatible = "hisilicon,hi3660-tsensor"; reg = <0x0 0xfff30000 0x0 0x1000>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; #thermal-sensor-cells = <1>; }; thermal-zones { cls0: cls0-thermal { polling-delay = <1000>; polling-delay-passive = <100>; sustainable-power = <4500>; /* sensor ID */ thermal-sensors = <&tsensor 1>; trips { threshold: trip-point0 { temperature = <65000>; hysteresis = <1000>; type = "passive"; }; target: trip-point1 { temperature = <75000>; hysteresis = <1000>; type = "passive"; }; }; cooling-maps { map0 { trip = <&target>; contribution = <1024>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&target>; contribution = <512>; cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; usb3_otg_bc: usb3_otg_bc@ff200000 { compatible = "hisilicon,hi3660-usb3-otg-bc", "syscon", "simple-mfd"; reg = <0x0 0xff200000 0x0 0x1000>; usb_phy: usb-phy { compatible = "hisilicon,hi3660-usb-phy"; #phy-cells = <0>; hisilicon,pericrg-syscon = <&crg_ctrl>; hisilicon,pctrl-syscon = <&pctrl>; hisilicon,eye-diagram-param = <0x22466e4>; }; }; dwc3: usb@ff100000 { compatible = "snps,dwc3"; reg = <0x0 0xff100000 0x0 0x100000>; clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; clock-names = "ref", "bus_early"; assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; assigned-clock-rates = <229000000>; resets = <&crg_rst 0x90 8>, <&crg_rst 0x90 7>, <&crg_rst 0x90 6>, <&crg_rst 0x90 5>; interrupts = <0 159 4>, <0 161 4>; phys = <&usb_phy>; phy-names = "usb3-phy"; }; }; }; #include "hi3660-coresight.dtsi" [ Dauer der Verarbeitung: 0.18 Sekunden (vorverarbeitet) ] |
2026-04-07