| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/arch/arm64/boot/dts/qcom/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 166 kB |
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Quelle sc8280xp.dtsi Sprache: unbekannt |
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Spracherkennung für: .dtsi vermutete Sprache: Unknown {[0] [0] [0]} [Methode: Schwerpunktbildung, einfache Gewichte, sechs Dimensionen] // SPDX-License-Identifier: BSD-3-Clause
/* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Linaro Limited */ #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sc8280xp-camcc.h> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc8280xp.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; clocks { xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32764>; }; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <981>; dynamic-power-coefficient = <549>; next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; }; }; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <981>; dynamic-power-coefficient = <549>; next-level-cache = <&l2_100>; power-domains = <&cpu_pd1>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_100: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <981>; dynamic-power-coefficient = <549>; next-level-cache = <&l2_200>; power-domains = <&cpu_pd2>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_200: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a78c"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <981>; dynamic-power-coefficient = <549>; next-level-cache = <&l2_300>; power-domains = <&cpu_pd3>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_300: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-x1c"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <590>; next-level-cache = <&l2_400>; power-domains = <&cpu_pd4>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_400: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-x1c"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <590>; next-level-cache = <&l2_500>; power-domains = <&cpu_pd5>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_500: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-x1c"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <590>; next-level-cache = <&l2_600>; power-domains = <&cpu_pd6>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_600: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-x1c"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <590>; next-level-cache = <&l2_700>; power-domains = <&cpu_pd7>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; l2_700: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; core4 { cpu = <&cpu4>; }; core5 { cpu = <&cpu5>; }; core6 { cpu = <&cpu6>; }; core7 { cpu = <&cpu7>; }; }; }; idle-states { entry-method = "psci"; little_cpu_sleep_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "little-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <355>; exit-latency-us = <909>; min-residency-us = <3934>; local-timer-stop; }; big_cpu_sleep_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "big-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <241>; exit-latency-us = <1461>; min-residency-us = <4488>; local-timer-stop; }; }; domain-idle-states { cluster_sleep_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; }; }; }; firmware { scm: scm { compatible = "qcom,scm-sc8280xp", "qcom,scm"; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; qcom,dload-mode = <&tcsr 0x13000>; }; }; aggre1_noc: interconnect-aggre1-noc { compatible = "qcom,sc8280xp-aggre1-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect-aggre2-noc { compatible = "qcom,sc8280xp-aggre2-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; clk_virt: interconnect-clk-virt { compatible = "qcom,sc8280xp-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; config_noc: interconnect-config-noc { compatible = "qcom,sc8280xp-config-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; dc_noc: interconnect-dc-noc { compatible = "qcom,sc8280xp-dc-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect-gem-noc { compatible = "qcom,sc8280xp-gem-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; lpass_noc: interconnect-lpass-ag-noc { compatible = "qcom,sc8280xp-lpass-ag-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect-mc-virt { compatible = "qcom,sc8280xp-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect-mmss-noc { compatible = "qcom,sc8280xp-mmss-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; nspa_noc: interconnect-nspa-noc { compatible = "qcom,sc8280xp-nspa-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; nspb_noc: interconnect-nspb-noc { compatible = "qcom,sc8280xp-nspb-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect-system-noc { compatible = "qcom,sc8280xp-system-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0x0 0x80000000 0x0 0x0>; }; cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-peak-kBps = <(300000 * 32)>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; opp-peak-kBps = <(384000 * 32)>; }; opp-499200000 { opp-hz = /bits/ 64 <499200000>; opp-peak-kBps = <(480000 * 32)>; }; opp-595200000 { opp-hz = /bits/ 64 <595200000>; opp-peak-kBps = <(576000 * 32)>; }; opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-peak-kBps = <(672000 * 32)>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; opp-peak-kBps = <(768000 * 32)>; }; opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-peak-kBps = <(864000 * 32)>; }; opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; opp-peak-kBps = <(960000 * 32)>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-peak-kBps = <(1075200 * 32)>; }; opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-peak-kBps = <(1171200 * 32)>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-peak-kBps = <(1267200 * 32)>; }; opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-peak-kBps = <(1363200 * 32)>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; opp-peak-kBps = <(1536000 * 32)>; }; opp-1670400000 { opp-hz = /bits/ 64 <1670400000>; opp-peak-kBps = <(1612800 * 32)>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-1881600000 { opp-hz = /bits/ 64 <1881600000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2227200000 { opp-hz = /bits/ 64 <2227200000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2342400000 { opp-hz = /bits/ 64 <2342400000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2438400000 { opp-hz = /bits/ 64 <2438400000>; opp-peak-kBps = <(1689600 * 32)>; }; }; cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-peak-kBps = <(768000 * 32)>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-peak-kBps = <(864000 * 32)>; }; opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-peak-kBps = <(960000 * 32)>; }; opp-1171200000 { opp-hz = /bits/ 64 <1171200000>; opp-peak-kBps = <(1171200 * 32)>; }; opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-peak-kBps = <(1267200 * 32)>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-peak-kBps = <(1363200 * 32)>; }; opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-peak-kBps = <(1459200 * 32)>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; opp-peak-kBps = <(1612800 * 32)>; }; opp-1747200000 { opp-hz = /bits/ 64 <1747200000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-1862400000 { opp-hz = /bits/ 64 <1862400000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-1977600000 { opp-hz = /bits/ 64 <1977600000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2169600000 { opp-hz = /bits/ 64 <2169600000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2284800000 { opp-hz = /bits/ 64 <2284800000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2496000000 { opp-hz = /bits/ 64 <2496000000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2592000000 { opp-hz = /bits/ 64 <2592000000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2688000000 { opp-hz = /bits/ 64 <2688000000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2803200000 { opp-hz = /bits/ 64 <2803200000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2899200000 { opp-hz = /bits/ 64 <2899200000>; opp-peak-kBps = <(1689600 * 32)>; }; opp-2995200000 { opp-hz = /bits/ 64 <2995200000>; opp-peak-kBps = <(1689600 * 32)>; }; }; qup_opp_table_100mhz: opp-table-qup100mhz { compatible = "operating-points-v2"; opp-75000000 { opp-hz = /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&cluster_sleep_0>; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; reserved-region@80000000 { reg = <0 0x80000000 0 0x860000>; no-map; }; cmd_db: cmd-db-region@80860000 { compatible = "qcom,cmd-db"; reg = <0 0x80860000 0 0x20000>; no-map; }; reserved-region@80880000 { reg = <0 0x80880000 0 0x80000>; no-map; }; smem_mem: smem-region@80900000 { compatible = "qcom,smem"; reg = <0 0x80900000 0 0x200000>; no-map; hwlocks = <&tcsr_mutex 3>; }; reserved-region@80b00000 { reg = <0 0x80b00000 0 0x100000>; no-map; }; reserved-region@83b00000 { reg = <0 0x83b00000 0 0x1700000>; no-map; }; reserved-region@85b00000 { reg = <0 0x85b00000 0 0xc00000>; no-map; }; pil_adsp_mem: adsp-region@86c00000 { reg = <0 0x86c00000 0 0x2000000>; no-map; }; pil_slpi_mem: slpi-region@88c00000 { reg = <0 0x88c00000 0 0x1500000>; no-map; }; pil_nsp0_mem: cdsp0-region@8a100000 { reg = <0 0x8a100000 0 0x1e00000>; no-map; }; pil_nsp1_mem: cdsp1-region@8c600000 { reg = <0 0x8c600000 0 0x1e00000>; no-map; }; reserved-region@aeb00000 { reg = <0 0xaeb00000 0 0x16600000>; no-map; }; }; smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; smp2p_adsp_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_adsp_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-nsp0 { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; smp2p_nsp0_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_nsp0_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-nsp1 { compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <12>; smp2p_nsp1_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_nsp1_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-slpi { compatible = "qcom,smp2p"; qcom,smem = <481>, <430>; interrupts-extended = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <3>; smp2p_slpi_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; smp2p_slpi_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; soc: soc@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; ethernet0: ethernet@20000 { compatible = "qcom,sc8280xp-ethqos"; reg = <0x0 0x00020000 0x0 0x10000>, <0x0 0x00036000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>, <&gcc GCC_EMAC0_PTP_CLK>, <&gcc GCC_EMAC0_RGMII_CLK>; clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; iommus = <&apps_smmu 0x4c0 0xf>; power-domains = <&gcc EMAC_0_GDSC>; snps,tso; snps,pbl = <32>; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; status = "disabled"; }; gcc: clock-controller@100000 { compatible = "qcom,gcc-sc8280xp"; reg = <0x0 0x00100000 0x0 0x1f0000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>, <0>, <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <&pcie2a_phy>, <&pcie2b_phy>, <&pcie3a_phy>, <&pcie3b_phy>, <&pcie4_phy>, <0>, <0>; power-domains = <&rpmhpd SC8280XP_CX>; }; ipcc: mailbox@408000 { compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; }; qfprom: efuse@784000 { compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x3000>; #address-cells = <1>; #size-cells = <1>; gpu_speed_bin: gpu-speed-bin@18b { reg = <0x18b 0x1>; bits = <5 3>; }; }; qup2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0xa3 0>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c16: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi16: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c17: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi17: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; uart17: serial@884000 { compatible = "qcom,geni-uart"; reg = <0 0x00884000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; operating-points-v2 = <&qup_opp_table_100mhz>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c18: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi18: spi@888000 { compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; uart18: serial@888000 { compatible = "qcom,geni-uart"; reg = <0 0x00888000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; operating-points-v2 = <&qup_opp_table_100mhz>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; interconnect-names = "qup-core", "qup-config"; pinctrl-0 = <&qup_uart18_default>; pinctrl-names = "default"; status = "disabled"; }; i2c19: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi19: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c20: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi20: spi@890000 { compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c21: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi21: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c22: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0 0x00898000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi22: spi@898000 { compatible = "qcom,geni-spi"; reg = <0 0x00898000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c23: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0089c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi23: spi@89c000 { compatible = "qcom,geni-spi"; reg = <0 0x0089c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; clock-names = "se"; interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; }; qup0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x6000>; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0x563 0>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c0: i2c@980000 { compatible = "qcom,geni-i2c"; reg = <0 0x00980000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi0: spi@980000 { compatible = "qcom,geni-spi"; reg = <0 0x00980000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0 0x00984000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi1: spi@984000 { compatible = "qcom,geni-spi"; reg = <0 0x00984000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0 0x00988000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi2: spi@988000 { compatible = "qcom,geni-spi"; reg = <0 0x00988000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; uart2: serial@988000 { compatible = "qcom,geni-uart"; reg = <0 0x00988000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; operating-points-v2 = <&qup_opp_table_100mhz>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi3: spi@98c000 { compatible = "qcom,geni-spi"; reg = <0 0x0098c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0 0x00990000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi4: spi@990000 { compatible = "qcom,geni-spi"; reg = <0 0x00990000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0 0x00994000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi5: spi@994000 { compatible = "qcom,geni-spi"; reg = <0 0x00994000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c6: i2c@998000 { compatible = "qcom,geni-i2c"; reg = <0 0x00998000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi6: spi@998000 { compatible = "qcom,geni-spi"; reg = <0 0x00998000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c7: i2c@99c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0099c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi7: spi@99c000 { compatible = "qcom,geni-spi"; reg = <0 0x0099c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; }; qup1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0x83 0>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; i2c8: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi8: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi9: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi10: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi11: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi12: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi13: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c14: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi14: spi@a98000 { compatible = "qcom,geni-spi"; reg = <0 0x00a98000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; spi15: spi@a9c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a9c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC8280XP_CX>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; }; rng: rng@10d3000 { compatible = "qcom,prng-ee"; reg = <0 0x010d3000 0 0x1000>; clocks = <&rpmhcc RPMH_HWKM_CLK>; clock-names = "core"; }; pcie4: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sc8280xp"; reg = <0x0 0x01c00000 0x0 0x3000>, <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, <0x0 0x30100000 0x0 0x100000>, <0x0 0x01c03000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <6>; num-lanes = <1>; msi-map = <0x0 &its 0xe0000 0x10000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, <&gcc GCC_PCIE_4_SLV_AXI_CLK>, <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, <&gcc GCC_CNOC_PCIE4_QX_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", "noc_aggr_4", "noc_aggr_south_sf", "cnoc_qx"; assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_4_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_4_GDSC>; required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; phy-names = "pciephy"; status = "disabled"; pcie4_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie4_phy: phy@1c06000 { compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; reg = <0x0 0x01c06000 0x0 0x2000>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, <&gcc GCC_PCIE_4_CLKREF_CLK>, <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_4_PIPE_CLK>, <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; power-domains = <&gcc PCIE_4_GDSC>; resets = <&gcc GCC_PCIE_4_PHY_BCR>; reset-names = "phy"; #clock-cells = <0>; clock-output-names = "pcie_4_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; pcie3b: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-sc8280xp"; reg = <0x0 0x01c08000 0x0 0x3000>, <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, <0x0 0x32100000 0x0 0x100000>, <0x0 0x01c0b000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <5>; num-lanes = <2>; msi-map = <0x0 &its 0xd0000 0x10000>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", "noc_aggr_4", "noc_aggr_south_sf"; assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_3B_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_3B_GDSC>; required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3b_phy>; phy-names = "pciephy"; status = "disabled"; pcie3b_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie3b_phy: phy@1c0e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3B_PIPE_CLK>, <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; power-domains = <&gcc PCIE_3B_GDSC>; resets = <&gcc GCC_PCIE_3B_PHY_BCR>; reset-names = "phy"; #clock-cells = <0>; clock-output-names = "pcie_3b_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; pcie3a: pcie@1c10000 { device_type = "pci"; compatible = "qcom,pcie-sc8280xp"; reg = <0x0 0x01c10000 0x0 0x3000>, <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, <0x0 0x34100000 0x0 0x100000>, <0x0 0x01c13000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <4>; num-lanes = <4>; msi-map = <0x0 &its 0xc0000 0x10000>; interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", "noc_aggr_4", "noc_aggr_south_sf"; assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_3A_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_3A_GDSC>; required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3a_phy>; phy-names = "pciephy"; status = "disabled"; pcie3a_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie3a_phy: phy@1c14000 { compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; reg = <0x0 0x01c14000 0x0 0x2000>, <0x0 0x01c16000 0x0 0x2000>; clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_3A_PIPE_CLK>, <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; power-domains = <&gcc PCIE_3A_GDSC>; resets = <&gcc GCC_PCIE_3A_PHY_BCR>; reset-names = "phy"; qcom,4ln-config-sel = <&tcsr 0xa044 1>; #clock-cells = <0>; clock-output-names = "pcie_3a_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; pcie2b: pcie@1c18000 { device_type = "pci"; compatible = "qcom,pcie-sc8280xp"; reg = <0x0 0x01c18000 0x0 0x3000>, <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, <0x0 0x38100000 0x0 0x100000>, <0x0 0x01c1b000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <3>; num-lanes = <2>; msi-map = <0x0 &its 0xb0000 0x10000>; interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", "noc_aggr_4", "noc_aggr_south_sf"; assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_2B_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_2B_GDSC>; required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2b_phy>; phy-names = "pciephy"; status = "disabled"; pcie2b_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie2b_phy: phy@1c1e000 { compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c1e000 0x0 0x2000>; clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2B_PIPE_CLK>, <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; power-domains = <&gcc PCIE_2B_GDSC>; resets = <&gcc GCC_PCIE_2B_PHY_BCR>; reset-names = "phy"; #clock-cells = <0>; clock-output-names = "pcie_2b_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; pcie2a: pcie@1c20000 { device_type = "pci"; compatible = "qcom,pcie-sc8280xp"; reg = <0x0 0x01c20000 0x0 0x3000>, <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, <0x0 0x3c100000 0x0 0x100000>, <0x0 0x01c23000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; dma-coherent; linux,pci-domain = <2>; num-lanes = <4>; msi-map = <0x0 &its 0xa0000 0x10000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", "noc_aggr_4", "noc_aggr_south_sf"; assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; assigned-clock-rates = <19200000>; interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_2A_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_2A_GDSC>; required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2a_phy>; phy-names = "pciephy"; status = "disabled"; pcie2a_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie2a_phy: phy@1c24000 { compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; reg = <0x0 0x01c24000 0x0 0x2000>, <0x0 0x01c26000 0x0 0x2000>; clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2A_PIPE_CLK>, <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; power-domains = <&gcc PCIE_2A_GDSC>; resets = <&gcc GCC_PCIE_2A_PHY_BCR>; reset-names = "phy"; qcom,4ln-config-sel = <&tcsr 0xa044 0>; #clock-cells = <0>; clock-output-names = "pcie_2a_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x3000>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; power-domains = <&gcc UFS_PHY_GDSC>; required-opps = <&rpmhpd_opp_nom>; iommus = <&apps_smmu 0xe0 0x0>; dma-coherent; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; freq-table-hz = <75000000 300000000>, <0 0>, <0 0>, <75000000 300000000>, <0 0>, <0 0>, <0 0>, <0 0>; status = "disabled"; }; ufs_mem_phy: phy@1d87000 { compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_UFS_CARD_CLKREF_CLK>; clock-names = "ref", "ref_aux", "qref"; power-domains = <&gcc UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; #phy-cells = <0>; status = "disabled"; }; ufs_card_hc: ufshc@1da4000 { compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01da4000 0 0x3000>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_card_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; #reset-cells = <1>; resets = <&gcc GCC_UFS_CARD_BCR>; reset-names = "rst"; power-domains = <&gcc UFS_CARD_GDSC>; iommus = <&apps_smmu 0x4a0 0x0>; dma-coherent; clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, <&gcc GCC_UFS_CARD_AHB_CLK>, <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; freq-table-hz = <75000000 300000000>, <0 0>, <0 0>, <75000000 300000000>, <0 0>, <0 0>, <0 0>, <0 0>; status = "disabled"; }; ufs_card_phy: phy@1da7000 { compatible = "qcom,sc8280xp-qmp-ufs-phy"; reg = <0 0x01da7000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; clock-names = "ref", "ref_aux", "qref"; power-domains = <&gcc UFS_CARD_GDSC>; resets = <&ufs_card_hc 0>; reset-names = "ufsphy"; #phy-cells = <0>; status = "disabled"; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; tcsr: syscon@1fc0000 { compatible = "qcom,sc8280xp-tcsr", "syscon"; reg = <0x0 0x01fc0000 0x0 0x30000>; }; remoteproc_slpi: remoteproc@2400000 { compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; reg = <0 0x02400000 0 0x10000>; interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SC8280XP_LCX>, <&rpmhpd SC8280XP_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_slpi_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "slpi"; qcom,remote-pid = <3>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "sdsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x0521 0x0>; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x0522 0x0>; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x0523 0x0>; }; }; }; }; remoteproc_adsp: remoteproc@3000000 { compatible = "qcom,sc8280xp-adsp-pas"; reg = <0 0x03000000 0 0x10000>; interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SC8280XP_LCX>, <&rpmhpd SC8280XP_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; remoteproc_adsp_glink: glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "lpass"; qcom,remote-pid = <2>; gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; qcom,domain = <GPR_DOMAIN_ID_ADSP>; qcom,intents = <512 20>; #address-cells = <1>; #size-cells = <0>; q6apm: service@1 { compatible = "qcom,q6apm"; reg = <GPR_APM_MODULE_IID>; #sound-dai-cells = <0>; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6apmdai: dais { compatible = "qcom,q6apm-dais"; iommus = <&apps_smmu 0x0c01 0x0>; }; q6apmbedai: bedais { compatible = "qcom,q6apm-lpass-dais"; #sound-dai-cells = <1>; }; }; q6prm: service@2 { compatible = "qcom,q6prm"; reg = <GPR_PRM_MODULE_IID>; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6prmcc: clock-controller { compatible = "qcom,q6prm-lpass-clocks"; #clock-cells = <2>; }; }; }; }; }; rxmacro: rxmacro@3200000 { compatible = "qcom,sc8280xp-lpass-rx-macro"; reg = <0 0x03200000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&vamacro>; clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; assigned-clock-rates = <19200000>, <19200000>; clock-output-names = "mclk"; #clock-cells = <0>; #sound-dai-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&rx_swr_default>; status = "disabled"; }; swr1: soundwire@3210000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03210000 0 0x2000>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rxmacro>; clock-names = "iface"; resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; reset-names = "swr_audio_cgcr"; label = "RX"; qcom,din-ports = <0>; qcom,dout-ports = <5>; qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; status = "disabled"; }; txmacro: txmacro@3220000 { compatible = "qcom,sc8280xp-lpass-tx-macro"; reg = <0 0x03220000 0 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&tx_swr_default>; clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&vamacro>; clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; assigned-clock-rates = <19200000>, <19200000>; clock-output-names = "mclk"; #clock-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; wsamacro: codec@3240000 { compatible = "qcom,sc8280xp-lpass-wsa-macro"; reg = <0 0x03240000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&vamacro>; clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; assigned-clock-rates = <19200000>, <19200000>; #clock-cells = <0>; clock-output-names = "mclk"; #sound-dai-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&wsa_swr_default>; status = "disabled"; }; swr0: soundwire@3250000 { reg = <0 0x03250000 0 0x2000>; compatible = "qcom,soundwire-v1.6.0"; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wsamacro>; clock-names = "iface"; resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; reset-names = "swr_audio_cgcr"; label = "WSA"; qcom,din-ports = <2>; qcom,dout-ports = <6>; qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; status = "disabled"; }; lpass_audiocc: clock-controller@32a9000 { compatible = "qcom,sc8280xp-lpassaudiocc"; reg = <0 0x032a9000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; swr2: soundwire@3330000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03330000 0 0x2000>; interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "core", "wakeup"; clocks = <&txmacro>; clock-names = "iface"; resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; reset-names = "swr_audio_cgcr"; label = "TX"; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; qcom,din-ports = <4>; qcom,dout-ports = <0>; qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; status = "disabled"; }; vamacro: codec@3370000 { compatible = "qcom,sc8280xp-lpass-va-macro"; reg = <0 0x03370000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "mclk", "macro", "dcodec", "npl"; assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; assigned-clock-rates = <19200000>; #clock-cells = <0>; clock-output-names = "fsgen"; #sound-dai-cells = <1>; status = "disabled"; }; lpass_tlmm: pinctrl@33c0000 { compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; reg = <0 0x33c0000 0x0 0x20000>, <0 0x3550000 0x0 0x10000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 19>; clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "core", "audio"; status = "disabled"; tx_swr_default: tx-swr-default-state { clk-pins { pins = "gpio0"; function = "swr_tx_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio1", "gpio2"; function = "swr_tx_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; rx_swr_default: rx-swr-default-state { clk-pins { pins = "gpio3"; function = "swr_rx_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio4", "gpio5"; function = "swr_rx_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; dmic01_default: dmic01-default-state { clk-pins { pins = "gpio6"; function = "dmic1_clk"; drive-strength = <8>; output-high; }; data-pins { pins = "gpio7"; function = "dmic1_data"; drive-strength = <8>; input-enable; }; }; dmic01_sleep: dmic01-sleep-state { clk-pins { pins = "gpio6"; function = "dmic1_clk"; drive-strength = <2>; bias-disable; output-low; }; data-pins { pins = "gpio7"; function = "dmic1_data"; drive-strength = <2>; bias-pull-down; input-enable; }; }; dmic23_default: dmic23-default-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; drive-strength = <8>; output-high; }; data-pins { pins = "gpio9"; function = "dmic2_data"; drive-strength = <8>; input-enable; }; }; dmic23_sleep: dmic23-sleep-state { clk-pins { pins = "gpio8"; function = "dmic2_clk"; drive-strength = <2>; bias-disable; output-low; }; data-pins { pins = "gpio9"; function = "dmic2_data"; drive-strength = <2>; bias-pull-down; input-enable; }; }; wsa_swr_default: wsa-swr-default-state { clk-pins { pins = "gpio10"; function = "wsa_swr_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio11"; function = "wsa_swr_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; wsa2_swr_default: wsa2-swr-default-state { clk-pins { pins = "gpio15"; function = "wsa2_swr_clk"; drive-strength = <2>; slew-rate = <1>; bias-disable; }; data-pins { pins = "gpio16"; function = "wsa2_swr_data"; drive-strength = <2>; slew-rate = <1>; bias-bus-hold; }; }; }; lpasscc: clock-controller@33e0000 { compatible = "qcom,sc8280xp-lpasscc"; reg = <0 0x033e0000 0 0x12000>; #clock-cells = <1>; #reset-cells = <1>; }; gpu: gpu@3d00000 { compatible = "qcom,adreno-690.0", "qcom,adreno"; reg = <0 0x03d00000 0 0x40000>, <0 0x03d9e000 0 0x1000>, <0 0x03d61000 0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; #cooling-cells = <2>; status = "disabled"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-270000000 { opp-hz = /bits/ 64 <270000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; opp-peak-kBps = <451000>; }; opp-410000000 { opp-hz = /bits/ 64 <410000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; opp-peak-kBps = <1555000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; opp-peak-kBps = <1555000>; }; opp-547000000 { opp-hz = /bits/ 64 <547000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; opp-peak-kBps = <1555000>; }; opp-606000000 { opp-hz = /bits/ 64 <606000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM>; opp-peak-kBps = <2736000>; }; opp-640000000 { opp-hz = /bits/ 64 <640000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; opp-peak-kBps = <2736000>; }; opp-655000000 { opp-hz = /bits/ 64 <655000000>; opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; opp-peak-kBps = <2736000>; }; opp-690000000 { opp-hz = /bits/ 64 <690000000>; opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; opp-peak-kBps = <2736000>; }; }; }; gmu: gmu@3d6a000 { compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x34000>, <0 0x03de0000 0 0x10000>, <0 0x0b290000 0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc", "ahb", "hub", "smmu_vote"; power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&gpu_smmu 5 0xc00>; operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; }; }; gpucc: clock-controller@3d90000 { compatible = "qcom,sc8280xp-gpucc"; reg = <0 0x03d90000 0 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; power-domains = <&rpmhpd SC8280XP_GFX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; gpu_smmu: iommu@3da0000 { compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; #iommu-cells = <2>; #global-interrupts = <2>; interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, <&gpucc GPU_CC_HUB_AON_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gpu_cc_ahb_clk", "gpu_cc_hlos1_vote_gpu_smmu_clk", "gpu_cc_cx_gmu_clk", "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; }; sdc2: mmc@8804000 { compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4e0 0x0>; power-domains = <&rpmhpd SC8280XP_CX>; operating-points-v2 = <&sdc2_opp_table>; bus-width = <4>; dma-coherent; status = "disabled"; sdc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1800000 400000>; opp-avg-kBps = <100000 0>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_svs_l1>; opp-peak-kBps = <5400000 1600000>; opp-avg-kBps = <200000 0>; }; }; }; usb_0_hsphy: phy@88e5000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; reg = <0 0x088e5000 0 0x400>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; #phy-cells = <0>; status = "disabled"; }; usb_2_hsphy0: phy@88e7000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; reg = <0 0x088e7000 0 0x400>; clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; #phy-cells = <0>; status = "disabled"; }; usb_2_hsphy1: phy@88e8000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; reg = <0 0x088e8000 0 0x400>; clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; #phy-cells = <0>; status = "disabled"; }; usb_2_hsphy2: phy@88e9000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; reg = <0 0x088e9000 0 0x400>; clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; #phy-cells = <0>; status = "disabled"; }; usb_2_hsphy3: phy@88ea000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; reg = <0 0x088ea000 0 0x400>; clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; #phy-cells = <0>; status = "disabled"; }; usb_0_qmpphy: phy@88eb000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; reg = <0 0x088eb000 0 0x4000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB4_EUD_CLKREF_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe"; power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; #phy-cells = <1>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_0_qmpphy_out: endpoint {}; }; port@1 { reg = <1>; usb_0_qmpphy_usb_ss_in: endpoint { remote-endpoint = <&usb_0_dwc3_ss>; }; }; port@2 { reg = <2>; usb_0_qmpphy_dp_in: endpoint {}; }; }; }; usb_2_qmpphy0: phy@88ef000 { compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; reg = <0 0x088ef000 0 0x2000>; clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, <&gcc GCC_USB3_MP0_CLKREF_CLK>, <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; clock-names = "aux", "ref", "com_aux", "pipe"; resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; reset-names = "phy", "phy_phy"; power-domains = <&gcc USB30_MP_GDSC>; #clock-cells = <0>; clock-output-names = "usb2_phy0_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; usb_2_qmpphy1: phy@88f1000 { compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; reg = <0 0x088f1000 0 0x2000>; clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, <&gcc GCC_USB3_MP1_CLKREF_CLK>, <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; clock-names = "aux", "ref", "com_aux", "pipe"; resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; reset-names = "phy", "phy_phy"; power-domains = <&gcc USB30_MP_GDSC>; #clock-cells = <0>; clock-output-names = "usb2_phy1_pipe_clk"; #phy-cells = <0>; status = "disabled"; }; usb_1_hsphy: phy@8902000 { compatible = "qcom,sc8280xp-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; reg = <0 0x08902000 0 0x400>; #phy-cells = <0>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; status = "disabled"; }; usb_1_qmpphy: phy@8903000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; reg = <0 0x08903000 0 0x4000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, <&gcc GCC_USB4_CLKREF_CLK>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe"; power-domains = <&gcc USB30_SEC_GDSC>; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; #phy-cells = <1>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_1_qmpphy_out: endpoint {}; }; port@1 { reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { remote-endpoint = <&usb_1_dwc3_ss>; }; }; port@2 { reg = <2>; usb_1_qmpphy_dp_in: endpoint {}; }; }; }; mdss1_dp0_phy: phy@8909a00 { compatible = "qcom,sc8280xp-dp-phy"; reg = <0 0x08909a00 0 0x19c>, <0 0x08909200 0 0xec>, <0 0x08909600 0 0xec>, <0 0x08909000 0 0x1c8>; clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; mdss1_dp1_phy: phy@890ca00 { compatible = "qcom,sc8280xp-dp-phy"; reg = <0 0x0890ca00 0 0x19c>, <0 0x0890c200 0 0xec>, <0 0x0890c600 0 0xec>, <0 0x0890c000 0 0x1c8>; clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; pmu@9091000 { compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x09091000 0 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; operating-points-v2 = <&llcc_bwmon_opp_table>; llcc_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <762000>; }; opp-1 { opp-peak-kBps = <1720000>; }; opp-2 { opp-peak-kBps = <2086000>; }; opp-3 { opp-peak-kBps = <2597000>; }; opp-4 { opp-peak-kBps = <2929000>; }; opp-5 { opp-peak-kBps = <3879000>; }; opp-6 { opp-peak-kBps = <5161000>; }; opp-7 { opp-peak-kBps = <5931000>; }; opp-8 { opp-peak-kBps = <6515000>; }; opp-9 { opp-peak-kBps = <7980000>; }; opp-10 { opp-peak-kBps = <8136000>; }; opp-11 { opp-peak-kBps = <10437000>; }; opp-12 { opp-peak-kBps = <12191000>; }; }; }; pmu@90b6400 { compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; operating-points-v2 = <&cpu_bwmon_opp_table>; cpu_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <2288000>; }; opp-1 { opp-peak-kBps = <4577000>; }; opp-2 { opp-peak-kBps = <7110000>; }; opp-3 { opp-peak-kBps = <9155000>; }; opp-4 { opp-peak-kBps = <12298000>; }; opp-5 { opp-peak-kBps = <14236000>; }; opp-6 { opp-peak-kBps = <15258001>; }; }; }; system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, <0 0x09600000 0 0x58000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", "llcc4_base", "llcc5_base", "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; usb_2: usb@a4f8800 { compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; reg = <0 0x0a4f8800 0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, <&gcc GCC_USB30_MP_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, <&gcc GCC_USB30_MP_SLEEP_CLK>, <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, <&gcc GCC_USB30_MP_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, <&pdc 127 IRQ_TYPE_EDGE_BOTH>, <&pdc 126 IRQ_TYPE_EDGE_BOTH>, <&pdc 129 IRQ_TYPE_EDGE_BOTH>, <&pdc 128 IRQ_TYPE_EDGE_BOTH>, <&pdc 131 IRQ_TYPE_EDGE_BOTH>, <&pdc 130 IRQ_TYPE_EDGE_BOTH>, <&pdc 133 IRQ_TYPE_EDGE_BOTH>, <&pdc 132 IRQ_TYPE_EDGE_BOTH>, <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event_1", "pwr_event_2", "pwr_event_3", "pwr_event_4", "hs_phy_1", "hs_phy_2", "hs_phy_3", "hs_phy_4", "dp_hs_phy_1", "dm_hs_phy_1", "dp_hs_phy_2", "dm_hs_phy_2", "dp_hs_phy_3", "dm_hs_phy_3", "dp_hs_phy_4", "dm_hs_phy_4", "ss_phy_1", "ss_phy_2"; power-domains = <&gcc USB30_MP_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_MP_BCR>; interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; interconnect-names = "usb-ddr", "apps-usb"; wakeup-source; status = "disabled"; usb_2_dwc3: usb@a400000 { compatible = "snps,dwc3"; reg = <0 0x0a400000 0 0xcd00>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x800 0x0>; phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, <&usb_2_hsphy1>, <&usb_2_qmpphy1>, <&usb_2_hsphy2>, <&usb_2_hsphy3>; phy-names = "usb2-0", "usb3-0", "usb2-1", "usb3-1", "usb2-2", "usb2-3"; dr_mode = "host"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; }; }; usb_0: usb@a6f8800 { compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; wakeup-source; status = "disabled"; usb_0_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x820 0x0>; phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_0_dwc3_hs: endpoint { }; }; port@1 { reg = <1>; usb_0_dwc3_ss: endpoint { remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; }; }; }; }; }; usb_1: usb@a8f8800 { compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_SLEEP_CLK>, <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, <&gcc GCC_SYS_NOC_USB_AXI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_SEC_BCR>; interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; interconnect-names = "usb-ddr", "apps-usb"; wakeup-source; status = "disabled"; usb_1_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x860 0x0>; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_1_dwc3_hs: endpoint { }; }; port@1 { reg = <1>; usb_1_dwc3_ss: endpoint { remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; }; }; cci0: cci@ac4a000 { compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg = <0 0x0ac4a000 0 0x1000>; interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, <&camcc CAMCC_SLOW_AHB_CLK_SRC>, <&camcc CAMCC_CPAS_AHB_CLK>, <&camcc CAMCC_CCI_0_CLK>; clock-names = "camnoc_axi", "slow_ahb_src", "cpas_ahb", "cci"; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci0_default>; pinctrl-1 = <&cci0_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; cci0_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; cci0_i2c1: i2c-bus@1 { reg = <1>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; cci1: cci@ac4b000 { compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg = <0 0x0ac4b000 0 0x1000>; interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, <&camcc CAMCC_SLOW_AHB_CLK_SRC>, <&camcc CAMCC_CPAS_AHB_CLK>, <&camcc CAMCC_CCI_1_CLK>; clock-names = "camnoc_axi", "slow_ahb_src", "cpas_ahb", "cci"; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci1_default>; pinctrl-1 = <&cci1_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; cci1_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; cci1_i2c1: i2c-bus@1 { reg = <1>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; cci2: cci@ac4c000 { compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg = <0 0x0ac4c000 0 0x1000>; interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, <&camcc CAMCC_SLOW_AHB_CLK_SRC>, <&camcc CAMCC_CPAS_AHB_CLK>, <&camcc CAMCC_CCI_2_CLK>; clock-names = "camnoc_axi", "slow_ahb_src", "cpas_ahb", "cci"; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci2_default>; pinctrl-1 = <&cci2_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; cci2_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; cci2_i2c1: i2c-bus@1 { reg = <1>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; cci3: cci@ac4d000 { compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg = <0 0x0ac4d000 0 0x1000>; interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, <&camcc CAMCC_SLOW_AHB_CLK_SRC>, <&camcc CAMCC_CPAS_AHB_CLK>, <&camcc CAMCC_CCI_3_CLK>; clock-names = "camnoc_axi", "slow_ahb_src", "cpas_ahb", "cci"; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci3_default>; pinctrl-1 = <&cci3_sleep>; pinctrl-names = "default", "sleep"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; cci3_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; cci3_i2c1: i2c-bus@1 { reg = <1>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; camss: camss@ac5a000 { compatible = "qcom,sc8280xp-camss"; reg = <0 0x0ac5a000 0 0x2000>, <0 0x0ac5c000 0 0x2000>, <0 0x0ac65000 0 0x2000>, <0 0x0ac67000 0 0x2000>, <0 0x0acaf000 0 0x4000>, <0 0x0acb3000 0 0x1000>, <0 0x0acb6000 0 0x4000>, <0 0x0acba000 0 0x1000>, <0 0x0acbd000 0 0x4000>, <0 0x0acc1000 0 0x1000>, <0 0x0acc4000 0 0x4000>, <0 0x0acc8000 0 0x1000>, <0 0x0accb000 0 0x4000>, <0 0x0accf000 0 0x1000>, <0 0x0acd2000 0 0x4000>, <0 0x0acd6000 0 0x1000>, <0 0x0acd9000 0 0x4000>, <0 0x0acdd000 0 0x1000>, <0 0x0ace0000 0 0x4000>, <0 0x0ace4000 0 0x1000>; reg-names = "csiphy2", "csiphy3", "csiphy0", "csiphy1", "vfe0", "csid0", "vfe1", "csid1", "vfe2", "csid2", "vfe_lite0", "csid0_lite", "vfe_lite1", "csid1_lite", "vfe_lite2", "csid2_lite", "vfe_lite3", "csid3_lite", "vfe3", "csid3"; interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csid1_lite", "vfe_lite1", "csiphy3", "csid0", "vfe0", "csid1", "vfe1", "csid0_lite", "vfe_lite0", "csiphy0", "csiphy1", "csiphy2", "csid2", "vfe2", "csid3_lite", "csid2_lite", "vfe_lite3", "vfe_lite2", "csid3", "vfe3"; power-domains = <&camcc IFE_0_GDSC>, <&camcc IFE_1_GDSC>, <&camcc IFE_2_GDSC>, <&camcc IFE_3_GDSC>, <&camcc TITAN_TOP_GDSC>; power-domain-names = "ife0", "ife1", "ife2", "ife3", "top"; clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, <&camcc CAMCC_CPAS_AHB_CLK>, <&camcc CAMCC_CSIPHY0_CLK>, <&camcc CAMCC_CSI0PHYTIMER_CLK>, <&camcc CAMCC_CSIPHY1_CLK>, <&camcc CAMCC_CSI1PHYTIMER_CLK>, <&camcc CAMCC_CSIPHY2_CLK>, <&camcc CAMCC_CSI2PHYTIMER_CLK>, <&camcc CAMCC_CSIPHY3_CLK>, <&camcc CAMCC_CSI3PHYTIMER_CLK>, <&camcc CAMCC_IFE_0_AXI_CLK>, <&camcc CAMCC_IFE_0_CLK>, <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, <&camcc CAMCC_IFE_0_CSID_CLK>, <&camcc CAMCC_IFE_1_AXI_CLK>, <&camcc CAMCC_IFE_1_CLK>, <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, <&camcc CAMCC_IFE_1_CSID_CLK>, <&camcc CAMCC_IFE_2_AXI_CLK>, <&camcc CAMCC_IFE_2_CLK>, <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, <&camcc CAMCC_IFE_2_CSID_CLK>, <&camcc CAMCC_IFE_3_AXI_CLK>, <&camcc CAMCC_IFE_3_CLK>, <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, <&camcc CAMCC_IFE_3_CSID_CLK>, <&camcc CAMCC_IFE_LITE_0_CLK>, <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, <&camcc CAMCC_IFE_LITE_1_CLK>, <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, <&camcc CAMCC_IFE_LITE_2_CLK>, <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, <&camcc CAMCC_IFE_LITE_3_CLK>, <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>; clock-names = "camnoc_axi", "cpas_ahb", "csiphy0", "csiphy0_timer", "csiphy1", "csiphy1_timer", "csiphy2", "csiphy2_timer", "csiphy3", "csiphy3_timer", "vfe0_axi", "vfe0", "vfe0_cphy_rx", "vfe0_csid", "vfe1_axi", "vfe1", "vfe1_cphy_rx", "vfe1_csid", "vfe2_axi", "vfe2", "vfe2_cphy_rx", "vfe2_csid", "vfe3_axi", "vfe3", "vfe3_cphy_rx", "vfe3_csid", "vfe_lite0", "vfe_lite0_cphy_rx", "vfe_lite0_csid", "vfe_lite1", "vfe_lite1_cphy_rx", "vfe_lite1_csid", "vfe_lite2", "vfe_lite2_cphy_rx", "vfe_lite2_csid", "vfe_lite3", "vfe_lite3_cphy_rx", "vfe_lite3_csid", "gcc_axi_hf", "gcc_axi_sf"; iommus = <&apps_smmu 0x2000 0x4e0>, <&apps_smmu 0x2020 0x4e0>, <&apps_smmu 0x2040 0x4e0>, <&apps_smmu 0x2060 0x4e0>, <&apps_smmu 0x2080 0x4e0>, <&apps_smmu 0x20e0 0x4e0>, <&apps_smmu 0x20c0 0x4e0>, <&apps_smmu 0x20a0 0x4e0>, <&apps_smmu 0x2400 0x4e0>, <&apps_smmu 0x2420 0x4e0>, <&apps_smmu 0x2440 0x4e0>, <&apps_smmu 0x2460 0x4e0>, <&apps_smmu 0x2480 0x4e0>, <&apps_smmu 0x24e0 0x4e0>, <&apps_smmu 0x24c0 0x4e0>, <&apps_smmu 0x24a0 0x4e0>; interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "cam_ahb", "cam_hf_mnoc", "cam_sf_mnoc", "cam_sf_icp_mnoc"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; }; port@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; }; port@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; }; }; }; camcc: clock-controller@ad00000 { compatible = "qcom,sc8280xp-camcc"; reg = <0 0x0ad00000 0 0x20000>; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; power-domains = <&rpmhpd SC8280XP_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; mdss0: display-subsystem@ae00000 { compatible = "qcom,sc8280xp-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; clocks = <&gcc GCC_DISP_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; iommus = <&apps_smmu 0x1000 0x402>; power-domains = <&dispcc0 MDSS_GDSC>; resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; interrupt-controller; #interrupt-cells = <1>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; mdss0_mdp: display-controller@ae01000 { compatible = "qcom,sc8280xp-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc0 DISP_CC_MDSS_MDP_CLK>, <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "nrt_bus", "iface", "lut", "core", "vsync"; interrupt-parent = <&mdss0>; interrupts = <0>; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; operating-points-v2 = <&mdss0_mdp_opp_table>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss0_intf0_out: endpoint { remote-endpoint = <&mdss0_dp0_in>; }; }; port@4 { reg = <4>; mdss0_intf4_out: endpoint { remote-endpoint = <&mdss0_dp1_in>; }; }; port@5 { reg = <5>; mdss0_intf5_out: endpoint { remote-endpoint = <&mdss0_dp3_in>; }; }; port@6 { reg = <6>; mdss0_intf6_out: endpoint { remote-endpoint = <&mdss0_dp2_in>; }; }; }; mdss0_mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-375000000 { opp-hz = /bits/ 64 <375000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; required-opps = <&rpmhpd_opp_nom>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; required-opps = <&rpmhpd_opp_turbo_l1>; }; }; }; mdss0_dp0: displayport-controller@ae90000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0xae90000 0 0x200>, <0 0xae90200 0 0x200>, <0 0xae90400 0 0x600>, <0 0xae91000 0 0x400>, <0 0xae91400 0 0x400>; interrupt-parent = <&mdss0>; interrupts = <12>; clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; operating-points-v2 = <&mdss0_dp0_opp_table>; power-domains = <&rpmhpd SC8280XP_MMCX>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss0_dp0_in: endpoint { remote-endpoint = <&mdss0_intf0_out>; }; }; port@1 { reg = <1>; mdss0_dp0_out: endpoint { }; }; }; mdss0_dp0_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss0_dp1: displayport-controller@ae98000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0xae98000 0 0x200>, <0 0xae98200 0 0x200>, <0 0xae98400 0 0x600>, <0 0xae99000 0 0x400>, <0 0xae99400 0 0x400>; interrupt-parent = <&mdss0>; interrupts = <13>; clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; operating-points-v2 = <&mdss0_dp1_opp_table>; power-domains = <&rpmhpd SC8280XP_MMCX>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss0_dp1_in: endpoint { remote-endpoint = <&mdss0_intf4_out>; }; }; port@1 { reg = <1>; mdss0_dp1_out: endpoint { }; }; }; mdss0_dp1_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss0_dp2: displayport-controller@ae9a000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0xae9a000 0 0x200>, <0 0xae9a200 0 0x200>, <0 0xae9a400 0 0x600>, <0 0xae9b000 0 0x400>, <0 0xae9b400 0 0x400>; clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; interrupt-parent = <&mdss0>; interrupts = <14>; phys = <&mdss0_dp2_phy>; phy-names = "dp"; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; operating-points-v2 = <&mdss0_dp2_opp_table>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss0_dp2_in: endpoint { remote-endpoint = <&mdss0_intf6_out>; }; }; port@1 { reg = <1>; }; }; mdss0_dp2_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss0_dp3: displayport-controller@aea0000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0xaea0000 0 0x200>, <0 0xaea0200 0 0x200>, <0 0xaea0400 0 0x600>, <0 0xaea1000 0 0x400>, <0 0xaea1400 0 0x400>; clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; interrupt-parent = <&mdss0>; interrupts = <15>; phys = <&mdss0_dp3_phy>; phy-names = "dp"; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; operating-points-v2 = <&mdss0_dp3_opp_table>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss0_dp3_in: endpoint { remote-endpoint = <&mdss0_intf5_out>; }; }; port@1 { reg = <1>; }; }; mdss0_dp3_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; }; mdss0_dp2_phy: phy@aec2a00 { compatible = "qcom,sc8280xp-dp-phy"; reg = <0 0x0aec2a00 0 0x19c>, <0 0x0aec2200 0 0xec>, <0 0x0aec2600 0 0xec>, <0 0x0aec2000 0 0x1c8>; clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; mdss0_dp3_phy: phy@aec5a00 { compatible = "qcom,sc8280xp-dp-phy"; reg = <0 0x0aec5a00 0 0x19c>, <0 0x0aec5200 0 0xec>, <0 0x0aec5600 0 0xec>, <0 0x0aec5000 0 0x1c8>; clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; dispcc0: clock-controller@af00000 { compatible = "qcom,sc8280xp-dispcc0"; reg = <0 0x0af00000 0 0x20000>; clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>, <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd SC8280XP_MMCX>; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; status = "disabled"; }; pdc: interrupt-controller@b220000 { compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, <69 86 1>, <70 520 54>, <124 609 28>, <159 638 1>, <160 720 8>, <168 801 1>, <169 728 30>, <199 416 2>, <201 449 1>, <202 89 1>, <203 451 1>, <204 462 1>, <205 264 1>, <206 579 1>, <207 653 1>, <208 656 1>, <209 659 1>, <210 122 1>, <211 699 1>, <212 705 1>, <213 450 1>, <214 643 1>, <216 646 5>, <221 390 5>, <226 700 3>, <229 240 3>, <232 269 1>, <233 377 1>, <234 372 1>, <235 138 1>, <236 857 1>, <237 860 1>, <238 137 1>, <239 668 1>, <240 366 1>, <241 949 1>, <242 815 5>, <247 769 1>, <248 768 1>, <249 663 1>, <250 799 2>, <252 798 1>, <253 765 1>, <254 763 1>, <255 454 1>, <258 139 1>, <259 786 2>, <261 370 2>, <263 158 2>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; tsens2: thermal-sensor@c251000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c251000 0 0x1ff>, <0 0x0c224000 0 0x8>; #qcom,sensors = <11>; interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; tsens3: thermal-sensor@c252000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c252000 0 0x1ff>, <0 0x0c225000 0 0x8>; #qcom,sensors = <5>; interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; tsens0: thermal-sensor@c263000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x8>; /* SROT */ #qcom,sensors = <14>; interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; restart@c264000 { compatible = "qcom,pshold"; reg = <0 0x0c264000 0 0x4>; /* TZ seems to block access */ status = "reserved"; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x8>; /* SROT */ #qcom,sensors = <16>; interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; aoss_qmp: power-management@c300000 { compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; }; sram@c3f0000 { compatible = "qcom,rpmh-stats"; reg = <0 0x0c3f0000 0 0x400>; qcom,qmp = <&aoss_qmp>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, <0 0x0c600000 0 0x2000000>, <0 0x0e600000 0 0x100000>, <0 0x0e700000 0 0xa0000>, <0 0x0c40a000 0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; tlmm: pinctrl@f100000 { compatible = "qcom,sc8280xp-tlmm"; reg = <0 0x0f100000 0 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 230>; wakeup-parent = <&pdc>; cci0_default: cci0-default-state { cci0_i2c0_default: cci0-i2c0-default-pins { /* cci_i2c_sda0, cci_i2c_scl0 */ pins = "gpio113", "gpio114"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; cci0_i2c1_default: cci0-i2c1-default-pins { /* cci_i2c_sda1, cci_i2c_scl1 */ pins = "gpio115", "gpio116"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; }; cci0_sleep: cci0-sleep-state { cci0_i2c0_sleep: cci0-i2c0-sleep-pins { /* cci_i2c_sda0, cci_i2c_scl0 */ pins = "gpio113", "gpio114"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; cci0_i2c1_sleep: cci0-i2c1-sleep-pins { /* cci_i2c_sda1, cci_i2c_scl1 */ pins = "gpio115", "gpio116"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; }; cci1_default: cci1-default-state { cci1_i2c0_default: cci1-i2c0-default-pins { /* cci_i2c_sda2, cci_i2c_scl2 */ pins = "gpio10","gpio11"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; cci1_i2c1_default: cci1-i2c1-default-pins { /* cci_i2c_sda3, cci_i2c_scl3 */ pins = "gpio123","gpio124"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; }; cci1_sleep: cci1-sleep-state { cci1_i2c0_sleep: cci1-i2c0-sleep-pins { /* cci_i2c_sda2, cci_i2c_scl2 */ pins = "gpio10","gpio11"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; cci1_i2c1_sleep: cci1-i2c1-sleep-pins { /* cci_i2c_sda3, cci_i2c_scl3 */ pins = "gpio123","gpio124"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; }; cci2_default: cci2-default-state { cci2_i2c0_default: cci2-i2c0-default-pins { /* cci_i2c_sda4, cci_i2c_scl4 */ pins = "gpio117","gpio118"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; cci2_i2c1_default: cci2-i2c1-default-pins { /* cci_i2c_sda5, cci_i2c_scl5 */ pins = "gpio12","gpio13"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; }; cci2_sleep: cci2-sleep-state { cci2_i2c0_sleep: cci2-i2c0-sleep-pins { /* cci_i2c_sda4, cci_i2c_scl4 */ pins = "gpio117","gpio118"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; cci2_i2c1_sleep: cci2-i2c1-sleep-pins { /* cci_i2c_sda5, cci_i2c_scl5 */ pins = "gpio12","gpio13"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; }; cci3_default: cci3-default-state { cci3_i2c0_default: cci3-i2c0-default-pins { /* cci_i2c_sda6, cci_i2c_scl6 */ pins = "gpio145","gpio146"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; cci3_i2c1_default: cci3-i2c1-default-pins { /* cci_i2c_sda7, cci_i2c_scl7 */ pins = "gpio164","gpio165"; function = "cci_i2c"; drive-strength = <2>; bias-pull-up; }; }; cci3_sleep: cci3-sleep-state { cci3_i2c0_sleep: cci3-i2c0-sleep-pins { /* cci_i2c_sda6, cci_i2c_scl6 */ pins = "gpio145","gpio146"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; cci3_i2c1_sleep: cci3-i2c1-sleep-pins { /* cci_i2c_sda7, cci_i2c_scl7 */ pins = "gpio164","gpio165"; function = "cci_i2c"; drive-strength = <2>; bias-pull-down; }; }; qup_uart18_default: qup-uart18-default-state { cts-pins { pins = "gpio66"; function = "qup18"; drive-strength = <2>; bias-disable; }; rts-pins { pins = "gpio67"; function = "qup18"; drive-strength = <2>; bias-disable; }; tx-pins { pins = "gpio68"; function = "qup18"; drive-strength = <2>; bias-disable; }; rx-pins { pins = "gpio69"; function = "qup18"; drive-strength = <2>; bias-disable; }; }; }; pcie_smmu: iommu@14f80000 { compatible = "arm,smmu-v3"; reg = <0 0x14f80000 0 0x80000>; #iommu-cells = <1>; interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; interrupt-names = "eventq", "gerror", "cmdq-sync"; dma-coherent; status = "reserved"; /* Controlled by QHEE. */ }; apps_smmu: iommu@15000000 { compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; dma-coherent; }; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; #interrupt-cells = <3>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; #redistributor-regions = <1>; redistributor-stride = <0 0x20000>; #address-cells = <2>; #size-cells = <2>; ranges; its: msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; #msi-cells = <1>; }; }; watchdog@17c10000 { compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; }; timer@17c20000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x17c20000 0x0 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x20000000>; frame@17c21000 { frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17c26000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; reg = <0x0 0x18200000 0x0 0x10000>, <0x0 0x18210000 0x0 0x10000>, <0x0 0x18220000 0x0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 1>; label = "apps_rsc"; power-domains = <&cluster_pd>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; rpmhcc: clock-controller { compatible = "qcom,sc8280xp-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board_clk>; }; rpmhpd: power-controller { compatible = "qcom,sc8280xp-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; }; rpmhpd_opp_min_svs: opp2 { opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; rpmhpd_opp_low_svs: opp3 { opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; rpmhpd_opp_svs: opp4 { opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; rpmhpd_opp_svs_l1: opp5 { opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; }; rpmhpd_opp_nom: opp6 { opp-level = <RPMH_REGULATOR_LEVEL_NOM>; }; rpmhpd_opp_nom_l1: opp7 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; }; rpmhpd_opp_nom_l2: opp8 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; }; rpmhpd_opp_turbo: opp9 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; }; rpmhpd_opp_turbo_l1: opp10 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; }; }; }; epss_l3: interconnect@18590000 { compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, <0 0x18592000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; #clock-cells = <1>; }; remoteproc_nsp0: remoteproc@1b300000 { compatible = "qcom,sc8280xp-nsp0-pas"; reg = <0 0x1b300000 0 0x10000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SC8280XP_NSP>; power-domain-names = "nsp"; memory-region = <&pil_nsp0_mem>; qcom,smem-states = <&smp2p_nsp0_out 0>; qcom,smem-state-names = "stop"; interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "nsp0"; qcom,remote-pid = <5>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; #address-cells = <1>; #size-cells = <0>; compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x3181 0x0420>; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x3182 0x0420>; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x3183 0x0420>; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x3184 0x0420>; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x3185 0x0420>; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x3186 0x0420>; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x3187 0x0420>; }; compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x3188 0x0420>; }; compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; reg = <9>; iommus = <&apps_smmu 0x318b 0x0420>; }; compute-cb@10 { compatible = "qcom,fastrpc-compute-cb"; reg = <10>; iommus = <&apps_smmu 0x318b 0x0420>; }; compute-cb@11 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; iommus = <&apps_smmu 0x318c 0x0420>; }; compute-cb@12 { compatible = "qcom,fastrpc-compute-cb"; reg = <12>; iommus = <&apps_smmu 0x318d 0x0420>; }; compute-cb@13 { compatible = "qcom,fastrpc-compute-cb"; reg = <13>; iommus = <&apps_smmu 0x318e 0x0420>; }; compute-cb@14 { compatible = "qcom,fastrpc-compute-cb"; reg = <14>; iommus = <&apps_smmu 0x318f 0x0420>; }; }; }; }; remoteproc_nsp1: remoteproc@21300000 { compatible = "qcom,sc8280xp-nsp1-pas"; reg = <0 0x21300000 0 0x10000>; interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SC8280XP_NSP>; power-domain-names = "nsp"; memory-region = <&pil_nsp1_mem>; qcom,smem-states = <&smp2p_nsp1_out 0>; qcom,smem-state-names = "stop"; interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "nsp1"; qcom,remote-pid = <12>; }; }; mdss1: display-subsystem@22000000 { compatible = "qcom,sc8280xp-mdss"; reg = <0 0x22000000 0 0x1000>; reg-names = "mdss"; clocks = <&gcc GCC_DISP_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x1800 0x402>; power-domains = <&dispcc1 MDSS_GDSC>; resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; interrupt-controller; #interrupt-cells = <1>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; mdss1_mdp: display-controller@22001000 { compatible = "qcom,sc8280xp-dpu"; reg = <0 0x22001000 0 0x8f000>, <0 0x220b0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc1 DISP_CC_MDSS_MDP_CLK>, <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "nrt_bus", "iface", "lut", "core", "vsync"; interrupt-parent = <&mdss1>; interrupts = <0>; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; operating-points-v2 = <&mdss1_mdp_opp_table>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss1_intf0_out: endpoint { remote-endpoint = <&mdss1_dp0_in>; }; }; port@4 { reg = <4>; mdss1_intf4_out: endpoint { remote-endpoint = <&mdss1_dp1_in>; }; }; port@5 { reg = <5>; mdss1_intf5_out: endpoint { remote-endpoint = <&mdss1_dp3_in>; }; }; port@6 { reg = <6>; mdss1_intf6_out: endpoint { remote-endpoint = <&mdss1_dp2_in>; }; }; }; mdss1_mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-375000000 { opp-hz = /bits/ 64 <375000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; required-opps = <&rpmhpd_opp_nom>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; required-opps = <&rpmhpd_opp_turbo_l1>; }; }; }; mdss1_dp0: displayport-controller@22090000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0x22090000 0 0x200>, <0 0x22090200 0 0x200>, <0 0x22090400 0 0x600>, <0 0x22091000 0 0x400>, <0 0x22091400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; interrupt-parent = <&mdss1>; interrupts = <12>; phys = <&mdss1_dp0_phy>; phy-names = "dp"; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; operating-points-v2 = <&mdss1_dp0_opp_table>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss1_dp0_in: endpoint { remote-endpoint = <&mdss1_intf0_out>; }; }; port@1 { reg = <1>; }; }; mdss1_dp0_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss1_dp1: displayport-controller@22098000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0x22098000 0 0x200>, <0 0x22098200 0 0x200>, <0 0x22098400 0 0x600>, <0 0x22099000 0 0x400>, <0 0x22099400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; interrupt-parent = <&mdss1>; interrupts = <13>; phys = <&mdss1_dp1_phy>; phy-names = "dp"; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; operating-points-v2 = <&mdss1_dp1_opp_table>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss1_dp1_in: endpoint { remote-endpoint = <&mdss1_intf4_out>; }; }; port@1 { reg = <1>; }; }; mdss1_dp1_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss1_dp2: displayport-controller@2209a000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0x2209a000 0 0x200>, <0 0x2209a200 0 0x200>, <0 0x2209a400 0 0x600>, <0 0x2209b000 0 0x400>, <0 0x2209b400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; interrupt-parent = <&mdss1>; interrupts = <14>; phys = <&mdss1_dp2_phy>; phy-names = "dp"; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; operating-points-v2 = <&mdss1_dp2_opp_table>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss1_dp2_in: endpoint { remote-endpoint = <&mdss1_intf6_out>; }; }; port@1 { reg = <1>; }; }; mdss1_dp2_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss1_dp3: displayport-controller@220a0000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0x220a0000 0 0x200>, <0 0x220a0200 0 0x200>, <0 0x220a0400 0 0x600>, <0 0x220a1000 0 0x400>, <0 0x220a1400 0 0x400>; clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; interrupt-parent = <&mdss1>; interrupts = <15>; phys = <&mdss1_dp3_phy>; phy-names = "dp"; power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; operating-points-v2 = <&mdss1_dp3_opp_table>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss1_dp3_in: endpoint { remote-endpoint = <&mdss1_intf5_out>; }; }; port@1 { reg = <1>; }; }; mdss1_dp3_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; }; mdss1_dp2_phy: phy@220c2a00 { compatible = "qcom,sc8280xp-dp-phy"; reg = <0 0x220c2a00 0 0x19c>, <0 0x220c2200 0 0xec>, <0 0x220c2600 0 0xec>, <0 0x220c2000 0 0x1c8>; clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; mdss1_dp3_phy: phy@220c5a00 { compatible = "qcom,sc8280xp-dp-phy"; reg = <0 0x220c5a00 0 0x19c>, <0 0x220c5200 0 0xec>, <0 0x220c5600 0 0xec>, <0 0x220c5000 0 0x1c8>; clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_AHB_CLK>; clock-names = "aux", "cfg_ahb"; power-domains = <&rpmhpd SC8280XP_MX>; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; dispcc1: clock-controller@22100000 { compatible = "qcom,sc8280xp-dispcc1"; reg = <0 0x22100000 0 0x20000>; clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <0>, <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>, <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd SC8280XP_MMCX>; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; status = "disabled"; }; ethernet1: ethernet@23000000 { compatible = "qcom,sc8280xp-ethqos"; reg = <0x0 0x23000000 0x0 0x10000>, <0x0 0x23016000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; clocks = <&gcc GCC_EMAC1_AXI_CLK>, <&gcc GCC_EMAC1_SLV_AHB_CLK>, <&gcc GCC_EMAC1_PTP_CLK>, <&gcc GCC_EMAC1_RGMII_CLK>; clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_lpi"; iommus = <&apps_smmu 0x40 0xf>; power-domains = <&gcc EMAC_1_GDSC>; snps,tso; snps,pbl = <32>; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; status = "disabled"; }; }; sound: sound { }; thermal-zones { cpu0-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 1>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu1-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 2>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu2-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 3>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu3-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 4>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu4-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 5>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu5-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 6>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu6-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 7>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu7-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 8>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cluster0-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 9>; trips { cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpu-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens2 2>; cooling-maps { map0 { trip = <&gpu_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; mem-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 15>; trips { trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; }; [zur Elbe Produktseite wechseln0.80QuellennavigatorsAnalyse erneut starten2026-04-29] |
2026-05-26