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SSL sdm845.dtsi
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Spracherkennung für: .dtsi vermutete Sprache: Unknown {[0] [0] [0]} [Methode: Schwerpunktbildung, einfache Gewichte, sechs Dimensionen] // SPDX-License-Identifier: GPL-2.0
/* * SDM845 SoC device tree source * * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ #include <dt-bindings/clock/qcom,camcc-sdm845.h> #include <dt-bindings/clock/qcom,dispcc-sdm845.h> #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/clock/qcom,gpucc-sdm845.h> #include <dt-bindings/clock/qcom,lpass-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sdm845.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/reset/qcom,sdm845-pdc.h> #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; i2c7 = &i2c7; i2c8 = &i2c8; i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; i2c12 = &i2c12; i2c13 = &i2c13; i2c14 = &i2c14; i2c15 = &i2c15; spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; spi3 = &spi3; spi4 = &spi4; spi5 = &spi5; spi6 = &spi6; spi7 = &spi7; spi8 = &spi8; spi9 = &spi9; spi10 = &spi10; spi11 = &spi11; spi12 = &spi12; spi13 = &spi13; spi14 = &spi14; spi15 = &spi15; }; chosen { }; clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <38400000>; clock-output-names = "xo_board"; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32764>; }; }; cpus: cpus { #address-cells = <2>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd0>; power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&l2_0>; l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; }; }; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd1>; power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&l2_100>; l2_100: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd2>; power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&l2_200>; l2_200: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; power-domains = <&cpu_pd3>; power-domain-names = "psci"; next-level-cache = <&l2_300>; l2_300: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu4: cpu@400 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd4>; power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&l2_400>; l2_400: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu5: cpu@500 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd5>; power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&l2_500>; l2_500: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu6: cpu@600 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd6>; power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&l2_600>; l2_600: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu7: cpu@700 { device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd7>; power-domain-names = "psci"; #cooling-cells = <2>; next-level-cache = <&l2_700>; l2_700: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; }; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; core4 { cpu = <&cpu4>; }; core5 { cpu = <&cpu5>; }; core6 { cpu = <&cpu6>; }; core7 { cpu = <&cpu7>; }; }; }; cpu_idle_states: idle-states { entry-method = "psci"; little_cpu_sleep_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "little-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <350>; exit-latency-us = <461>; min-residency-us = <1890>; local-timer-stop; }; big_cpu_sleep_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "big-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <264>; exit-latency-us = <621>; min-residency-us = <952>; local-timer-stop; }; }; domain-idle-states { cluster_sleep_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; }; }; }; firmware { scm { compatible = "qcom,scm-sdm845", "qcom,scm"; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0 0x80000000 0 0>; }; cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; cpu0_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-peak-kBps = <800000 4800000>; }; cpu0_opp2: opp-403200000 { opp-hz = /bits/ 64 <403200000>; opp-peak-kBps = <800000 4800000>; }; cpu0_opp3: opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-peak-kBps = <800000 6451200>; }; cpu0_opp4: opp-576000000 { opp-hz = /bits/ 64 <576000000>; opp-peak-kBps = <800000 6451200>; }; cpu0_opp5: opp-652800000 { opp-hz = /bits/ 64 <652800000>; opp-peak-kBps = <800000 7680000>; }; cpu0_opp6: opp-748800000 { opp-hz = /bits/ 64 <748800000>; opp-peak-kBps = <1804000 9216000>; }; cpu0_opp7: opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-peak-kBps = <1804000 9216000>; }; cpu0_opp8: opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-peak-kBps = <1804000 10444800>; }; cpu0_opp9: opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-peak-kBps = <1804000 11980800>; }; cpu0_opp10: opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-peak-kBps = <1804000 11980800>; }; cpu0_opp11: opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-peak-kBps = <2188000 13516800>; }; cpu0_opp12: opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; opp-peak-kBps = <2188000 15052800>; }; cpu0_opp13: opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-peak-kBps = <2188000 16588800>; }; cpu0_opp14: opp-1420800000 { opp-hz = /bits/ 64 <1420800000>; opp-peak-kBps = <3072000 18124800>; }; cpu0_opp15: opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-peak-kBps = <3072000 19353600>; }; cpu0_opp16: opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; opp-peak-kBps = <4068000 19353600>; }; cpu0_opp17: opp-1689600000 { opp-hz = /bits/ 64 <1689600000>; opp-peak-kBps = <4068000 20889600>; }; cpu0_opp18: opp-1766400000 { opp-hz = /bits/ 64 <1766400000>; opp-peak-kBps = <4068000 22425600>; }; }; cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; cpu4_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-peak-kBps = <800000 4800000>; }; cpu4_opp2: opp-403200000 { opp-hz = /bits/ 64 <403200000>; opp-peak-kBps = <800000 4800000>; }; cpu4_opp3: opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-peak-kBps = <1804000 4800000>; }; cpu4_opp4: opp-576000000 { opp-hz = /bits/ 64 <576000000>; opp-peak-kBps = <1804000 4800000>; }; cpu4_opp5: opp-652800000 { opp-hz = /bits/ 64 <652800000>; opp-peak-kBps = <1804000 4800000>; }; cpu4_opp6: opp-748800000 { opp-hz = /bits/ 64 <748800000>; opp-peak-kBps = <1804000 4800000>; }; cpu4_opp7: opp-825600000 { opp-hz = /bits/ 64 <825600000>; opp-peak-kBps = <2188000 9216000>; }; cpu4_opp8: opp-902400000 { opp-hz = /bits/ 64 <902400000>; opp-peak-kBps = <2188000 9216000>; }; cpu4_opp9: opp-979200000 { opp-hz = /bits/ 64 <979200000>; opp-peak-kBps = <2188000 9216000>; }; cpu4_opp10: opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-peak-kBps = <3072000 9216000>; }; cpu4_opp11: opp-1132800000 { opp-hz = /bits/ 64 <1132800000>; opp-peak-kBps = <3072000 11980800>; }; cpu4_opp12: opp-1209600000 { opp-hz = /bits/ 64 <1209600000>; opp-peak-kBps = <4068000 11980800>; }; cpu4_opp13: opp-1286400000 { opp-hz = /bits/ 64 <1286400000>; opp-peak-kBps = <4068000 11980800>; }; cpu4_opp14: opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-peak-kBps = <4068000 15052800>; }; cpu4_opp15: opp-1459200000 { opp-hz = /bits/ 64 <1459200000>; opp-peak-kBps = <4068000 15052800>; }; cpu4_opp16: opp-1536000000 { opp-hz = /bits/ 64 <1536000000>; opp-peak-kBps = <5412000 15052800>; }; cpu4_opp17: opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; opp-peak-kBps = <5412000 15052800>; }; cpu4_opp18: opp-1689600000 { opp-hz = /bits/ 64 <1689600000>; opp-peak-kBps = <5412000 19353600>; }; cpu4_opp19: opp-1766400000 { opp-hz = /bits/ 64 <1766400000>; opp-peak-kBps = <6220000 19353600>; }; cpu4_opp20: opp-1843200000 { opp-hz = /bits/ 64 <1843200000>; opp-peak-kBps = <6220000 19353600>; }; cpu4_opp21: opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; opp-peak-kBps = <7216000 19353600>; }; cpu4_opp22: opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-peak-kBps = <7216000 20889600>; }; cpu4_opp23: opp-2092800000 { opp-hz = /bits/ 64 <2092800000>; opp-peak-kBps = <7216000 20889600>; }; cpu4_opp24: opp-2169600000 { opp-hz = /bits/ 64 <2169600000>; opp-peak-kBps = <7216000 20889600>; }; cpu4_opp25: opp-2246400000 { opp-hz = /bits/ 64 <2246400000>; opp-peak-kBps = <7216000 20889600>; }; cpu4_opp26: opp-2323200000 { opp-hz = /bits/ 64 <2323200000>; opp-peak-kBps = <7216000 20889600>; }; cpu4_opp27: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <7216000 22425600>; }; cpu4_opp28: opp-2476800000 { opp-hz = /bits/ 64 <2476800000>; opp-peak-kBps = <7216000 22425600>; }; cpu4_opp29: opp-2553600000 { opp-hz = /bits/ 64 <2553600000>; opp-peak-kBps = <7216000 22425600>; }; cpu4_opp30: opp-2649600000 { opp-hz = /bits/ 64 <2649600000>; opp-peak-kBps = <7216000 22425600>; }; cpu4_opp31: opp-2745600000 { opp-hz = /bits/ 64 <2745600000>; opp-peak-kBps = <7216000 25497600>; }; cpu4_opp32: opp-2803200000 { opp-hz = /bits/ 64 <2803200000>; opp-peak-kBps = <7216000 25497600>; }; }; dsi_opp_table: opp-table-dsi { compatible = "operating-points-v2"; opp-19200000 { opp-hz = /bits/ 64 <19200000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-275000000 { opp-hz = /bits/ 64 <275000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-328580000 { opp-hz = /bits/ 64 <328580000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-358000000 { opp-hz = /bits/ 64 <358000000>; required-opps = <&rpmhpd_opp_nom>; }; }; qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-19200000 { opp-hz = /bits/ 64 <19200000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-150000000 { opp-hz = /bits/ 64 <150000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_nom>; }; }; qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-50000000 { opp-hz = /bits/ 64 <50000000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-75000000 { opp-hz = /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-128000000 { opp-hz = /bits/ 64 <128000000>; required-opps = <&rpmhpd_opp_nom>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; psci: psci { compatible = "arm,psci-1.0"; method = "smc"; cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; domain-idle-states = <&big_cpu_sleep_0>; }; cluster_pd: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&cluster_sleep_0>; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_mem: hyp-mem@85700000 { reg = <0 0x85700000 0 0x600000>; no-map; }; xbl_mem: xbl-mem@85e00000 { reg = <0 0x85e00000 0 0x100000>; no-map; }; aop_mem: aop-mem@85fc0000 { reg = <0 0x85fc0000 0 0x20000>; no-map; }; aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { compatible = "qcom,cmd-db"; reg = <0x0 0x85fe0000 0 0x20000>; no-map; }; smem@86000000 { compatible = "qcom,smem"; reg = <0x0 0x86000000 0 0x200000>; no-map; hwlocks = <&tcsr_mutex 3>; }; tz_mem: tz@86200000 { reg = <0 0x86200000 0 0x2d00000>; no-map; }; rmtfs_mem: rmtfs@88f00000 { compatible = "qcom,rmtfs-mem"; reg = <0 0x88f00000 0 0x200000>; no-map; qcom,client-id = <1>; qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; }; qseecom_mem: qseecom@8ab00000 { reg = <0 0x8ab00000 0 0x1400000>; no-map; }; camera_mem: camera-mem@8bf00000 { reg = <0 0x8bf00000 0 0x500000>; no-map; }; ipa_fw_mem: ipa-fw@8c400000 { reg = <0 0x8c400000 0 0x10000>; no-map; }; ipa_gsi_mem: ipa-gsi@8c410000 { reg = <0 0x8c410000 0 0x5000>; no-map; }; gpu_mem: gpu@8c415000 { reg = <0 0x8c415000 0 0x2000>; no-map; }; adsp_mem: adsp@8c500000 { reg = <0 0x8c500000 0 0x1a00000>; no-map; }; wlan_msa_mem: wlan-msa@8df00000 { reg = <0 0x8df00000 0 0x100000>; no-map; }; mpss_region: mpss@8e000000 { reg = <0 0x8e000000 0 0x7800000>; no-map; }; venus_mem: venus@95800000 { reg = <0 0x95800000 0 0x500000>; no-map; }; cdsp_mem: cdsp@95d00000 { reg = <0 0x95d00000 0 0x800000>; no-map; }; mba_region: mba@96500000 { reg = <0 0x96500000 0 0x200000>; no-map; }; slpi_mem: slpi@96700000 { reg = <0 0x96700000 0 0x1400000>; no-map; }; spss_mem: spss@97b00000 { reg = <0 0x97b00000 0 0x100000>; no-map; }; mdata_mem: mpss-metadata { alloc-ranges = <0 0xa0000000 0 0x20000000>; size = <0 0x4000>; no-map; }; fastrpc_mem: fastrpc { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; alignment = <0x0 0x400000>; size = <0x0 0x1000000>; reusable; }; }; adsp_pas: remoteproc-adsp { compatible = "qcom,sdm845-adsp-pas"; interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; memory-region = <&adsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; label = "lpass"; qcom,remote-pid = <2>; mboxes = <&apss_shared 8>; apr { compatible = "qcom,apr-v2"; qcom,glink-channels = "apr_audio_svc"; qcom,domain = <APR_DOMAIN_ADSP>; #address-cells = <1>; #size-cells = <0>; qcom,intents = <512 20>; service@3 { reg = <APR_SVC_ADSP_CORE>; compatible = "qcom,q6core"; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; }; q6afe: service@4 { compatible = "qcom,q6afe"; reg = <APR_SVC_AFE>; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6afedai: dais { compatible = "qcom,q6afe-dais"; #address-cells = <1>; #size-cells = <0>; #sound-dai-cells = <1>; }; }; q6asm: service@7 { compatible = "qcom,q6asm"; reg = <APR_SVC_ASM>; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6asmdai: dais { compatible = "qcom,q6asm-dais"; #address-cells = <1>; #size-cells = <0>; #sound-dai-cells = <1>; iommus = <&apps_smmu 0x1821 0x0>; }; }; q6adm: service@8 { compatible = "qcom,q6adm"; reg = <APR_SVC_ADM>; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; q6routing: routing { compatible = "qcom,q6adm-routing"; #sound-dai-cells = <0>; }; }; }; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x1823 0x0>; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x1824 0x0>; }; }; }; }; cdsp_pas: remoteproc-cdsp { compatible = "qcom,sdm845-cdsp-pas"; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; memory-region = <&cdsp_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; label = "turing"; qcom,remote-pid = <5>; mboxes = <&apss_shared 4>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x1401 0x30>; }; compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x1402 0x30>; }; compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x1403 0x30>; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x1404 0x30>; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x1405 0x30>; }; compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x1406 0x30>; }; compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x1407 0x30>; }; compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x1408 0x30>; }; }; }; }; smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 6>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-lpass { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; ipa_smp2p_out: ipa-ap-to-modem { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; ipa_smp2p_in: ipa-modem-to-ap { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-slpi { compatible = "qcom,smp2p"; qcom,smem = <481>, <430>; interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 26>; qcom,local-pid = <0>; qcom,remote-pid = <3>; slpi_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; slpi_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; soc: soc@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sdm845"; reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <&pcie0_phy>, <&pcie1_phy>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; power-domains = <&rpmhpd SDM845_CX>; }; qfprom@784000 { compatible = "qcom,sdm845-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>; #address-cells = <1>; #size-cells = <1>; qusb2p_hstx_trim: hstx-trim-primary@1eb { reg = <0x1eb 0x1>; bits = <1 4>; }; qusb2s_hstx_trim: hstx-trim-secondary@1eb { reg = <0x1eb 0x2>; bits = <6 4>; }; }; rng: rng@793000 { compatible = "qcom,prng-ee"; reg = <0 0x00793000 0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; gpi_dma0: dma-controller@800000 { #dma-cells = <3>; compatible = "qcom,sdm845-gpi-dma"; reg = <0 0x00800000 0 0x60000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <13>; dma-channel-mask = <0xfa>; iommus = <&apps_smmu 0x0016 0x0>; status = "disabled"; }; qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; iommus = <&apps_smmu 0x3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi0: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart0: serial@880000 { compatible = "qcom,geni-uart"; reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart0_default>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c1: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi1: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_default>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart1: serial@884000 { compatible = "qcom,geni-uart"; reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart1_default>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi2: spi@888000 { compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_default>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart2: serial@888000 { compatible = "qcom,geni-uart"; reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c3: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_default>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi3: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_default>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart3: serial@88c000 { compatible = "qcom,geni-uart"; reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c4: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi4: spi@890000 { compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_default>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart4: serial@890000 { compatible = "qcom,geni-uart"; reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart4_default>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c5: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi5: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_default>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart5: serial@894000 { compatible = "qcom,geni-uart"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_default>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c6: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi6: spi@898000 { compatible = "qcom,geni-spi"; reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_default>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart6: serial@898000 { compatible = "qcom,geni-uart"; reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c7: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; spi7: spi@89c000 { compatible = "qcom,geni-spi"; reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi7_default>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart7: serial@89c000 { compatible = "qcom,geni-uart"; reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; gpi_dma1: dma-controller@a00000 { #dma-cells = <3>; compatible = "qcom,sdm845-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <13>; dma-channel-mask = <0xfa>; iommus = <&apps_smmu 0x06d6 0x0>; status = "disabled"; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0x6c3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core"; status = "disabled"; i2c8: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi8: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_default>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart8: serial@a80000 { compatible = "qcom,geni-uart"; reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart8_default>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi9: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_default>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart9: serial@a84000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_default>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi10: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_default>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart10: serial@a88000 { compatible = "qcom,geni-uart"; reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart10_default>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi11: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_default>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart11: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart11_default>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi12: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart12: serial@a90000 { compatible = "qcom,geni-uart"; reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart12_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi13: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_default>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart13: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart13_default>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c14: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi14: spi@a98000 { compatible = "qcom,geni-spi"; reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi14_default>; interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart14: serial@a98000 { compatible = "qcom,geni-uart"; reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart14_default>; interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; }; spi15: spi@a9c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a9c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_default>; interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, <&gpi_dma1 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart15: serial@a9c000 { compatible = "qcom,geni-uart"; reg = <0 0x00a9c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart15_default>; interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, <0 0x01300000 0 0x50000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; dma@10a2000 { compatible = "qcom,sdm845-dcc", "qcom,dcc"; reg = <0x0 0x010a2000 0x0 0x1000>, <0x0 0x010ae000 0x0 0x2000>; }; pmu@114a000 { compatible = "qcom,sdm845-llcc-bwmon"; reg = <0 0x0114a000 0 0x1000>; interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>; operating-points-v2 = <&llcc_bwmon_opp_table>; llcc_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; /* * The interconnect path bandwidth taken from * cpu4_opp_table bandwidth for gladiator_noc-mem_noc * interconnect. This also matches the * bandwidth table of qcom,llccbw (qcom,bw-tbl, * bus width: 4 bytes) from msm-4.9 downstream * kernel. */ opp-0 { opp-peak-kBps = <800000>; }; opp-1 { opp-peak-kBps = <1804000>; }; opp-2 { opp-peak-kBps = <3072000>; }; opp-3 { opp-peak-kBps = <5412000>; }; opp-4 { opp-peak-kBps = <7216000>; }; }; }; pmu@1436400 { compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x01436400 0 0x600>; interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; operating-points-v2 = <&cpu_bwmon_opp_table>; cpu_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; /* * The interconnect path bandwidth taken from * cpu4_opp_table bandwidth for OSM L3 * interconnect. This also matches the OSM L3 * from bandwidth table of qcom,cpu4-l3lat-mon * (qcom,core-dev-table, bus width: 16 bytes) * from msm-4.9 downstream kernel. */ opp-0 { opp-peak-kBps = <4800000>; }; opp-1 { opp-peak-kBps = <9216000>; }; opp-2 { opp-peak-kBps = <15052800>; }; opp-3 { opp-peak-kBps = <20889600>; }; opp-4 { opp-peak-kBps = <25497600>; }; }; }; pcie0: pcie@1c00000 { compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60100000 0 0x100000>, <0 0x01c07000 0 0x1000>; reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "tbu"; iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, <0x100 &apps_smmu 0x1c11 0x1>, <0x200 &apps_smmu 0x1c12 0x1>, <0x300 &apps_smmu 0x1c13 0x1>, <0x400 &apps_smmu 0x1c14 0x1>, <0x500 &apps_smmu 0x1c15 0x1>, <0x600 &apps_smmu 0x1c16 0x1>, <0x700 &apps_smmu 0x1c17 0x1>, <0x800 &apps_smmu 0x1c18 0x1>, <0x900 &apps_smmu 0x1c19 0x1>, <0xa00 &apps_smmu 0x1c1a 0x1>, <0xb00 &apps_smmu 0x1c1b 0x1>, <0xc00 &apps_smmu 0x1c1c 0x1>, <0xd00 &apps_smmu 0x1c1d 0x1>, <0xe00 &apps_smmu 0x1c1e 0x1>, <0xf00 &apps_smmu 0x1c1f 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; phy-names = "pciephy"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie0_phy: phy@1c06000 { compatible = "qcom,sdm845-qmp-pcie-phy"; reg = <0 0x01c06000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; clock-output-names = "pcie_0_pipe_clk"; #clock-cells = <0>; #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; assigned-clock-rates = <100000000>; status = "disabled"; }; pcie1: pcie@1c08000 { compatible = "qcom,pcie-sdm845"; reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40100000 0 0x100000>, <0 0x01c0c000 0 0x1000>; reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_1_CLKREF_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ref", "tbu"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, <0x100 &apps_smmu 0x1c01 0x1>, <0x200 &apps_smmu 0x1c02 0x1>, <0x300 &apps_smmu 0x1c03 0x1>, <0x400 &apps_smmu 0x1c04 0x1>, <0x500 &apps_smmu 0x1c05 0x1>, <0x600 &apps_smmu 0x1c06 0x1>, <0x700 &apps_smmu 0x1c07 0x1>, <0x800 &apps_smmu 0x1c08 0x1>, <0x900 &apps_smmu 0x1c09 0x1>, <0xa00 &apps_smmu 0x1c0a 0x1>, <0xb00 &apps_smmu 0x1c0b 0x1>, <0xc00 &apps_smmu 0x1c0c 0x1>, <0xd00 &apps_smmu 0x1c0d 0x1>, <0xe00 &apps_smmu 0x1c0e 0x1>, <0xf00 &apps_smmu 0x1c0f 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; phy-names = "pciephy"; status = "disabled"; pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; ranges; }; }; pcie1_phy: phy@1c0a000 { compatible = "qcom,sdm845-qhp-pcie-phy"; reg = <0 0x01c0a000 0 0x2000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_CLKREF_CLK>, <&gcc GCC_PCIE_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; clock-output-names = "pcie_1_pipe_clk"; #clock-cells = <0>; #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; assigned-clock-rates = <100000000>; status = "disabled"; }; mem_noc: interconnect@1380000 { compatible = "qcom,sdm845-mem-noc"; reg = <0 0x01380000 0 0x27200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; dc_noc: interconnect@14e0000 { compatible = "qcom,sdm845-dc-noc"; reg = <0 0x014e0000 0 0x400>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; config_noc: interconnect@1500000 { compatible = "qcom,sdm845-config-noc"; reg = <0 0x01500000 0 0x5080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sdm845-system-noc"; reg = <0 0x01620000 0 0x18080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sdm845-aggre1-noc"; reg = <0 0x016e0000 0 0x15080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sdm845-aggre2-noc"; reg = <0 0x01700000 0 0x1f300>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sdm845-mmss-noc"; reg = <0 0x01740000 0 0x1c100>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x2500>, <0 0x01d90000 0 0x8000>; reg-names = "std", "ice"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; power-domains = <&gcc UFS_PHY_GDSC>; #reset-cells = <1>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; iommus = <&apps_smmu 0x100 0xf>; clock-names = "core_clk", "bus_aggr_clk", "iface_clk", "core_clk_unipro", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk", "ice_core_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; interconnect-names = "ufs-ddr", "cpu-ufs"; status = "disabled"; ufs_opp_table: opp-table { compatible = "operating-points-v2"; opp-50000000 { opp-hz = /bits/ 64 <50000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <37500000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <150000000>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <0>, /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; ufs_mem_phy: phy@1d87000 { compatible = "qcom,sdm845-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>; clock-names = "ref", "ref_aux", "qref"; power-domains = <&gcc UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; #phy-cells = <0>; status = "disabled"; }; cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rpmhcc RPMH_CE_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; iommus = <&apps_smmu 0x704 0x1>, <&apps_smmu 0x706 0x1>, <&apps_smmu 0x714 0x1>, <&apps_smmu 0x716 0x1>; }; crypto: crypto@1dfa000 { compatible = "qcom,crypto-v5.4"; reg = <0 0x01dfa000 0 0x6000>; clocks = <&gcc GCC_CE1_AHB_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&rpmhcc RPMH_CE_CLK>; clock-names = "iface", "bus", "core"; dmas = <&cryptobam 6>, <&cryptobam 7>; dma-names = "rx", "tx"; iommus = <&apps_smmu 0x704 0x1>, <&apps_smmu 0x706 0x1>, <&apps_smmu 0x714 0x1>, <&apps_smmu 0x716 0x1>; }; ipa: ipa@1e40000 { compatible = "qcom,sdm845-ipa"; iommus = <&apps_smmu 0x720 0x0>, <&apps_smmu 0x722 0x0>; reg = <0 0x01e40000 0 0x7000>, <0 0x01e47000 0 0x2000>, <0 0x01e04000 0 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", "gsi", "ipa-clock-query", "ipa-setup-ready"; clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names = "memory", "imem", "config"; qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; status = "disabled"; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; #hwlock-cells = <1>; }; tcsr_regs_1: syscon@1f60000 { compatible = "qcom,sdm845-tcsr", "syscon"; reg = <0 0x01f60000 0 0x20000>; }; tlmm: pinctrl@3400000 { compatible = "qcom,sdm845-pinctrl"; reg = <0 0x03400000 0 0xc00000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc_intc>; cci0_default: cci0-default-state { /* SDA, SCL */ pins = "gpio17", "gpio18"; function = "cci_i2c"; bias-pull-up; drive-strength = <2>; /* 2 mA */ }; cci0_sleep: cci0-sleep-state { /* SDA, SCL */ pins = "gpio17", "gpio18"; function = "cci_i2c"; drive-strength = <2>; /* 2 mA */ bias-pull-down; }; cci1_default: cci1-default-state { /* SDA, SCL */ pins = "gpio19", "gpio20"; function = "cci_i2c"; bias-pull-up; drive-strength = <2>; /* 2 mA */ }; cci1_sleep: cci1-sleep-state { /* SDA, SCL */ pins = "gpio19", "gpio20"; function = "cci_i2c"; drive-strength = <2>; /* 2 mA */ bias-pull-down; }; qspi_clk: qspi-clk-state { pins = "gpio95"; function = "qspi_clk"; }; qspi_cs0: qspi-cs0-state { pins = "gpio90"; function = "qspi_cs"; }; qspi_cs1: qspi-cs1-state { pins = "gpio89"; function = "qspi_cs"; }; qspi_data0: qspi-data0-state { pins = "gpio91"; function = "qspi_data"; }; qspi_data1: qspi-data1-state { pins = "gpio92"; function = "qspi_data"; }; qspi_data23: qspi-data23-state { pins = "gpio93", "gpio94"; function = "qspi_data"; }; qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; function = "qup0"; }; qup_i2c1_default: qup-i2c1-default-state { pins = "gpio17", "gpio18"; function = "qup1"; }; qup_i2c2_default: qup-i2c2-default-state { pins = "gpio27", "gpio28"; function = "qup2"; }; qup_i2c3_default: qup-i2c3-default-state { pins = "gpio41", "gpio42"; function = "qup3"; }; qup_i2c4_default: qup-i2c4-default-state { pins = "gpio89", "gpio90"; function = "qup4"; }; qup_i2c5_default: qup-i2c5-default-state { pins = "gpio85", "gpio86"; function = "qup5"; }; qup_i2c6_default: qup-i2c6-default-state { pins = "gpio45", "gpio46"; function = "qup6"; }; qup_i2c7_default: qup-i2c7-default-state { pins = "gpio93", "gpio94"; function = "qup7"; }; qup_i2c8_default: qup-i2c8-default-state { pins = "gpio65", "gpio66"; function = "qup8"; }; qup_i2c9_default: qup-i2c9-default-state { pins = "gpio6", "gpio7"; function = "qup9"; }; qup_i2c10_default: qup-i2c10-default-state { pins = "gpio55", "gpio56"; function = "qup10"; }; qup_i2c11_default: qup-i2c11-default-state { pins = "gpio31", "gpio32"; function = "qup11"; }; qup_i2c12_default: qup-i2c12-default-state { pins = "gpio49", "gpio50"; function = "qup12"; }; qup_i2c13_default: qup-i2c13-default-state { pins = "gpio105", "gpio106"; function = "qup13"; }; qup_i2c14_default: qup-i2c14-default-state { pins = "gpio33", "gpio34"; function = "qup14"; }; qup_i2c15_default: qup-i2c15-default-state { pins = "gpio81", "gpio82"; function = "qup15"; }; qup_spi0_default: qup-spi0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; }; qup_spi1_default: qup-spi1-default-state { pins = "gpio17", "gpio18", "gpio19", "gpio20"; function = "qup1"; }; qup_spi2_default: qup-spi2-default-state { pins = "gpio27", "gpio28", "gpio29", "gpio30"; function = "qup2"; }; qup_spi3_default: qup-spi3-default-state { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "qup3"; }; qup_spi4_default: qup-spi4-default-state { pins = "gpio89", "gpio90", "gpio91", "gpio92"; function = "qup4"; }; qup_spi5_default: qup-spi5-default-state { pins = "gpio85", "gpio86", "gpio87", "gpio88"; function = "qup5"; }; qup_spi6_default: qup-spi6-default-state { pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "qup6"; }; qup_spi7_default: qup-spi7-default-state { pins = "gpio93", "gpio94", "gpio95", "gpio96"; function = "qup7"; }; qup_spi8_default: qup-spi8-default-state { pins = "gpio65", "gpio66", "gpio67", "gpio68"; function = "qup8"; }; qup_spi9_default: qup-spi9-default-state { pins = "gpio6", "gpio7", "gpio4", "gpio5"; function = "qup9"; }; qup_spi10_default: qup-spi10-default-state { pins = "gpio55", "gpio56", "gpio53", "gpio54"; function = "qup10"; }; qup_spi11_default: qup-spi11-default-state { pins = "gpio31", "gpio32", "gpio33", "gpio34"; function = "qup11"; }; qup_spi12_default: qup-spi12-default-state { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "qup12"; }; qup_spi13_default: qup-spi13-default-state { pins = "gpio105", "gpio106", "gpio107", "gpio108"; function = "qup13"; }; qup_spi14_default: qup-spi14-default-state { pins = "gpio33", "gpio34", "gpio31", "gpio32"; function = "qup14"; }; qup_spi15_default: qup-spi15-default-state { pins = "gpio81", "gpio82", "gpio83", "gpio84"; function = "qup15"; }; qup_uart0_default: qup-uart0-default-state { qup_uart0_tx: tx-pins { pins = "gpio2"; function = "qup0"; }; qup_uart0_rx: rx-pins { pins = "gpio3"; function = "qup0"; }; }; qup_uart1_default: qup-uart1-default-state { qup_uart1_tx: tx-pins { pins = "gpio19"; function = "qup1"; }; qup_uart1_rx: rx-pins { pins = "gpio20"; function = "qup1"; }; }; qup_uart2_default: qup-uart2-default-state { qup_uart2_tx: tx-pins { pins = "gpio29"; function = "qup2"; }; qup_uart2_rx: rx-pins { pins = "gpio30"; function = "qup2"; }; }; qup_uart3_default: qup-uart3-default-state { qup_uart3_tx: tx-pins { pins = "gpio43"; function = "qup3"; }; qup_uart3_rx: rx-pins { pins = "gpio44"; function = "qup3"; }; }; qup_uart3_4pin: qup-uart3-4pin-state { qup_uart3_4pin_cts: cts-pins { pins = "gpio41"; function = "qup3"; }; qup_uart3_4pin_rts_tx: rts-tx-pins { pins = "gpio42", "gpio43"; function = "qup3"; }; qup_uart3_4pin_rx: rx-pins { pins = "gpio44"; function = "qup3"; }; }; qup_uart4_default: qup-uart4-default-state { qup_uart4_tx: tx-pins { pins = "gpio91"; function = "qup4"; }; qup_uart4_rx: rx-pins { pins = "gpio92"; function = "qup4"; }; }; qup_uart5_default: qup-uart5-default-state { qup_uart5_tx: tx-pins { pins = "gpio87"; function = "qup5"; }; qup_uart5_rx: rx-pins { pins = "gpio88"; function = "qup5"; }; }; qup_uart6_default: qup-uart6-default-state { qup_uart6_tx: tx-pins { pins = "gpio47"; function = "qup6"; }; qup_uart6_rx: rx-pins { pins = "gpio48"; function = "qup6"; }; }; qup_uart6_4pin: qup-uart6-4pin-state { qup_uart6_4pin_cts: cts-pins { pins = "gpio45"; function = "qup6"; bias-pull-down; }; qup_uart6_4pin_rts_tx: rts-tx-pins { pins = "gpio46", "gpio47"; function = "qup6"; drive-strength = <2>; bias-disable; }; qup_uart6_4pin_rx: rx-pins { pins = "gpio48"; function = "qup6"; bias-pull-up; }; }; qup_uart7_default: qup-uart7-default-state { qup_uart7_tx: tx-pins { pins = "gpio95"; function = "qup7"; }; qup_uart7_rx: rx-pins { pins = "gpio96"; function = "qup7"; }; }; qup_uart8_default: qup-uart8-default-state { qup_uart8_tx: tx-pins { pins = "gpio67"; function = "qup8"; }; qup_uart8_rx: rx-pins { pins = "gpio68"; function = "qup8"; }; }; qup_uart9_default: qup-uart9-default-state { qup_uart9_tx: tx-pins { pins = "gpio4"; function = "qup9"; }; qup_uart9_rx: rx-pins { pins = "gpio5"; function = "qup9"; }; }; qup_uart10_default: qup-uart10-default-state { qup_uart10_tx: tx-pins { pins = "gpio53"; function = "qup10"; }; qup_uart10_rx: rx-pins { pins = "gpio54"; function = "qup10"; }; }; qup_uart11_default: qup-uart11-default-state { qup_uart11_tx: tx-pins { pins = "gpio33"; function = "qup11"; }; qup_uart11_rx: rx-pins { pins = "gpio34"; function = "qup11"; }; }; qup_uart12_default: qup-uart12-default-state { qup_uart12_tx: tx-pins { pins = "gpio51"; function = "qup0"; }; qup_uart12_rx: rx-pins { pins = "gpio52"; function = "qup0"; }; }; qup_uart13_default: qup-uart13-default-state { qup_uart13_tx: tx-pins { pins = "gpio107"; function = "qup13"; }; qup_uart13_rx: rx-pins { pins = "gpio108"; function = "qup13"; }; }; qup_uart14_default: qup-uart14-default-state { qup_uart14_tx: tx-pins { pins = "gpio31"; function = "qup14"; }; qup_uart14_rx: rx-pins { pins = "gpio32"; function = "qup14"; }; }; qup_uart15_default: qup-uart15-default-state { qup_uart15_tx: tx-pins { pins = "gpio83"; function = "qup15"; }; qup_uart15_rx: rx-pins { pins = "gpio84"; function = "qup15"; }; }; quat_mi2s_sleep: quat-mi2s-sleep-state { pins = "gpio58", "gpio59"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; quat_mi2s_active: quat-mi2s-active-state { pins = "gpio58", "gpio59"; function = "qua_mi2s"; drive-strength = <8>; bias-disable; output-high; }; quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { pins = "gpio60"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { pins = "gpio60"; function = "qua_mi2s"; drive-strength = <8>; bias-disable; }; quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { pins = "gpio61"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { pins = "gpio61"; function = "qua_mi2s"; drive-strength = <8>; bias-disable; }; quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { pins = "gpio62"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { pins = "gpio62"; function = "qua_mi2s"; drive-strength = <8>; bias-disable; }; quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { pins = "gpio63"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { pins = "gpio63"; function = "qua_mi2s"; drive-strength = <8>; bias-disable; }; }; mss_pil: remoteproc@4080000 { compatible = "qcom,sdm845-mss-pil"; reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; reg-names = "qdsp6", "rmb"; interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>, <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, <&gcc GCC_MSS_SNOC_AXI_CLK>, <&gcc GCC_MSS_MFAB_AXIS_CLK>, <&gcc GCC_PRNG_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "bus", "mem", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng", "xo"; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; resets = <&aoss_reset AOSS_CC_MSS_RESTART>, <&pdc_reset PDC_MODEM_SYNC_RESET>; reset-names = "mss_restart", "pdc_reset"; qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; power-domains = <&rpmhpd SDM845_CX>, <&rpmhpd SDM845_MX>, <&rpmhpd SDM845_MSS>; power-domain-names = "cx", "mx", "mss"; status = "disabled"; mba { memory-region = <&mba_region>; }; mpss { memory-region = <&mpss_region>; }; metadata { memory-region = <&mdata_mem>; }; glink-edge { interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,remote-pid = <1>; mboxes = <&apss_shared 12>; }; }; gpucc: clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; reg = <0 0x05090000 0 0x9000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; }; slpi_pas: remoteproc@5c00000 { compatible = "qcom,sdm845-slpi-pas"; reg = <0 0x5c00000 0 0x4000>; interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; qcom,qmp = <&aoss_qmp>; power-domains = <&rpmhpd SDM845_LCX>, <&rpmhpd SDM845_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; qcom,smem-states = <&slpi_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; label = "dsps"; qcom,remote-pid = <3>; mboxes = <&apss_shared 24>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "sdsp"; qcom,non-secure-domain; qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>; memory-region = <&fastrpc_mem>; #address-cells = <1>; #size-cells = <0>; compute-cb@0 { compatible = "qcom,fastrpc-compute-cb"; reg = <0>; }; }; }; }; stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { stm_out: endpoint { remote-endpoint = <&funnel0_in7>; }; }; }; }; funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel0_out: endpoint { remote-endpoint = <&merge_funnel_in0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@7 { reg = <7>; funnel0_in7: endpoint { remote-endpoint = <&stm_out>; }; }; }; }; funnel@6043000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06043000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel2_out: endpoint { remote-endpoint = <&merge_funnel_in2>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@5 { reg = <5>; funnel2_in5: endpoint { remote-endpoint = <&apss_merge_funnel_out>; }; }; }; }; funnel@6045000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06045000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { merge_funnel_out: endpoint { remote-endpoint = <&etf_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; merge_funnel_in0: endpoint { remote-endpoint = <&funnel0_out>; }; }; port@2 { reg = <2>; merge_funnel_in2: endpoint { remote-endpoint = <&funnel2_out>; }; }; }; }; replicator@6046000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x06046000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { replicator_out: endpoint { remote-endpoint = <&etr_in>; }; }; }; in-ports { port { replicator_in: endpoint { remote-endpoint = <&etf_out>; }; }; }; }; etf@6047000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06047000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { etf_out: endpoint { remote-endpoint = <&replicator_in>; }; }; }; in-ports { port { etf_in: endpoint { remote-endpoint = <&merge_funnel_out>; }; }; }; }; etr@6048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06048000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,scatter-gather; in-ports { port { etr_in: endpoint { remote-endpoint = <&replicator_out>; }; }; }; }; etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; cpu = <&cpu0>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm0_out: endpoint { remote-endpoint = <&apss_funnel_in0>; }; }; }; }; etm@7140000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07140000 0 0x1000>; cpu = <&cpu1>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm1_out: endpoint { remote-endpoint = <&apss_funnel_in1>; }; }; }; }; etm@7240000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07240000 0 0x1000>; cpu = <&cpu2>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm2_out: endpoint { remote-endpoint = <&apss_funnel_in2>; }; }; }; }; etm@7340000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07340000 0 0x1000>; cpu = <&cpu3>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm3_out: endpoint { remote-endpoint = <&apss_funnel_in3>; }; }; }; }; etm@7440000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07440000 0 0x1000>; cpu = <&cpu4>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm4_out: endpoint { remote-endpoint = <&apss_funnel_in4>; }; }; }; }; etm@7540000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07540000 0 0x1000>; cpu = <&cpu5>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm5_out: endpoint { remote-endpoint = <&apss_funnel_in5>; }; }; }; }; etm@7640000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07640000 0 0x1000>; cpu = <&cpu6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm6_out: endpoint { remote-endpoint = <&apss_funnel_in6>; }; }; }; }; etm@7740000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07740000 0 0x1000>; cpu = <&cpu7>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; out-ports { port { etm7_out: endpoint { remote-endpoint = <&apss_funnel_in7>; }; }; }; }; funnel@7800000 { /* APSS Funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07800000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_funnel_out: endpoint { remote-endpoint = <&apss_merge_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; apss_funnel_in0: endpoint { remote-endpoint = <&etm0_out>; }; }; port@1 { reg = <1>; apss_funnel_in1: endpoint { remote-endpoint = <&etm1_out>; }; }; port@2 { reg = <2>; apss_funnel_in2: endpoint { remote-endpoint = <&etm2_out>; }; }; port@3 { reg = <3>; apss_funnel_in3: endpoint { remote-endpoint = <&etm3_out>; }; }; port@4 { reg = <4>; apss_funnel_in4: endpoint { remote-endpoint = <&etm4_out>; }; }; port@5 { reg = <5>; apss_funnel_in5: endpoint { remote-endpoint = <&etm5_out>; }; }; port@6 { reg = <6>; apss_funnel_in6: endpoint { remote-endpoint = <&etm6_out>; }; }; port@7 { reg = <7>; apss_funnel_in7: endpoint { remote-endpoint = <&etm7_out>; }; }; }; }; funnel@7810000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07810000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_merge_funnel_out: endpoint { remote-endpoint = <&funnel2_in5>; }; }; }; in-ports { port { apss_merge_funnel_in: endpoint { remote-endpoint = <&apss_funnel_out>; }; }; }; }; sdhc_2: mmc@8804000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0xa0 0xf>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&sdhc2_opp_table>; status = "disabled"; sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-9600000 { opp-hz = /bits/ 64 <9600000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-19200000 { opp-hz = /bits/ 64 <19200000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-201500000 { opp-hz = /bits/ 64 <201500000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; }; qspi: spi@88df000 { compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; reg = <0 0x088df000 0 0x600>; iommus = <&apps_smmu 0x160 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qspi_opp_table>; status = "disabled"; }; slim: slim-ngd@171c0000 { compatible = "qcom,slim-ngd-v2.1.0"; reg = <0 0x171c0000 0 0x2c000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; dmas = <&slimbam 3>, <&slimbam 4>; dma-names = "rx", "tx"; iommus = <&apps_smmu 0x1806 0x0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; lmh_cluster1: lmh@17d70800 { compatible = "qcom,sdm845-lmh"; reg = <0 0x17d70800 0 0x400>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; cpus = <&cpu4>; qcom,lmh-temp-arm-millicelsius = <65000>; qcom,lmh-temp-low-millicelsius = <94500>; qcom,lmh-temp-high-millicelsius = <95000>; interrupt-controller; #interrupt-cells = <1>; }; lmh_cluster0: lmh@17d78800 { compatible = "qcom,sdm845-lmh"; reg = <0 0x17d78800 0 0x400>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; cpus = <&cpu0>; qcom,lmh-temp-arm-millicelsius = <65000>; qcom,lmh-temp-low-millicelsius = <94500>; qcom,lmh-temp-high-millicelsius = <95000>; interrupt-controller; #interrupt-cells = <1>; }; usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e2000 0 0x400>; status = "disabled"; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; nvmem-cells = <&qusb2p_hstx_trim>; }; usb_2_hsphy: phy@88e3000 { compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; nvmem-cells = <&qusb2s_hstx_trim>; }; usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sdm845-qmp-usb3-dp-phy"; reg = <0 0x088e8000 0 0x3000>; status = "disabled"; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; clock-names = "aux", "ref", "com_aux", "usb3_pipe", "cfg_ahb"; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; #phy-cells = <1>; orientation-switch; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_1_qmpphy_out: endpoint { }; }; port@1 { reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { remote-endpoint = <&usb_1_dwc3_ss>; }; }; port@2 { reg = <2>; usb_1_qmpphy_dp_in: endpoint { remote-endpoint = <&dp_out>; }; }; }; }; usb_2_qmpphy: phy@88eb000 { compatible = "qcom,sdm845-qmp-usb3-uni-phy"; reg = <0 0x088eb000 0 0x1000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, <&gcc GCC_USB3_SEC_CLKREF_CLK>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "com_aux", "pipe"; clock-output-names = "usb3_uni_phy_pipe_clk_src"; #clock-cells = <0>; #phy-cells = <0>; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB3PHY_PHY_SEC_BCR>; reset-names = "phy", "phy_phy"; status = "disabled"; }; usb_1: usb@a6f8800 { compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB30_PRIM_BCR>; interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x740 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,parkmode-disable-ss-quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; usb_1_dwc3_hs: endpoint { }; }; port@1 { reg = <1>; usb_1_dwc3_ss: endpoint { remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; }; }; usb_2: usb@a8f8800 { compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_SLEEP_CLK>, <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <150000000>; interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; resets = <&gcc GCC_USB30_SEC_BCR>; interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_2_dwc3: usb@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x760 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,parkmode-disable-ss-quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; }; venus: video-codec@aa00000 { compatible = "qcom,sdm845-venus-v2"; reg = <0 0x0aa00000 0 0xff000>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&videocc VENUS_GDSC>, <&videocc VCODEC0_GDSC>, <&videocc VCODEC1_GDSC>, <&rpmhpd SDM845_CX>; power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; operating-points-v2 = <&venus_opp_table>; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; clock-names = "core", "iface", "bus", "vcodec0_core", "vcodec0_bus", "vcodec1_core", "vcodec1_bus"; iommus = <&apps_smmu 0x10a0 0x8>, <&apps_smmu 0x10b0 0x0>; memory-region = <&venus_mem>; interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; interconnect-names = "video-mem", "cpu-cfg"; status = "disabled"; video-core0 { compatible = "venus-decoder"; }; video-core1 { compatible = "venus-encoder"; }; venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-320000000 { opp-hz = /bits/ 64 <320000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-380000000 { opp-hz = /bits/ 64 <380000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-444000000 { opp-hz = /bits/ 64 <444000000>; required-opps = <&rpmhpd_opp_nom>; }; opp-533000097 { opp-hz = /bits/ 64 <533000097>; required-opps = <&rpmhpd_opp_turbo>; }; }; }; videocc: clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0 0x0ab00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; }; camss: camss@acb3000 { compatible = "qcom,sdm845-camss"; reg = <0 0x0acb3000 0 0x1000>, <0 0x0acba000 0 0x1000>, <0 0x0acc8000 0 0x1000>, <0 0x0ac65000 0 0x1000>, <0 0x0ac66000 0 0x1000>, <0 0x0ac67000 0 0x1000>, <0 0x0ac68000 0 0x1000>, <0 0x0acaf000 0 0x4000>, <0 0x0acb6000 0 0x4000>, <0 0x0acc4000 0 0x4000>; reg-names = "csid0", "csid1", "csid2", "csiphy0", "csiphy1", "csiphy2", "csiphy3", "vfe0", "vfe1", "vfe_lite"; interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csid0", "csid1", "csid2", "csiphy0", "csiphy1", "csiphy2", "csiphy3", "vfe0", "vfe1", "vfe_lite"; power-domains = <&clock_camcc IFE_0_GDSC>, <&clock_camcc IFE_1_GDSC>, <&clock_camcc TITAN_TOP_GDSC>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_CPAS_AHB_CLK>, <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY0_CLK>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY1_CLK>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY2_CLK>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, <&clock_camcc CAM_CC_CSIPHY3_CLK>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMERA_AXI_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK>, <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK>, <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, <&clock_camcc CAM_CC_IFE_LITE_CLK>, <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; clock-names = "camnoc_axi", "cpas_ahb", "cphy_rx_src", "csi0", "csi0_src", "csi1", "csi1_src", "csi2", "csi2_src", "csiphy0", "csiphy0_timer", "csiphy0_timer_src", "csiphy1", "csiphy1_timer", "csiphy1_timer_src", "csiphy2", "csiphy2_timer", "csiphy2_timer_src", "csiphy3", "csiphy3_timer", "csiphy3_timer_src", "gcc_camera_ahb", "gcc_camera_axi", "slow_ahb_src", "soc_ahb", "vfe0_axi", "vfe0", "vfe0_cphy_rx", "vfe0_src", "vfe1_axi", "vfe1", "vfe1_cphy_rx", "vfe1_src", "vfe_lite", "vfe_lite_cphy_rx", "vfe_lite_src"; iommus = <&apps_smmu 0x0808 0x0>, <&apps_smmu 0x0810 0x8>, <&apps_smmu 0x0c08 0x0>, <&apps_smmu 0x0c10 0x8>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; }; port@1 { reg = <1>; }; port@2 { reg = <2>; }; port@3 { reg = <3>; }; }; }; cci: cci@ac4a000 { compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; reg = <0 0x0ac4a000 0 0x4000>; interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; power-domains = <&clock_camcc TITAN_TOP_GDSC>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, <&clock_camcc CAM_CC_CPAS_AHB_CLK>, <&clock_camcc CAM_CC_CCI_CLK>, <&clock_camcc CAM_CC_CCI_CLK_SRC>; clock-names = "camnoc_axi", "soc_ahb", "slow_ahb_src", "cpas_ahb", "cci", "cci_src"; assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_CCI_CLK>; assigned-clock-rates = <80000000>, <37500000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cci0_default &cci1_default>; pinctrl-1 = <&cci0_sleep &cci1_sleep>; status = "disabled"; cci_i2c0: i2c-bus@0 { reg = <0>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; cci_i2c1: i2c-bus@1 { reg = <1>; clock-frequency = <1000000>; #address-cells = <1>; #size-cells = <0>; }; }; clock_camcc: clock-controller@ad00000 { compatible = "qcom,sdm845-camcc"; reg = <0 0x0ad00000 0 0x10000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; }; mdss: display-subsystem@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; power-domains = <&dispcc MDSS_GDSC>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "core"; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <1>; interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "mdp0-mem", "mdp1-mem"; iommus = <&apps_smmu 0x880 0x8>, <&apps_smmu 0xc80 0x8>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; mdss_mdp: display-controller@ae01000 { compatible = "qcom,sdm845-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SDM845_CX>; interrupt-parent = <&mdss>; interrupts = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf0_out: endpoint { remote-endpoint = <&dp_in>; }; }; port@1 { reg = <1>; dpu_intf1_out: endpoint { remote-endpoint = <&mdss_dsi0_in>; }; }; port@2 { reg = <2>; dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; }; mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-19200000 { opp-hz = /bits/ 64 <19200000>; required-opps = <&rpmhpd_opp_min_svs>; }; opp-171428571 { opp-hz = /bits/ 64 <171428571>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-344000000 { opp-hz = /bits/ 64 <344000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss_dp: displayport-controller@ae90000 { status = "disabled"; compatible = "qcom,sdm845-dp"; reg = <0 0x0ae90000 0 0x200>, <0 0x0ae90200 0 0x200>, <0 0x0ae90400 0 0x600>, <0 0x0ae90a00 0 0x600>, <0 0x0ae91000 0 0x600>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; operating-points-v2 = <&dp_opp_table>; power-domains = <&rpmhpd SDM845_CX>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dp_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; }; port@1 { reg = <1>; dp_out: endpoint { remote-endpoint = <&usb_1_qmpphy_dp_in>; }; }; }; dp_opp_table: opp-table { compatible = "operating-points-v2"; opp-162000000 { opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss_dsi0: dsi@ae94000 { compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; phys = <&mdss_dsi0_phy>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; mdss_dsi0_out: endpoint { }; }; }; }; mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94a00 0 0x1e0>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; status = "disabled"; }; mdss_dsi1: dsi@ae96000 { compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; phys = <&mdss_dsi1_phy>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dsi1_in: endpoint { remote-endpoint = <&dpu_intf2_out>; }; }; port@1 { reg = <1>; mdss_dsi1_out: endpoint { }; }; }; }; mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-10nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, <0 0x0ae96a00 0 0x10e>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; status = "disabled"; }; }; gpu: gpu@5000000 { compatible = "qcom,adreno-630.2", "qcom,adreno"; reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; reg-names = "kgsl_3d0_reg_memory", "cx_mem"; /* * Look ma, no clocks! The GPU clocks and power are * controlled entirely by the GMU */ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; #cooling-cells = <2>; interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; status = "disabled"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-710000000 { opp-hz = /bits/ 64 <710000000>; opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; opp-peak-kBps = <7216000>; }; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; opp-peak-kBps = <7216000>; }; opp-596000000 { opp-hz = /bits/ 64 <596000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; opp-peak-kBps = <6220000>; }; opp-520000000 { opp-hz = /bits/ 64 <520000000>; opp-level = <RPMH_REGULATOR_LEVEL_NOM>; opp-peak-kBps = <6220000>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; opp-peak-kBps = <4068000>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; opp-peak-kBps = <2724000>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; opp-peak-kBps = <1648000>; }; }; }; adreno_smmu: iommu@5040000 { compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0 0x05040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "bus", "iface"; power-domains = <&gpucc GPU_CX_GDSC>; }; gmu: gmu@506a000 { compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; reg = <0 0x0506a000 0 0x30000>, <0 0x0b280000 0 0x10000>, <0 0x0b480000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc"; power-domains = <&gpucc GPU_CX_GDSC>, <&gpucc GPU_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5>; operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; }; }; dispcc: clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "gcc_disp_gpll0_div_clk_src", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_byteclk", "dsi1_phy_pll_out_dsiclk", "dp_link_clk_divsel_ten", "dp_vco_divided_clk_src_mux"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; pdc_intc: interrupt-controller@b220000 { compatible = "qcom,sdm845-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; pdc_reset: reset-controller@b2e0000 { compatible = "qcom,sdm845-pdc-global"; reg = <0 0x0b2e0000 0 0x20000>; #reset-cells = <1>; }; tsens0: thermal-sensor@c263000 { compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <13>; interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <8>; interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; aoss_reset: reset-controller@c2a0000 { compatible = "qcom,sdm845-aoss-cc"; reg = <0 0x0c2a0000 0 0x31000>; #reset-cells = <1>; }; aoss_qmp: power-management@c300000 { compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; mboxes = <&apss_shared 0>; #clock-cells = <0>; cx_cdev: cx { #cooling-cells = <2>; }; ebi_cdev: ebi { #cooling-cells = <2>; }; }; sram@c3f0000 { compatible = "qcom,sdm845-rpmh-stats"; reg = <0 0x0c3f0000 0 0x400>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, <0 0x0c600000 0 0x2000000>, <0 0x0e600000 0 0x100000>, <0 0x0e700000 0 0xa0000>, <0 0x0c40a000 0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; sram@14680000 { compatible = "qcom,sdm845-imem", "syscon", "simple-mfd"; reg = <0 0x14680000 0 0x40000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x14680000 0x40000>; pil-reloc@3f94c { compatible = "qcom,pil-reloc-info"; reg = <0x3f94c 0xc8>; }; }; apps_smmu: iommu@15000000 { compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x80000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; }; anoc_1_tbu: tbu@150c5000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150c5000 0x0 0x1000>; interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; qcom,stream-id-range = <&apps_smmu 0x0 0x400>; }; anoc_2_tbu: tbu@150c9000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150c9000 0x0 0x1000>; interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; qcom,stream-id-range = <&apps_smmu 0x400 0x400>; }; mnoc_hf_0_tbu: tbu@150cd000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150cd000 0x0 0x1000>; interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; qcom,stream-id-range = <&apps_smmu 0x800 0x400>; }; mnoc_hf_1_tbu: tbu@150d1000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150d1000 0x0 0x1000>; interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; }; mnoc_sf_0_tbu: tbu@150d5000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150d5000 0x0 0x1000>; interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; }; compute_dsp_tbu: tbu@150d9000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150d9000 0x0 0x1000>; interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; }; adsp_tbu: tbu@150dd000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150dd000 0x0 0x1000>; interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; }; anoc_1_pcie_tbu: tbu@150e1000 { compatible = "qcom,sdm845-tbu"; reg = <0x0 0x150e1000 0x0 0x1000>; clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; }; lpasscc: clock-controller@17014000 { compatible = "qcom,sdm845-lpasscc"; reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; reg-names = "cc", "qdsp6ss"; #clock-cells = <1>; status = "disabled"; }; gladiator_noc: interconnect@17900000 { compatible = "qcom,sdm845-gladiator-noc"; reg = <0 0x17900000 0 0xd080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; watchdog@17980000 { compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; reg = <0 0x17980000 0 0x1000>; clocks = <&sleep_clk>; interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; }; apss_shared: mailbox@17990000 { compatible = "qcom,sdm845-apss-shared"; reg = <0 0x17990000 0 0x1000>; #mbox-cells = <1>; }; apps_rsc: rsc@179c0000 { compatible = "qcom,sdm845-rpmh-apps-rsc", "qcom,rpmh-rsc"; label = "apps_rsc"; reg = <0 0x179c0000 0 0x10000>, <0 0x179d0000 0 0x10000>, <0 0x179e0000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 1>; power-domains = <&cluster_pd>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; rpmhcc: clock-controller { compatible = "qcom,sdm845-rpmh-clk"; #clock-cells = <1>; clock-names = "xo"; clocks = <&xo_board>; }; rpmhpd: power-controller { compatible = "qcom,sdm845-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; }; rpmhpd_opp_min_svs: opp2 { opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; rpmhpd_opp_low_svs: opp3 { opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; rpmhpd_opp_svs: opp4 { opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; rpmhpd_opp_svs_l1: opp5 { opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; }; rpmhpd_opp_nom: opp6 { opp-level = <RPMH_REGULATOR_LEVEL_NOM>; }; rpmhpd_opp_nom_l1: opp7 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; }; rpmhpd_opp_nom_l2: opp8 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; }; rpmhpd_opp_turbo: opp9 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; }; rpmhpd_opp_turbo_l1: opp10 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; }; }; }; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; #interrupt-cells = <3>; interrupt-controller; reg = <0 0x17a00000 0 0x10000>, /* GICD */ <0 0x17a60000 0 0x100000>; /* GICR * 8 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; msi-controller@17a40000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0 0x17a40000 0 0x20000>; status = "disabled"; }; }; slimbam: dma-controller@17184000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; num-channels = <23>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <1>; qcom,num-ees = <4>; iommus = <&apps_smmu 0x1806 0x0>; }; timer@17c90000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c90000 0 0x1000>; frame@17ca0000 { frame-number = <0>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17ca0000 0x1000>, <0x17cb0000 0x1000>; }; frame@17cc0000 { frame-number = <1>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17cc0000 0x1000>; status = "disabled"; }; frame@17cd0000 { frame-number = <2>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17cd0000 0x1000>; status = "disabled"; }; frame@17ce0000 { frame-number = <3>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17ce0000 0x1000>; status = "disabled"; }; frame@17cf0000 { frame-number = <4>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17cf0000 0x1000>; status = "disabled"; }; frame@17d00000 { frame-number = <5>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17d00000 0x1000>; status = "disabled"; }; frame@17d10000 { frame-number = <6>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17d10000 0x1000>; status = "disabled"; }; }; osm_l3: interconnect@17d41000 { compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3"; reg = <0 0x17d41000 0 0x1400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; cpufreq_hw: cpufreq@17d43000 { compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; #clock-cells = <1>; }; wifi: wifi@18800000 { compatible = "qcom,wcn3990-wifi"; status = "disabled"; reg = <0 0x18800000 0 0x800000>; reg-names = "membase"; memory-region = <&wlan_msa_mem>; clock-names = "cxo_ref_clk_pin"; clocks = <&rpmhcc RPMH_RF_CLK2>; interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x0040 0x1>; }; }; sound: sound { }; thermal-zones { cpu0-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 1>; trips { cpu0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu0_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu1-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 2>; trips { cpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu1_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu2-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 3>; trips { cpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu2_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu3-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 4>; trips { cpu3_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu3_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu4-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 7>; trips { cpu4_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu5-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 8>; trips { cpu5_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu6-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 9>; trips { cpu6_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; cpu7-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 10>; trips { cpu7_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; aoss0-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 0>; trips { aoss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; cluster0-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 5>; trips { cluster0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cluster0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; cluster1-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 6>; trips { cluster1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cluster1_crit: cluster1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; }; }; }; gpu-top-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 11>; cooling-maps { map0 { trip = <&gpu_top_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu_top_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; gpu-bottom-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens0 12>; cooling-maps { map0 { trip = <&gpu_bottom_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { gpu_bottom_alert0: trip-point0 { temperature = <85000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { temperature = <110000>; hysteresis = <1000>; type = "critical"; }; }; }; aoss1-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 0>; trips { aoss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; q6-modem-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 1>; trips { q6_modem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; mem-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 2>; trips { mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; wlan-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 3>; trips { wlan_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; q6-hvx-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 4>; trips { q6_hvx_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; camera-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 5>; trips { camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; video-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 6>; trips { video_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; modem-thermal { polling-delay-passive = <250>; thermal-sensors = <&tsens1 7>; trips { modem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; }; }; [Verzeichnis aufwärts0.74unsichere VerbindungÜbersetzung europäischer Sprachen durch Browser2026-04-29] |
2026-05-26