Quelle  sdx75.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * SDX75 SoC device tree source
 *
 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 */

#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sdx75.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
 #address-cells = <2>;
 #size-cells = <2>;
 interrupt-parent = <&intc>;

 chosen: chosen { };

 clocks {
  xo_board: xo-board {
   compatible = "fixed-clock";
   clock-frequency = <76800000>;
   #clock-cells = <0>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   clock-frequency = <32764>;
   #clock-cells = <0>;
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x0>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   next-level-cache = <&l2_0>;

   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x100>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   next-level-cache = <&l2_100>;

   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x200>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   next-level-cache = <&l2_200>;

   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x300>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   next-level-cache = <&l2_300>;

   l2_300: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   cpu_off: cpu-sleep-0 {
    compatible = "arm,idle-state";
    entry-latency-us = <235>;
    exit-latency-us = <428>;
    min-residency-us = <1774>;
    arm,psci-suspend-param = <0x40000003>;
    local-timer-stop;
   };

   cpu_rail_off: cpu-rail-sleep-1 {
    compatible = "arm,idle-state";
    entry-latency-us = <800>;
    exit-latency-us = <750>;
    min-residency-us = <4090>;
    arm,psci-suspend-param = <0x40000004>;
    local-timer-stop;
   };

  };

  domain-idle-states {
   cluster_sleep_0: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41000044>;
    entry-latency-us = <1050>;
    exit-latency-us = <2500>;
    min-residency-us = <5309>;
   };

   cluster_sleep_1: cluster-sleep-1 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41001344>;
    entry-latency-us = <2761>;
    exit-latency-us = <3964>;
    min-residency-us = <8467>;
   };

   cluster_sleep_2: cluster-sleep-2 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100b344>;
    entry-latency-us = <2793>;
    exit-latency-us = <4023>;
    min-residency-us = <9826>;
   };
  };
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sdx75", "qcom,scm";
  };
 };

 clk_virt: interconnect-0 {
  compatible = "qcom,sdx75-clk-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
  clocks = <&rpmhcc RPMH_QPIC_CLK>;
 };

 mc_virt: interconnect-1 {
  compatible = "qcom,sdx75-mc-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 memory@80000000 {
  device_type = "memory";
  reg = <0x0 0x80000000 0x0 0x0>;
 };

 pmu {
  compatible = "arm,cortex-a55-pmu";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_off &cpu_rail_off>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_off &cpu_rail_off>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_off &cpu_rail_off>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_off &cpu_rail_off>;
  };

  cluster_pd: power-domain-cpu-cluster0 {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_0 &cluster_sleep_1 &cluster_sleep_2>;
  };
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  gunyah_hyp_mem: gunyah-hyp@80000000 {
   reg = <0x0 0x80000000 0x0 0x800000>;
   no-map;
  };

  hyp_elf_package_mem: hyp-elf-package@80800000 {
   reg = <0x0 0x80800000 0x0 0x200000>;
   no-map;
  };

  access_control_db_mem: access-control-db@81380000 {
   reg = <0x0 0x81380000 0x0 0x80000>;
   no-map;
  };

  qteetz_mem: qteetz@814e0000 {
   reg = <0x0 0x814e0000 0x0 0x2a0000>;
   no-map;
  };

  trusted_apps_mem: trusted-apps@81780000 {
   reg = <0x0 0x81780000 0x0 0xa00000>;
   no-map;
  };

  xbl_ramdump_mem: xbl-ramdump@87a00000 {
   reg = <0x0 0x87a00000 0x0 0x1c0000>;
   no-map;
  };

  cpucp_fw_mem: cpucp-fw@87c00000 {
   reg = <0x0 0x87c00000 0x0 0x100000>;
   no-map;
  };

  xbl_dtlog_mem: xbl-dtlog@87d00000 {
   reg = <0x0 0x87d00000 0x0 0x40000>;
   no-map;
  };

  xbl_sc_mem: xbl-sc@87d40000 {
   reg = <0x0 0x87d40000 0x0 0x40000>;
   no-map;
  };

  modem_efs_shared_mem: modem-efs-shared@87d80000 {
   reg = <0x0 0x87d80000 0x0 0x10000>;
   no-map;
  };

  aop_image_mem: aop-image@87e00000 {
   reg = <0x0 0x87e00000 0x0 0x20000>;
   no-map;
  };

  smem_mem: smem@87e20000 {
   reg = <0x0 0x87e20000 0x0 0xc0000>;
   no-map;
  };

  aop_cmd_db_mem: aop-cmd-db@87ee0000 {
   compatible = "qcom,cmd-db";
   reg = <0x0 0x87ee0000 0x0 0x20000>;
   no-map;
  };

  aop_config_mem: aop-config@87f00000 {
   reg = <0x0 0x87f00000 0x0 0x20000>;
   no-map;
  };

  ipa_fw_mem: ipa-fw@87f20000 {
   reg = <0x0 0x87f20000 0x0 0x10000>;
   no-map;
  };

  secdata_mem: secdata@87f30000 {
   reg = <0x0 0x87f30000 0x0 0x1000>;
   no-map;
  };

  tme_crashdump_mem: tme-crashdump@87f31000 {
   reg = <0x0 0x87f31000 0x0 0x40000>;
   no-map;
  };

  tme_log_mem: tme-log@87f71000 {
   reg = <0x0 0x87f71000 0x0 0x4000>;
   no-map;
  };

  uefi_log_mem: uefi-log@87f75000 {
   reg = <0x0 0x87f75000 0x0 0x10000>;
   no-map;
  };

  qdss_mem: qdss@88500000 {
   reg = <0x0 0x88500000 0x0 0x300000>;
   no-map;
  };

  qlink_logging_mem: qlink-logging@88800000 {
   reg = <0x0 0x88800000 0x0 0x300000>;
   no-map;
  };

  audio_heap_mem: audio-heap@88b00000 {
   compatible = "shared-dma-pool";
   reg = <0x0 0x88b00000 0x0 0x400000>;
   no-map;
  };

  mpss_dsm_mem_2: mpss-dsm-2@88f00000 {
   reg = <0x0 0x88f00000 0x0 0x2500000>;
   no-map;
  };

  mpss_dsm_mem: mpss-dsm@8b400000 {
   reg = <0x0 0x8b400000 0x0 0x2b80000>;
   no-map;
  };

  q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
   reg = <0x0 0x8df80000 0x0 0x80000>;
   no-map;
  };

  mpssadsp_mem: mpssadsp@8e000000 {
   reg = <0x0 0x8e000000 0x0 0xf100000>;
   no-map;
  };

  gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
   reg = <0x0 0xbdb00000 0x0 0x2000000>;
   no-map;
  };

  smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
   reg = <0x0 0xbfb00000 0x0 0x100000>;
   no-map;
  };

  hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
   reg = <0x0 0xbfc00000 0x0 0x400000>;
   no-map;
  };
 };

 smp2p-modem {
  compatible = "qcom,smp2p";
  qcom,smem = <435>, <428>;
  interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_MPSS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <1>;

  smp2p_modem_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_modem_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  ipa_smp2p_out: ipa-ap-to-modem {
   qcom,entry-name = "ipa";
   #qcom,smem-state-cells = <1>;
  };

  ipa_smp2p_in: ipa-modem-to-ap {
   qcom,entry-name = "ipa";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smem: smem {
  compatible = "qcom,smem";
  memory-region = <&smem_mem>;
  hwlocks = <&tcsr_mutex 3>;
 };

 soc: soc@0 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;

  gcc: clock-controller@80000 {
   compatible = "qcom,sdx75-gcc";
   reg = <0x0 0x0080000 0x0 0x1f7400>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&sleep_clk>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
  };

  ipcc: mailbox@408000 {
   compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
   reg = <0 0x00408000 0 0x1000>;
   interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-controller;
   #interrupt-cells = <3>;
   #mbox-cells = <2>;
  };

  gpi_dma: dma-controller@900000 {
   compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
   reg = <0x0 0x00900000 0x0 0x60000>;
   #dma-cells = <3>;
   interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0x7f>;
   iommus = <&apps_smmu 0xf6 0x0>;
   status = "disabled";
  };

  qupv3_id_0: geniqup@9c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x009c0000 0x0 0x2000>;
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   clock-names = "m-ahb",
          "s-ahb";
   iommus = <&apps_smmu 0xe3 0x0>;
   interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
      &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "qup-core";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   status = "disabled";

   i2c0: i2c@980000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00980000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_i2c0_data_clk>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
           <&gpi_dma 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi0: spi@980000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00980000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
           <&gpi_dma 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart1: serial@984000 {
    compatible = "qcom,geni-debug-uart";
    reg = <0x0 0x00984000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config";
    interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qupv3_se1_2uart_active>;
    pinctrl-1 = <&qupv3_se1_2uart_sleep>;
    pinctrl-names = "default",
      "sleep";
    status = "disabled";
   };

   i2c2: i2c@988000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00988000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_i2c2_data_clk>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
           <&gpi_dma 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi2: spi@988000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00988000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
           <&gpi_dma 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   i2c3: i2c@98c000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x0098c000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_i2c3_data_clk>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
           <&gpi_dma 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi3: spi@98c000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x0098c000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
           <&gpi_dma 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart4: serial@990000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00990000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c5: i2c@994000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00994000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_i2c5_data_clk>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
           <&gpi_dma 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   i2c6: i2c@998000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00998000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_i2c6_data_clk>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
           <&gpi_dma 1 6 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi6: spi@998000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00998000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
           <&gpi_dma 1 6 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   i2c7: i2c@99c000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x0099c000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_i2c7_data_clk>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
           <&gpi_dma 1 7 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi7: spi@99c000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x0099c000 0x0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
           <&gpi_dma 1 7 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };
  };

  usb_hsphy: phy@ff4000 {
   compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
   reg = <0x0 0x00ff4000 0x0 0x154>;
   #phy-cells = <0>;

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "ref";

   resets = <&gcc GCC_QUSB2PHY_BCR>;

   status = "disabled";
  };

  usb_qmpphy: phy@ff6000 {
   compatible = "qcom,sdx75-qmp-usb3-uni-phy";
   reg = <0x0 0x00ff6000 0x0 0x2000>;

   clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
     <&gcc GCC_USB2_CLKREF_EN>,
     <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
     <&gcc GCC_USB3_PHY_PIPE_CLK>;
   clock-names = "aux",
          "ref",
          "cfg_ahb",
          "pipe";

   power-domains = <&gcc GCC_USB3_PHY_GDSC>;

   resets = <&gcc GCC_USB3_PHY_BCR>,
     <&gcc GCC_USB3PHY_PHY_BCR>;
   reset-names = "phy",
          "phy_phy";

   #clock-cells = <0>;
   clock-output-names = "usb3_uni_phy_pipe_clk_src";

   #phy-cells = <0>;

   status = "disabled";
  };

  system_noc: interconnect@1640000 {
   compatible = "qcom,sdx75-system-noc";
   reg = <0x0 0x01640000 0x0 0x4b400>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  pcie_anoc: interconnect@16c0000 {
   compatible = "qcom,sdx75-pcie-anoc";
   reg = <0x0 0x016c0000 0x0 0x14200>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  qpic_bam: dma-controller@1c9c000 {
   compatible = "qcom,bam-v1.7.0";
   reg = <0x0 0x01c9c000 0x0 0x1c000>;
   interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&rpmhcc RPMH_QPIC_CLK>;
   clock-names = "bam_clk";
   #dma-cells = <1>;
   qcom,ee = <0>;
   qcom,controlled-remotely;
   iommus = <&apps_smmu 0x100 0x3>;
   dma-coherent;
   status = "disabled";
  };

  qpic_nand: nand-controller@1cc8000 {
   compatible = "qcom,sdx75-nand", "qcom,sdx55-nand";
   reg = <0x0 0x01cc8000 0x0 0x10000>;
   #address-cells = <1>;
   #size-cells = <0>;
   clocks = <&rpmhcc RPMH_QPIC_CLK>,
     <&sleep_clk>;
   clock-names = "core",
          "aon";
   dmas = <&qpic_bam 0>,
          <&qpic_bam 1>,
          <&qpic_bam 2>;
   dma-names = "tx",
        "rx",
        "cmd";
   iommus = <&apps_smmu 0x100 0x3>;
   status = "disabled";
  };

  tcsr_mutex: hwlock@1f40000 {
   compatible = "qcom,tcsr-mutex";
   reg = <0x0 0x01f40000 0x0 0x40000>;
   #hwlock-cells = <1>;
  };

  tcsr: syscon@1fc0000 {
   compatible = "qcom,sdx75-tcsr", "syscon";
   reg = <0x0 0x01fc0000 0x0 0x30000>;
  };

  remoteproc_mpss: remoteproc@4080000 {
   compatible = "qcom,sdx75-mpss-pas";
   reg = <0 0x04080000 0 0x10000>;

   interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "wdog",
       "fatal",
       "ready",
       "handover",
       "stop-ack",
       "shutdown-ack";

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "xo";

   power-domains = <&rpmhpd RPMHPD_CX>,
     <&rpmhpd RPMHPD_MSS>;
   power-domain-names = "cx",
          "mss";

   memory-region = <&mpssadsp_mem>, <&q6_mpss_dtb_mem>,
     <&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
     <&qlink_logging_mem>;

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&smp2p_modem_out 0>;
   qcom,smem-state-names = "stop";

   status = "disabled";

   glink-edge {
    interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
            IPCC_MPROC_SIGNAL_PING
            IRQ_TYPE_EDGE_RISING>;
    mboxes = <&ipcc IPCC_CLIENT_MPSS
      IPCC_MPROC_SIGNAL_PING>;
    label = "mpss";
    qcom,remote-pid = <1>;
   };
  };

  sdhc: mmc@8804000 {
   compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
   reg = <0x0 0x08804000 0x0 0x1000>;

   interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hc_irq",
       "pwr_irq";

   clocks = <&gcc GCC_SDCC1_AHB_CLK>,
     <&gcc GCC_SDCC1_APPS_CLK>,
     <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "iface",
          "core",
          "xo";
   iommus = <&apps_smmu 0x00a0 0x0>;
   qcom,dll-config = <0x0007442c>;
   qcom,ddr-config = <0x80040868>;
   power-domains = <&rpmhpd RPMHPD_CX>;
   operating-points-v2 = <&sdhc1_opp_table>;

   interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
     <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
   interconnect-names = "sdhc-ddr",
          "cpu-sdhc";
   bus-width = <4>;
   dma-coherent;

   /* Forbid SDR104/SDR50 - broken hw! */
   sdhci-caps-mask = <0x3 0>;

   status = "disabled";

   sdhc1_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-100000000 {
     opp-hz = /bits/ 64 <100000000>;
     required-opps = <&rpmhpd_opp_low_svs>;
    };

    opp-384000000 {
     opp-hz = /bits/ 64 <384000000>;
     required-opps = <&rpmhpd_opp_nom>;
    };
   };
  };

  usb: usb@a6f8800 {
   compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
   reg = <0x0 0x0a6f8800 0x0 0x400>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
     <&gcc GCC_USB30_MASTER_CLK>,
     <&gcc GCC_USB30_MSTR_AXI_CLK>,
     <&gcc GCC_USB30_SLEEP_CLK>,
     <&gcc GCC_USB30_MOCK_UTMI_CLK>;
   clock-names = "cfg_noc",
          "core",
          "iface",
          "sleep",
          "mock_utmi";

   assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
       <&gcc GCC_USB30_MASTER_CLK>;
   assigned-clock-rates = <19200000>, <200000000>;

   interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
           <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
           <&pdc 9 IRQ_TYPE_EDGE_RISING>,
           <&pdc 10 IRQ_TYPE_EDGE_RISING>,
           <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "pwr_event",
       "hs_phy_irq",
       "dm_hs_phy_irq",
       "dp_hs_phy_irq",
       "ss_phy_irq";

   power-domains = <&gcc GCC_USB30_GDSC>;

   resets = <&gcc GCC_USB30_BCR>;

   interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
      &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "usb-ddr",
          "apps-usb";

   status = "disabled";

   usb_dwc3: usb@a600000 {
    compatible = "snps,dwc3";
    reg = <0x0 0x0a600000 0x0 0xcd00>;
    interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
    iommus = <&apps_smmu 0x80 0x0>;
    snps,dis_u2_susphy_quirk;
    snps,dis_enblslpm_quirk;
    snps,dis-u1-entry-quirk;
    snps,dis-u2-entry-quirk;
    phys = <&usb_hsphy>,
           <&usb_qmpphy>;
    phy-names = "usb2-phy",
         "usb3-phy";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;

      usb_1_dwc3_hs: endpoint {
      };
     };

     port@1 {
      reg = <1>;

      usb_1_dwc3_ss: endpoint {
      };
     };
    };
   };
  };

  pdc: interrupt-controller@b220000 {
   compatible = "qcom,sdx75-pdc", "qcom,pdc";
   reg = <0x0 0xb220000 0x0 0x30000>,
         <0x0 0x174000f0 0x0 0x64>;
   qcom,pdc-ranges = <0 147 52>,
       <52 266 32>,
       <84 500 59>;
   #interrupt-cells = <2>;
   interrupt-parent = <&intc>;
   interrupt-controller;
  };

  aoss_qmp: power-management@c310000 {
   compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
   reg = <0 0x0c310000 0 0x1000>;
   interrupt-parent = <&ipcc>;
   interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
           IRQ_TYPE_EDGE_RISING>;
   mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;

   #clock-cells = <0>;
  };

  spmi_bus: spmi@c400000 {
   compatible = "qcom,spmi-pmic-arb";
   reg = <0x0 0x0c400000 0x0 0x3000>,
         <0x0 0x0c500000 0x0 0x400000>,
         <0x0 0x0c440000 0x0 0x80000>,
         <0x0 0x0c4c0000 0x0 0x10000>,
         <0x0 0x0c42d000 0x0 0x4000>;
   reg-names = "core",
        "chnls",
        "obsrvr",
        "intr",
        "cnfg";
   interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "periph_irq";
   qcom,ee = <0>;
   qcom,channel = <0>;
   qcom,bus-id = <0>;
   #address-cells = <2>;
   #size-cells = <0>;
   interrupt-controller;
   #interrupt-cells = <4>;
  };

  tlmm: pinctrl@f000000 {
   compatible = "qcom,sdx75-tlmm";
   reg = <0x0 0x0f000000 0x0 0x400000>;
   interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
   gpio-controller;
   #gpio-cells = <2>;
   gpio-ranges = <&tlmm 0 0 133>;
   interrupt-controller;
   #interrupt-cells = <2>;
   wakeup-parent = <&pdc>;

   qup_i2c0_data_clk: qup-i2c0-data-clk-state {
    /* SDA, SCL */
    pins = "gpio8", "gpio9";
    function = "qup_se0";
    drive-strength = <2>;
    bias-pull-up;
   };

   qup_i2c2_data_clk: qup-i2c2-data-clk-state {
    /* SDA, SCL */
    pins = "gpio14", "gpio15";
    function = "qup_se2";
    drive-strength = <2>;
    bias-pull-up;
   };

   qup_i2c3_data_clk: qup-i2c3-data-clk-state {
    /* SDA, SCL */
    pins = "gpio52", "gpio53";
    function = "qup_se3";
    drive-strength = <2>;
    bias-pull-up;
   };

   qup_i2c5_data_clk: qup-i2c5-data-clk-state {
    /* SDA, SCL */
    pins = "gpio110", "gpio111";
    function = "qup_se5";
    drive-strength = <2>;
    bias-pull-up;
   };

   qup_i2c6_data_clk: qup-i2c6-data-clk-state {
    /* SDA, SCL */
    pins = "gpio112", "gpio113";
    function = "qup_se6";
    drive-strength = <2>;
    bias-pull-up;
   };

   qup_i2c7_data_clk: qup-i2c7-data-clk-state {
    /* SDA, SCL */
    pins = "gpio116", "gpio117";
    function = "qup_se7";
    drive-strength = <2>;
    bias-pull-up;
   };

   qup_spi0_cs: qup-spi0-cs-state {
    pins = "gpio11";
    function = "qup_se0";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi0_data_clk: qup-spi0-data-clk-state {
    /* MISO, MOSI, CLK */
    pins = "gpio8", "gpio9", "gpio10";
    function = "qup_se0";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi2_cs: qup-spi2-cs-state {
    pins = "gpio17";
    function = "qup_se2";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi2_data_clk: qup-spi2-data-clk-state {
    /* MISO, MOSI, CLK */
    pins = "gpio14", "gpio15", "gpio16";
    function = "qup_se2";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi3_cs: qup-spi3-cs-state {
    pins = "gpio55";
    function = "qup_se3";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi3_data_clk: qup-spi3-data-clk-state {
    /* MISO, MOSI, CLK */
    pins = "gpio52", "gpio53", "gpio54";
    function = "qup_se3";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi6_cs: qup-spi6-cs-state {
    pins = "gpio115";
    function = "qup_se6";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi6_data_clk: qup-spi6-data-clk-state {
    /* MISO, MOSI, CLK */
    pins = "gpio112", "gpio113", "gpio114";
    function = "qup_se6";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi7_cs: qup-spi7-cs-state {
    pins = "gpio119";
    function = "qup_se7";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_spi7_data_clk: qup-spi7-data-clk-state {
    /* MISO, MOSI, CLK */
    pins = "gpio116", "gpio117", "gpio118";
    function = "qup_se7";
    drive-strength = <6>;
    bias-pull-down;
   };

   qup_uart4_cts_rts: qup-uart4-cts-rts-state {
    /* CTS, RTS */
    pins = "gpio52", "gpio53";
    function = "qup_se3";
    drive-strength = <2>;
    bias-pull-down;
   };

   qup_uart4_default: qup-uart4-default-state {
    /* TX, RX */
    pins = "gpio54", "gpio55";
    function = "qup_se3";
    drive-strength = <2>;
    bias-pull-up;
   };

   qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
    tx-pins {
     pins = "gpio12";
     function = "qup_se1_l2_mira";
     drive-strength = <2>;
     bias-disable;
    };

    rx-pins {
     pins = "gpio13";
     function = "qup_se1_l3_mira";
     drive-strength = <2>;
     bias-disable;
    };
   };

   qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
    pins = "gpio12", "gpio13";
    function = "gpio";
    drive-strength = <2>;
    bias-pull-down;
   };

   sdc1_default: sdc1-default-state {
    clk-pins {
     pins = "sdc1_clk";
     drive-strength = <16>;
     bias-disable;
    };

    cmd-pins {
     pins = "sdc1_cmd";
     drive-strength = <10>;
     bias-pull-up;
    };

    data-pins {
     pins = "sdc1_data";
     drive-strength = <10>;
     bias-pull-up;
    };
   };

   sdc1_sleep: sdc1-sleep-state {
    clk-pins {
     pins = "sdc1_clk";
     drive-strength = <2>;
     bias-disable;
    };

    cmd-pins {
     pins = "sdc1_cmd";
     drive-strength = <2>;
     bias-pull-up;
    };

    data-pins {
     pins = "sdc1_data";
     drive-strength = <2>;
     bias-pull-up;
    };
   };
  };

  apps_smmu: iommu@15000000 {
   compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
   reg = <0x0 0x15000000 0x0 0x40000>;
   #iommu-cells = <2>;
   #global-interrupts = <2>;
   dma-coherent;
   interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
  };

  intc: interrupt-controller@17200000 {
   compatible = "arm,gic-v3";
   #interrupt-cells = <3>;
   interrupt-controller;
   #redistributor-regions = <1>;
   redistributor-stride = <0x0 0x20000>;
   reg = <0x0 0x17200000 0x0 0x10000>,
         <0x0 0x17260000 0x0 0x80000>;
   interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  };

  timer@17420000 {
   compatible = "arm,armv7-timer-mem";
   reg = <0x0 0x17420000 0x0 0x1000>;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0 0 0x20000000>;

   frame@17421000 {
    reg = <0x17421000 0x1000>,
          <0x17422000 0x1000>;
    frame-number = <0>;
    interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
   };

   frame@17423000 {
    reg = <0x17423000 0x1000>;
    frame-number = <1>;
    interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17425000 {
    reg = <0x17425000 0x1000>;
    frame-number = <2>;
    interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17427000 {
    reg = <0x17427000 0x1000>;
    frame-number = <3>;
    interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@17429000 {
    reg = <0x17429000 0x1000>;
    frame-number = <4>;
    interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@1742b000 {
    reg = <0x1742b000 0x1000>;
    frame-number = <5>;
    interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };

   frame@1742d000 {
    reg = <0x1742d000 0x1000>;
    frame-number = <6>;
    interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    status = "disabled";
   };
  };

  apps_rsc: rsc@17a00000 {
   label = "apps_rsc";
   compatible = "qcom,rpmh-rsc";
   reg = <0x0 0x17a00000 0x0 0x10000>,
         <0x0 0x17a10000 0x0 0x10000>,
         <0x0 0x17a20000 0x0 0x10000>;
   reg-names = "drv-0", "drv-1", "drv-2";
   interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

   power-domains = <&cluster_pd>;
   qcom,tcs-offset = <0xd00>;
   qcom,drv-id = <2>;
   qcom,tcs-config = <ACTIVE_TCS    3>,
       <SLEEP_TCS     2>,
       <WAKE_TCS      2>,
       <CONTROL_TCS   0>;

   apps_bcm_voter: bcm-voter {
    compatible = "qcom,bcm-voter";
   };

   rpmhcc: clock-controller {
    compatible = "qcom,sdx75-rpmh-clk";
    clocks = <&xo_board>;
    clock-names = "xo";
    #clock-cells = <1>;
   };

   rpmhpd: power-controller {
    compatible = "qcom,sdx75-rpmhpd";
    #power-domain-cells = <1>;
    operating-points-v2 = <&rpmhpd_opp_table>;

    rpmhpd_opp_table: opp-table {
     compatible = "operating-points-v2";

     rpmhpd_opp_ret: opp-16 {
      opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
     };

     rpmhpd_opp_min_svs: opp-48 {
      opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
     };

     rpmhpd_opp_low_svs: opp-64 {
      opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
     };

     rpmhpd_opp_svs: opp-128 {
      opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
     };

     rpmhpd_opp_svs_l1: opp-192 {
      opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
     };

     rpmhpd_opp_nom: opp-256 {
      opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
     };

     rpmhpd_opp_nom_l1: opp-320 {
      opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
     };

     rpmhpd_opp_nom_l2: opp-336 {
      opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
     };

     rpmhpd_opp_turbo: opp-384 {
      opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
     };

     rpmhpd_opp_turbo_l1: opp-416 {
      opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
     };
    };
   };
  };

  cpufreq_hw: cpufreq@17d91000 {
   compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
   reg = <0x0 0x17d91000 0x0 0x1000>;
   reg-names = "freq-domain0";
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GPLL0>;
   clock-names = "xo",
          "alternate";
   interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "dcvsh-irq-0";
   #freq-domain-cells = <1>;
   #clock-cells = <1>;
  };

  dc_noc: interconnect@190e0000 {
   compatible = "qcom,sdx75-dc-noc";
   reg = <0x0 0x190e0000 0x0 0x8200>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  gem_noc: interconnect@19100000 {
   compatible = "qcom,sdx75-gem-noc";
   reg = <0x0 0x19100000 0x0 0x34080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
        <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
        <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
        <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 };
};