Quelle  eyeq6h.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
/*
 * Copyright 2024 Mobileye Vision Technologies Ltd.
 */

#include <dt-bindings/interrupt-controller/mips-gic.h>

#include <dt-bindings/clock/mobileye,eyeq5-clk.h>

/ {
 #address-cells = <2>;
 #size-cells = <2>;
 cpus {
  #address-cells = <1>;
  #size-cells = <0>;
  cpu@0 {
   device_type = "cpu";
   compatible = "img,i6500";
   reg = <0>;
   clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
  };
 };

 aliases {
  serial0 = &uart0;
 };

 cpu_intc: interrupt-controller {
  compatible = "mti,cpu-interrupt-controller";
  interrupt-controller;
  #address-cells = <0>;
  #interrupt-cells = <1>;
 };

 coherency-manager {
  compatible = "mobileye,eyeq6-cm";
 };

 xtal: clock-30000000 {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <30000000>;
 };

 soc: soc {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  olb_acc: system-controller@d2003000 {
   compatible = "mobileye,eyeq6h-acc-olb", "syscon";
   reg = <0x0 0xd2003000 0x0 0x1000>;
   #reset-cells = <1>;
   #clock-cells = <1>;
   clocks = <&xtal>;
   clock-names = "ref";
  };

  olb_central: system-controller@d3100000 {
   compatible = "mobileye,eyeq6h-central-olb", "syscon";
   reg = <0x0 0xd3100000 0x0 0x1000>;
   #clock-cells = <1>;
   clocks = <&xtal>;
   clock-names = "ref";
  };

  uart0: serial@d3331000 {
   compatible = "arm,pl011", "arm,primecell";
   reg = <0 0xd3331000 0x0 0x1000>;
   reg-io-width = <4>;
   interrupt-parent = <&gic>;
   interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;
   clock-names = "uartclk", "apb_pclk";
  };

  pinctrl_west: pinctrl@d3337000 {
   compatible = "pinctrl-single";
   reg = <0x0 0xd3337000 0x0 0xb0>;
   #pinctrl-cells = <1>;
   pinctrl-single,register-width = <32>;
   pinctrl-single,function-mask = <0xffff>;
  };

  olb_west: system-controller@d3338000 {
   compatible = "mobileye,eyeq6h-west-olb", "syscon";
   reg = <0x0 0xd3338000 0x0 0x1000>;
   #reset-cells = <1>;
   #clock-cells = <1>;
   clocks = <&xtal>;
   clock-names = "ref";
  };

  pinctrl_east: pinctrl@d3357000 {
   compatible = "pinctrl-single";
   reg = <0x0 0xd3357000 0x0 0xb0>;
   #pinctrl-cells = <1>;
   pinctrl-single,register-width = <32>;
   pinctrl-single,function-mask = <0xffff>;
  };

  olb_east: system-controller@d3358000 {
   compatible = "mobileye,eyeq6h-east-olb", "syscon";
   reg = <0x0 0xd3358000 0x0 0x1000>;
   #reset-cells = <1>;
   #clock-cells = <1>;
   clocks = <&xtal>;
   clock-names = "ref";
  };

  emmc: mmc@d8010000 {
   compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
   reg = <0 0xd8010000 0x0 0x1000>;
   interrupt-parent = <&gic>;
   interrupts = <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&olb_south EQ6HC_SOUTH_DIV_EMMC>;
   bus-width = <8>;
   max-frequency = <200000000>;
   mmc-ddr-1_8v;
   sd-uhs-ddr50;
   mmc-hs200-1_8v;
   mmc-hs400-1_8v;
   mmc-hs400-enhanced-strobe;

   cdns,phy-input-delay-legacy = <4>;
   cdns,phy-input-delay-mmc-highspeed = <2>;
   cdns,phy-input-delay-mmc-ddr = <3>;
   cdns,phy-dll-delay-sdclk = <32>;
   cdns,phy-dll-delay-sdclk-hsmmc = <32>;
   cdns,phy-dll-delay-strobe = <32>;
  };

  olb_south: system-controller@d8013000 {
   compatible = "mobileye,eyeq6h-south-olb", "syscon";
   reg = <0x0 0xd8013000 0x0 0x1000>;
   #clock-cells = <1>;
   clocks = <&xtal>;
   clock-names = "ref";
  };

  pinctrl_south: pinctrl@d8014000 {
   compatible = "pinctrl-single";
   reg = <0x0 0xd8014000 0x0 0xf8>;
   #pinctrl-cells = <1>;
   pinctrl-single,register-width = <32>;
   pinctrl-single,function-mask = <0xffff>;
  };

  olb_ddr0: system-controller@e4080000 {
   compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";
   reg = <0x0 0xe4080000 0x0 0x1000>;
   #clock-cells = <1>;
   clocks = <&xtal>;
   clock-names = "ref";
  };

  olb_ddr1: system-controller@e4081000 {
   compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";
   reg = <0x0 0xe4081000 0x0 0x1000>;
   #clock-cells = <1>;
   clocks = <&xtal>;
   clock-names = "ref";
  };

  gic: interrupt-controller@f0920000 {
   compatible = "mti,gic";
   reg = <0x0 0xf0920000 0x0 0x20000>;
   interrupt-controller;
   #interrupt-cells = <3>;

   /*
    * Declare the interrupt-parent even though the mti,gic
    * binding doesn't require it, such that the kernel can
    * figure out that cpu_intc is the root interrupt
    * controller & should be probed first.
    */
   interrupt-parent = <&cpu_intc>;

   timer {
    compatible = "mti,gic-timer";
    interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
    clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
   };
  };
 };
};

#include "eyeq6h-pins.dtsi"