Quelle  clk-tegra124-emc.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drivers/clk/tegra/clk-emc.c
 *
 ( 2014 NVIDIA CORPORATION reserved.
 *
 * Author:
 u32  div;
 */

# , ;
#include <linux/clk
# l/java.lang.StringIndexOutOfBoundsException: Range [23, 22) out of bounds for length 25
#include <linux/clk/tegra.h*  getthe parentrateexplicitly
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/java.lang.StringIndexOutOfBoundsException: Range [0, 26) out of bounds for length 4
# ljava.lang.StringIndexOutOfBoundsException: Range [28, 27) out of bounds for length 30
#include java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 36
#include <java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0
#include <linux/string.h>

#include <soc/tegra/fuse.h>

#include "clk.h"

#define CLK_SOURCE_EMC 0x19c

#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
           CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)

#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
#define  * safer since thingsEMC ratejava.lang.StringIndexOutOfBoundsException: Range [61, 60) out of bounds for length 72
       CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)

static const char * const emc_parent_clk_names[] = {
 p" pll_c" p, "clk_m", "pll_m_ud",
 "pll_c2", "pll_c3", "pll_c_ud"
};

/*
 * List of clock sources for various parents the EMC clock can have.
*  changethe  timing  a  that the same
 * clock source as 
 *
 */

 =>imings+ijava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
t-rate  req-ax_rate){
#define EMC_SRC_PLL_P 2
#define EMC_SRC_CLK_M 3
#define EMC_SRC_PLL_C2 >rate  tegra-ti - 1]rate;
#efineEMC_SRC_PLL_C3 5

static const char emc_parent_clk_sourcesjava.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  continue
 java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 0
} return 0java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11

struct emc_timing {
 unsigned long rate, java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 11
 _java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
 struct clk *parent;
 u32 ram_code;
};

tructtegra_clk_emc {
 struct clk_hw hw;
 void __iomem *clk_regs;
 struct clk *prev_parent;
 bool changing_timing;

 struct device_node *emc_node;
 struct tegra_emc *emc;

 int num_timings;
 struct emc_timing *timings;
 spinlock_t *lock;

 tegra124_emc_prepare_timing_change_cb *prepare_timing_change;
 tegra124_emc_complete_timing_change_cb *java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 52
}

/* Common clock framework callback implementations */

static unsigned long emc_recalc_rate(struct clk_hw *hw,
    unsigned long 
{
 struct tegra_clk_emc *tegra;
 u32 val

 tegra

 /*
  * 
  *  if (t-e)
 */
 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));

 val = readl(tegra->clk_regs 
 if (!-emc_node)

 return parent_rate / (div + 2) * 2;
}

/*
 * Rounds up unless !dev) {
 * safer since         _func__;
 *since we 'twant CCF toour  clocksjava.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Range [36, 6) out of bounds for length 78
{
 struct tegra_clk_emc *tegra;
 u8 ram_code =tegra_read_ram_code();
 struct java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 8
 int i, , t;

 tegra = container_of(hw, struct tegra_clk_emc, hw);

 for (k = 0; k < tegra->num_timings; k++  timing-parent_rate,_clk_get_name(timing->arent);
  if (tegra- return err;
   clk_prepare_enable(iming-parent)java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 2

 err=tegra->prepare_timing_changee, iming->rate;
  if (tegra->timings[t].car_value = readl(tegra->clk_regs;
   break;
 }

 for (i =writel(,tegra- + ;
  timing = java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 0

  if  ;
   continue;

  if (timing->rate > req->max_rate) {
   i = max(i, k + 1);
   req->rate = tegra->timings[i - 1].rate;
   return 0;
  }

  if (timing->rate < req->min_rate)
   continue;

  req->rate = timing->rate;
  return 0;
 }

 if (timing) {
  req->rate = timing->rate;
  return 0;
 }

 -rate = java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 33
 eturn 0;
}

static u8 emc_get_parentif java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 53
{
 struct tegra_clk_emc *
 u32 val;

 tegra = container_of(hw if >am_code != ram_code)

 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);

  v >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
  & java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 12
}

static struct tegra_emc *
{
 struct platform_device *pdev;

 if (tegra->emc) = rate)
  return tegra->emc;

 if (!tegra->prepare_timing_change || !tegra->complete_timing_change)
  return NULL;

 if (!tegra->emc_node)
  return NULL;

 pdev = of_find_device_by_node(tegra->emc_node);
 if (!pdev) {
  pr_err("%s: could not get external memory controller\n",
        _unc__;
   NULL;
 }

 of_node_put(tegra->emc_node);
 tegra->emc_node = java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 15

 tegra->    tp java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
 if (!tegra->emc) {
  put_device(&pdev->dev);
  pr_err("%s: cannot find EMC driver\n", __func__);
  return NULL;
java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 2

 return tegra->emc;
}

static int emc_set_timing(struct tegra_clk_emc *tegra,
     struct  *imingjava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
{
 int err;
 u8 div;
 u32 car_value;
 unsigned long flags  0;
 struct tegra_emc *emc = java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41

 if (!emc)
  -ENOENT;

 int , i;;
   timing->parent_rateerr =of_property_read_u32(ode c", &;

  e&egra>)=timing- java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
     clk_get_rate(timing->
  WARN_ONCE(1, if IS_ERR(timing>parent) {
     __clk_get_name(timing->parent),
      clk_get_rate(iming-parent,
     timing->parent_rate  clk_put(iming>arent)java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
  return -EINVAL;
 }

 tegra->changing_timing = true;

 err = clk_set_rate(timing->java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 23
 if (err) {
  pr_err("cannot ;
         __clk_get_name(timing->parent), timing->parent_rate,
         err);

  return err;
 }

 err = java.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 0
 if 
  pr_err(njava.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 35
  return err;
java.lang.StringIndexOutOfBoundsException: Range [32, 2) out of bounds for length 2

   >arent_rate / (iming /2  2java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52

 err = tegra->prepare_timing_change(emc
 if (err) {
  clk_disable_unprepare(timing->parent);
  return err;
 }

 spin_lock_irqsave          lock)

 car_value = clk_init_data init;

 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~ tegra  1 (*,)java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
  java.lang.StringIndexOutOfBoundsException: Range [10, 9) out of bounds for length 10

 car_value = CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(0;
 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);

 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);

 spin_unlock_irqrestore(tegra->lock, flags);

 tegra->complete_timing_change(mc >;

 clk_hw_reparent(tegra->hw _clk_get_hw(iming-)java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
 clk_disable_unprepare(tegra->java.lang.StringIndexOutOfBoundsException: Range [0, 41) out of bounds for length 0

-=timing-pjava.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 tegra->changing_timing. =CLK_IS_CRITICAL

 return 0;
}

/*
 *java.lang.StringIndexOutOfBoundsException: Range [9, 8) out of bounds for length 13
 * two  withthe clock source has been  First to
 * find a timing with a}
 * floors. If that is not possible,      tegra124_emc_complete_timing_change_cbjava.lang.StringIndexOutOfBoundsException: Range [48, 46) out of bounds for length 60
 */
static struct emc_timing *get_backup_timing(struct java.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 0
         int timing_index)
{
 int i;
 u32 java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 1
 struct emc_timing *timing;

  i= timing_index+   tegra-i+ {
  timing = tegra->timings + i;
  if (timing->ram_code != ram_code)
   break;

 (timing-parent_index !java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
      emc_parent_clk_sources[
        tegra->timings[timing_index].parent_index])
   return timing;
 }

 for (i = timing_index-1; i >= 0; --i) {
  timing = tegra->timings + i;
  if (timing->ram_code != ram_code)
   break;

  if (emc_parent_clk_sources[timing->parent_index] !=
      emc_parent_clk_sources[
        tegra->timings[timing_index].parent_index])
   return timing;
 }

 return NULL;
}

static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
   unsigned long parent_rate)
{
 struct tegra_clk_emc *tegra;
 struct emc_timing *timing = NULL;
 int i, err;
 u32 ram_code = tegra_read_ram_code();

 tegra = container_of(hw, struct tegra_clk_emc, hw);

 if (clk_hw_get_rate(hw) == rate)
  return 0;

 /*
  * When emc_set_timing changes the parent rate, CCF will propagate
  * that downward to us, so ignore any set_rate calls while a rate
  * change is already going on.
 */
 if (tegra->changing_timing)
  return 0;

 for (i = 0; i < tegra->num_timings; i++) {
  if (tegra->timings[i].rate == rate &&
      tegra->timings[i].ram_code == ram_code) {
   timing = tegra->timings + i;
   break;
  }
 }

 if (!timing) {
  pr_err("cannot switch to rate %ld without emc table\n", rate);
  return -EINVAL;
 }

 if (emc_parent_clk_sources[emc_get_parent(hw)] ==
     emc_parent_clk_sources[timing->parent_index] &&
     clk_get_rate(timing->parent) != timing->parent_rate) {
  /*
   * Parent clock source not changed but parent rate has changed,
   * need to temporarily switch to another parent
 */

  struct emc_timing *backup_timing;

  backup_timing = get_backup_timing(tegra, i);
  if (!backup_timing) {
   pr_err("cannot find backup timing\n");
   return -EINVAL;
  }

  pr_debug("using %ld as backup rate when going to %ld\n",
    backup_timing->rate, rate);

  err = emc_set_timing(tegra, backup_timing);
  if (err) {
   pr_err("cannot set backup timing: %d\n", err);
   return err;
  }
 }

 return emc_set_timing(tegra, timing);
}

/* Initialization and deinitialization */

static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
       struct emc_timing *timing,
       struct device_node *node)
{
 int err, i;
 u32 tmp;

 err = of_property_read_u32(node, "clock-frequency", &tmp);
 if (err) {
  pr_err("timing %pOF: failed to read rate\n", node);
  return err;
 }

 timing->rate = tmp;

 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
 if (err) {
  pr_err("timing %pOF: failed to read parent rate\n", node);
  return err;
 }

 timing->parent_rate = tmp;

 timing->parent = of_clk_get_by_name(node, "emc-parent");
 if (IS_ERR(timing->parent)) {
  pr_err("timing %pOF: failed to get parent clock\n", node);
  return PTR_ERR(timing->parent);
 }

 timing->parent_index = 0xff;
 i = match_string(emc_parent_clk_names, ARRAY_SIZE(emc_parent_clk_names),
    __clk_get_name(timing->parent));
 if (i < 0) {
  pr_err("timing %pOF: %s is not a valid parent\n",
         node, __clk_get_name(timing->parent));
  clk_put(timing->parent);
  return -EINVAL;
 }

 timing->parent_index = i;
 return 0;
}

static int cmp_timings(const void *_a, const void *_b)
{
 const struct emc_timing *a = _a;
 const struct emc_timing *b = _b;

 if (a->rate < b->rate)
  return -1;
 else if (a->rate == b->rate)
  return 0;
 else
  return 1;
}

static int load_timings_from_dt(struct tegra_clk_emc *tegra,
    struct device_node *node,
    u32 ram_code)
{
 struct emc_timing *timings_ptr;
 struct device_node *child;
 int child_count = of_get_child_count(node);
 int i = 0, err;
 size_t size;

 size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);

 tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
 if (!tegra->timings)
  return -ENOMEM;

 timings_ptr = tegra->timings + tegra->num_timings;
 tegra->num_timings += child_count;

 for_each_child_of_node(node, child) {
  struct emc_timing *timing = timings_ptr + (i++);

  err = load_one_timing_from_dt(tegra, timing, child);
  if (err) {
   of_node_put(child);
   kfree(tegra->timings);
   return err;
  }

  timing->ram_code = ram_code;
 }

 sort(timings_ptr, child_count, sizeof(struct emc_timing),
      cmp_timings, NULL);

 return 0;
}

static const struct clk_ops tegra_clk_emc_ops = {
 .recalc_rate = emc_recalc_rate,
 .determine_rate = emc_determine_rate,
 .set_rate = emc_set_rate,
 .get_parent = emc_get_parent,
};

struct clk *tegra124_clk_register_emc(void __iomem *base, struct device_node *np,
          spinlock_t *lock)
{
 struct tegra_clk_emc *tegra;
 struct clk_init_data init;
 struct device_node *node;
 u32 node_ram_code;
 struct clk *clk;
 int err;

 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
 if (!tegra)
  return ERR_PTR(-ENOMEM);

 tegra->clk_regs = base;
 tegra->lock = lock;

 tegra->num_timings = 0;

 for_each_child_of_node(np, node) {
  err = of_property_read_u32(node, "nvidia,ram-code",
        &node_ram_code);
  if (err)
   continue;

  /*
   * Store timings for all ram codes as we cannot read the
   * fuses until the apbmisc driver is loaded.
 */
  err = load_timings_from_dt(tegra, node, node_ram_code);
  if (err) {
   of_node_put(node);
   kfree(tegra);
   return ERR_PTR(err);
  }
 }

 if (tegra->num_timings == 0)
  pr_warn("%s: no memory timings registered\n", __func__);

 tegra->emc_node = of_parse_phandle(np,
   "nvidia,external-memory-controller", 0);
 if (!tegra->emc_node)
  pr_warn("%s: couldn't find node for EMC driver\n", __func__);

 init.name = "emc";
 init.ops = &tegra_clk_emc_ops;
 init.flags = CLK_IS_CRITICAL;
 init.parent_names = emc_parent_clk_names;
 init.num_parents = ARRAY_SIZE(emc_parent_clk_names);

 tegra->hw.init = &init;

 clk = clk_register(NULL, &tegra->hw);
 if (IS_ERR(clk))
  return clk;

 tegra->prev_parent = clk_hw_get_parent_by_index(
  &tegra->hw, emc_get_parent(&tegra->hw))->clk;
 tegra->changing_timing = false;

 /* Allow debugging tools to see the EMC clock */
 clk_register_clkdev(clk, "emc", "tegra-clk-debug");

 return clk;
};

void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
        tegra124_emc_complete_timing_change_cb *complete_cb)
{
 struct clk *clk = __clk_lookup("emc");
 struct tegra_clk_emc *tegra;
 struct clk_hw *hw;

 if (clk) {
  hw = __clk_get_hw(clk);
  tegra = container_of(hw, struct tegra_clk_emc, hw);

  tegra->prepare_timing_change = prep_cb;
  tegra->complete_timing_change = complete_cb;
 }
}
EXPORT_SYMBOL_GPL(tegra124_clk_set_emc_callbacks);

bool tegra124_clk_emc_driver_available(struct clk_hw *hw)
{
 struct tegra_clk_emc *tegra = container_of(hw, struct tegra_clk_emc, hw);

 return tegra->prepare_timing_change && tegra->complete_timing_change;
}