Quelle  gfx_v8_0.c   Sprache: C

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/pci.h>

#include "amdgpu.h"
#include "amdgpu_gfx.h"
#include "amdgpu_ring.h"
#include "vi.h"
#include "vi_structs.h"
#include "vid.h"
#include "amdgpu_ucode.h"
#include "amdgpu_atombios.h"
#include "atombios_i2c.h"
#include "clearstate_vi.h"

#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"

#include "oss/oss_3_0_d.h"
#include "oss/oss_3_0_sh_mask.h"

#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
#include "gca/gfx_8_0_d.h"
#include "gca/gfx_8_0_enum.h"
#include "gca/gfx_8_0_sh_mask.h"

#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"

#include "smu/smu_7_1_3_d.h"

#include "ivsrcid/ivsrcid_vislands30.h"

#define GFX8_NUM_GFX_RINGS     1
#define GFX8_MEC_HPD_SIZE 4096

#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003

#define ARRAY_MODE(x)     ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
#define PIPE_CONFIG(x)     ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
#define TILE_SPLIT(x)     ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
#define MICRO_TILE_MODE_NEW(x)    ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
#define SAMPLE_SPLIT(x)     ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
#define BANK_WIDTH(x)     ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
#define BANK_HEIGHT(x)     ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
#define MACRO_TILE_ASPECT(x)    ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
#define NUM_BANKS(x)     ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)

#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L

/* BPM SERDES CMD */
#define SET_BPM_SERDES_CMD    1
#define CLE_BPM_SERDES_CMD    0

/* BPM Register Address*/
enum {
 BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
 BPM_REG_CGLS_ON,            /* ON/OFF CGLS: shall be controlled by RLC FW */
 BPM_REG_CGCG_OVERRIDE,      /* Set/Clear CGCG Override */
 BPM_REG_MGCG_OVERRIDE,      /* Set/Clear MGCG Override */
 BPM_REG_FGCG_OVERRIDE,      /* Set/Clear FGCG Override */
 BPM_REG_FGCG_MAX
};

#define RLC_FormatDirectRegListLength        14

MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");

MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
MODULE_FIRMWARE("amdgpu/stoney_me.bin");
MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");

MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
MODULE_FIRMWARE("amdgpu/tonga_me.bin");
MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");

MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
MODULE_FIRMWARE("amdgpu/topaz_me.bin");
MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");

MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
MODULE_FIRMWARE("amdgpu/fiji_me.bin");
MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");

MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");

MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");

MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");

MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
MODULE_FIRMWARE("amdgpu/vegam_me.bin");
MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");

static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
{
 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
};

static const u32 golden_settings_tonga_a11[] =
{
 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmGB_GPU_ID, 0x0000000f, 0x00000000,
 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
};

static const u32 tonga_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
};

static const u32 tonga_mgcg_cgcg_init[] =
{
 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
};

static const u32 golden_settings_vegam_a11[] =
{
 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
 mmSQ_CONFIG, 0x07f80000, 0x01180000,
 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
};

static const u32 vegam_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
};

static const u32 golden_settings_polaris11_a11[] =
{
 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
 mmSQ_CONFIG, 0x07f80000, 0x01180000,
 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
};

static const u32 polaris11_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
};

static const u32 golden_settings_polaris10_a11[] =
{
 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
 mmSQ_CONFIG, 0x07f80000, 0x07180000,
 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
};

static const u32 polaris10_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
};

static const u32 fiji_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
};

static const u32 golden_settings_fiji_a10[] =
{
 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
};

static const u32 fiji_mgcg_cgcg_init[] =
{
 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
};

static const u32 golden_settings_iceland_a11[] =
{
 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 mmGB_GPU_ID, 0x0000000f, 0x00000000,
 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
};

static const u32 iceland_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
};

static const u32 iceland_mgcg_cgcg_init[] =
{
 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
};

static const u32 cz_golden_settings_a11[] =
{
 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmGB_GPU_ID, 0x0000000f, 0x00000000,
 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
};

static const u32 cz_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
};

static const u32 cz_mgcg_cgcg_init[] =
{
 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
};

static const u32 stoney_golden_settings_a11[] =
{
 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 mmGB_GPU_ID, 0x0000000f, 0x00000000,
 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
};

static const u32 stoney_golden_common_all[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
};

static const u32 stoney_mgcg_cgcg_init[] =
{
 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
};


static const char * const sq_edc_source_names[] = {
 "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
 "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
 "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
 "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
 "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
 "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
};

static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);

#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK                    0x0000007fL
#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT                  0x00000000L

static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
{
 uint32_t data;

 switch (adev->asic_type) {
 case CHIP_TOPAZ:
  amdgpu_device_program_register_sequence(adev,
       iceland_mgcg_cgcg_init,
       ARRAY_SIZE(iceland_mgcg_cgcg_init));
  amdgpu_device_program_register_sequence(adev,
       golden_settings_iceland_a11,
       ARRAY_SIZE(golden_settings_iceland_a11));
  amdgpu_device_program_register_sequence(adev,
       iceland_golden_common_all,
       ARRAY_SIZE(iceland_golden_common_all));
  break;
 case CHIP_FIJI:
  amdgpu_device_program_register_sequence(adev,
       fiji_mgcg_cgcg_init,
       ARRAY_SIZE(fiji_mgcg_cgcg_init));
  amdgpu_device_program_register_sequence(adev,
       golden_settings_fiji_a10,
       ARRAY_SIZE(golden_settings_fiji_a10));
  amdgpu_device_program_register_sequence(adev,
       fiji_golden_common_all,
       ARRAY_SIZE(fiji_golden_common_all));
  break;

 case CHIP_TONGA:
  amdgpu_device_program_register_sequence(adev,
       tonga_mgcg_cgcg_init,
       ARRAY_SIZE(tonga_mgcg_cgcg_init));
  amdgpu_device_program_register_sequence(adev,
       golden_settings_tonga_a11,
       ARRAY_SIZE(golden_settings_tonga_a11));
  amdgpu_device_program_register_sequence(adev,
       tonga_golden_common_all,
       ARRAY_SIZE(tonga_golden_common_all));
  break;
 case CHIP_VEGAM:
  amdgpu_device_program_register_sequence(adev,
       golden_settings_vegam_a11,
       ARRAY_SIZE(golden_settings_vegam_a11));
  amdgpu_device_program_register_sequence(adev,
       vegam_golden_common_all,
       ARRAY_SIZE(vegam_golden_common_all));
  break;
 case CHIP_POLARIS11:
 case CHIP_POLARIS12:
  amdgpu_device_program_register_sequence(adev,
       golden_settings_polaris11_a11,
       ARRAY_SIZE(golden_settings_polaris11_a11));
  amdgpu_device_program_register_sequence(adev,
       polaris11_golden_common_all,
       ARRAY_SIZE(polaris11_golden_common_all));
  break;
 case CHIP_POLARIS10:
  amdgpu_device_program_register_sequence(adev,
       golden_settings_polaris10_a11,
       ARRAY_SIZE(golden_settings_polaris10_a11));
  amdgpu_device_program_register_sequence(adev,
       polaris10_golden_common_all,
       ARRAY_SIZE(polaris10_golden_common_all));
  data = RREG32_SMC(ixCG_ACLK_CNTL);
  data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK;
  data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;
  WREG32_SMC(ixCG_ACLK_CNTL, data);
  if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&
      ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
       (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
       (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {
   amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
   amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
  }
  break;
 case CHIP_CARRIZO:
  amdgpu_device_program_register_sequence(adev,
       cz_mgcg_cgcg_init,
       ARRAY_SIZE(cz_mgcg_cgcg_init));
  amdgpu_device_program_register_sequence(adev,
       cz_golden_settings_a11,
       ARRAY_SIZE(cz_golden_settings_a11));
  amdgpu_device_program_register_sequence(adev,
       cz_golden_common_all,
       ARRAY_SIZE(cz_golden_common_all));
  break;
 case CHIP_STONEY:
  amdgpu_device_program_register_sequence(adev,
       stoney_mgcg_cgcg_init,
       ARRAY_SIZE(stoney_mgcg_cgcg_init));
  amdgpu_device_program_register_sequence(adev,
       stoney_golden_settings_a11,
       ARRAY_SIZE(stoney_golden_settings_a11));
  amdgpu_device_program_register_sequence(adev,
       stoney_golden_common_all,
       ARRAY_SIZE(stoney_golden_common_all));
  break;
 default:
  break;
 }
}

static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
{
 struct amdgpu_device *adev = ring->adev;
 uint32_t tmp = 0;
 unsigned i;
 int r;

 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
 r = amdgpu_ring_alloc(ring, 3);
 if (r)
  return r;

 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
 amdgpu_ring_write(ring, 0xDEADBEEF);
 amdgpu_ring_commit(ring);

 for (i = 0; i < adev->usec_timeout; i++) {
  tmp = RREG32(mmSCRATCH_REG0);
  if (tmp == 0xDEADBEEF)
   break;
  udelay(1);
 }

 if (i >= adev->usec_timeout)
  r = -ETIMEDOUT;

 return r;
}

static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
 struct amdgpu_device *adev = ring->adev;
 struct amdgpu_ib ib;
 struct dma_fence *f = NULL;

 unsigned int index;
 uint64_t gpu_addr;
 uint32_t tmp;
 long r;

 r = amdgpu_device_wb_get(adev, &index);
 if (r)
  return r;

 gpu_addr = adev->wb.gpu_addr + (index * 4);
 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 memset(&ib, 0, sizeof(ib));

 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
 if (r)
  goto err1;

 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 ib.ptr[2] = lower_32_bits(gpu_addr);
 ib.ptr[3] = upper_32_bits(gpu_addr);
 ib.ptr[4] = 0xDEADBEEF;
 ib.length_dw = 5;

 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 if (r)
  goto err2;

 r = dma_fence_wait_timeout(f, false, timeout);
 if (r == 0) {
  r = -ETIMEDOUT;
  goto err2;
 } else if (r < 0) {
  goto err2;
 }

 tmp = adev->wb.wb[index];
 if (tmp == 0xDEADBEEF)
  r = 0;
 else
  r = -EINVAL;

err2:
 amdgpu_ib_free(&ib, NULL);
 dma_fence_put(f);
err1:
 amdgpu_device_wb_free(adev, index);
 return r;
}


static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
{
 amdgpu_ucode_release(&adev->gfx.pfp_fw);
 amdgpu_ucode_release(&adev->gfx.me_fw);
 amdgpu_ucode_release(&adev->gfx.ce_fw);
 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 amdgpu_ucode_release(&adev->gfx.mec_fw);
 if ((adev->asic_type != CHIP_STONEY) &&
     (adev->asic_type != CHIP_TOPAZ))
  amdgpu_ucode_release(&adev->gfx.mec2_fw);

 kfree(adev->gfx.rlc.register_list_format);
}

static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
{
 const char *chip_name;
 int err;
 struct amdgpu_firmware_info *info = NULL;
 const struct common_firmware_header *header = NULL;
 const struct gfx_firmware_header_v1_0 *cp_hdr;
 const struct rlc_firmware_header_v2_0 *rlc_hdr;
 unsigned int *tmp = NULL, i;

 DRM_DEBUG("\n");

 switch (adev->asic_type) {
 case CHIP_TOPAZ:
  chip_name = "topaz";
  break;
 case CHIP_TONGA:
  chip_name = "tonga";
  break;
 case CHIP_CARRIZO:
  chip_name = "carrizo";
  break;
 case CHIP_FIJI:
  chip_name = "fiji";
  break;
 case CHIP_STONEY:
  chip_name = "stoney";
  break;
 case CHIP_POLARIS10:
  chip_name = "polaris10";
  break;
 case CHIP_POLARIS11:
  chip_name = "polaris11";
  break;
 case CHIP_POLARIS12:
  chip_name = "polaris12";
  break;
 case CHIP_VEGAM:
  chip_name = "vegam";
  break;
 default:
  BUG();
 }

 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
  err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
        AMDGPU_UCODE_OPTIONAL,
        "amdgpu/%s_pfp_2.bin", chip_name);
  if (err == -ENODEV) {
   err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
         AMDGPU_UCODE_REQUIRED,
         "amdgpu/%s_pfp.bin", chip_name);
  }
 } else {
  err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
        AMDGPU_UCODE_REQUIRED,
        "amdgpu/%s_pfp.bin", chip_name);
 }
 if (err)
  goto out;
 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);

 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
  err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
        AMDGPU_UCODE_OPTIONAL,
        "amdgpu/%s_me_2.bin", chip_name);
  if (err == -ENODEV) {
   err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
         AMDGPU_UCODE_REQUIRED,
         "amdgpu/%s_me.bin", chip_name);
  }
 } else {
  err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
        AMDGPU_UCODE_REQUIRED,
        "amdgpu/%s_me.bin", chip_name);
 }
 if (err)
  goto out;
 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);

 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
  err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
        AMDGPU_UCODE_OPTIONAL,
        "amdgpu/%s_ce_2.bin", chip_name);
  if (err == -ENODEV) {
   err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
         AMDGPU_UCODE_REQUIRED,
         "amdgpu/%s_ce.bin", chip_name);
  }
 } else {
  err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
        AMDGPU_UCODE_REQUIRED,
        "amdgpu/%s_ce.bin", chip_name);
 }
 if (err)
  goto out;
 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);

 /*
 * Support for MCBP/Virtualization in combination with chained IBs is
 * formal released on feature version #46
 */
 if (adev->gfx.ce_feature_version >= 46 &&
     adev->gfx.pfp_feature_version >= 46) {
  adev->virt.chained_ib_support = true;
  DRM_INFO("Chained IB support enabled!\n");
 } else
  adev->virt.chained_ib_support = false;

 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
       AMDGPU_UCODE_REQUIRED,
       "amdgpu/%s_rlc.bin", chip_name);
 if (err)
  goto out;
 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);

 adev->gfx.rlc.save_and_restore_offset =
   le32_to_cpu(rlc_hdr->save_and_restore_offset);
 adev->gfx.rlc.clear_state_descriptor_offset =
   le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 adev->gfx.rlc.avail_scratch_ram_locations =
   le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 adev->gfx.rlc.reg_restore_list_size =
   le32_to_cpu(rlc_hdr->reg_restore_list_size);
 adev->gfx.rlc.reg_list_format_start =
   le32_to_cpu(rlc_hdr->reg_list_format_start);
 adev->gfx.rlc.reg_list_format_separate_start =
   le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 adev->gfx.rlc.starting_offsets_start =
   le32_to_cpu(rlc_hdr->starting_offsets_start);
 adev->gfx.rlc.reg_list_format_size_bytes =
   le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 adev->gfx.rlc.reg_list_size_bytes =
   le32_to_cpu(rlc_hdr->reg_list_size_bytes);

 adev->gfx.rlc.register_list_format =
   kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
     adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);

 if (!adev->gfx.rlc.register_list_format) {
  err = -ENOMEM;
  goto out;
 }

 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
  adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);

 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;

 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
  adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);

 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
  err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
        AMDGPU_UCODE_OPTIONAL,
        "amdgpu/%s_mec_2.bin", chip_name);
  if (err == -ENODEV) {
   err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
         AMDGPU_UCODE_REQUIRED,
         "amdgpu/%s_mec.bin", chip_name);
  }
 } else {
  err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
        AMDGPU_UCODE_REQUIRED,
        "amdgpu/%s_mec.bin", chip_name);
 }
 if (err)
  goto out;
 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);

 if ((adev->asic_type != CHIP_STONEY) &&
     (adev->asic_type != CHIP_TOPAZ)) {
  if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
   err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
         AMDGPU_UCODE_OPTIONAL,
         "amdgpu/%s_mec2_2.bin", chip_name);
   if (err == -ENODEV) {
    err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
          AMDGPU_UCODE_REQUIRED,
          "amdgpu/%s_mec2.bin", chip_name);
   }
  } else {
   err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
         AMDGPU_UCODE_REQUIRED,
         "amdgpu/%s_mec2.bin", chip_name);
  }
  if (!err) {
   cp_hdr = (const struct gfx_firmware_header_v1_0 *)
    adev->gfx.mec2_fw->data;
   adev->gfx.mec2_fw_version =
    le32_to_cpu(cp_hdr->header.ucode_version);
   adev->gfx.mec2_feature_version =
    le32_to_cpu(cp_hdr->ucode_feature_version);
  } else {
   err = 0;
   adev->gfx.mec2_fw = NULL;
  }
 }

 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 info->fw = adev->gfx.pfp_fw;
 header = (const struct common_firmware_header *)info->fw->data;
 adev->firmware.fw_size +=
  ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);

 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 info->fw = adev->gfx.me_fw;
 header = (const struct common_firmware_header *)info->fw->data;
 adev->firmware.fw_size +=
  ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);

 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 info->fw = adev->gfx.ce_fw;
 header = (const struct common_firmware_header *)info->fw->data;
 adev->firmware.fw_size +=
  ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);

 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 info->fw = adev->gfx.rlc_fw;
 header = (const struct common_firmware_header *)info->fw->data;
 adev->firmware.fw_size +=
  ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);

 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 info->fw = adev->gfx.mec_fw;
 header = (const struct common_firmware_header *)info->fw->data;
 adev->firmware.fw_size +=
  ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);

 /* we need account JT in */
 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 adev->firmware.fw_size +=
  ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);

 if (amdgpu_sriov_vf(adev)) {
  info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
  info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
  info->fw = adev->gfx.mec_fw;
  adev->firmware.fw_size +=
   ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
 }

 if (adev->gfx.mec2_fw) {
  info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
  info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
  info->fw = adev->gfx.mec2_fw;
  header = (const struct common_firmware_header *)info->fw->data;
  adev->firmware.fw_size +=
   ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 }

out:
 if (err) {
  dev_err(adev->dev, "gfx8: Failed to load firmware %s gfx firmware\n", chip_name);
  amdgpu_ucode_release(&adev->gfx.pfp_fw);
  amdgpu_ucode_release(&adev->gfx.me_fw);
  amdgpu_ucode_release(&adev->gfx.ce_fw);
  amdgpu_ucode_release(&adev->gfx.rlc_fw);
  amdgpu_ucode_release(&adev->gfx.mec_fw);
  amdgpu_ucode_release(&adev->gfx.mec2_fw);
 }
 return err;
}

static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
        volatile u32 *buffer)
{
 u32 count = 0;

 if (adev->gfx.rlc.cs_data == NULL)
  return;
 if (buffer == NULL)
  return;

 count = amdgpu_gfx_csb_preamble_start(buffer);
 count = amdgpu_gfx_csb_data_parser(adev, buffer, count);

 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);

 amdgpu_gfx_csb_preamble_end(buffer, count);
}

static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
{
 if (adev->asic_type == CHIP_CARRIZO)
  return 5;
 else
  return 4;
}

static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
{
 const struct cs_section_def *cs_data;
 int r;

 adev->gfx.rlc.cs_data = vi_cs_data;

 cs_data = adev->gfx.rlc.cs_data;

 if (cs_data) {
  /* init clear state block */
  r = amdgpu_gfx_rlc_init_csb(adev);
  if (r)
   return r;
 }

 if ((adev->asic_type == CHIP_CARRIZO) ||
     (adev->asic_type == CHIP_STONEY)) {
  adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
  r = amdgpu_gfx_rlc_init_cpt(adev);
  if (r)
   return r;
 }

 /* init spm vmid with 0xf */
 if (adev->gfx.rlc.funcs->update_spm_vmid)
  adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);

 return 0;
}

static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
{
 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
}

static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
{
 int r;
 u32 *hpd;
 size_t mec_hpd_size;

 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);

 /* take ownership of the relevant compute queues */
 amdgpu_gfx_compute_queue_acquire(adev);

 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
 if (mec_hpd_size) {
  r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
           AMDGPU_GEM_DOMAIN_VRAM |
           AMDGPU_GEM_DOMAIN_GTT,
           &adev->gfx.mec.hpd_eop_obj,
           &adev->gfx.mec.hpd_eop_gpu_addr,
           (void **)&hpd);
  if (r) {
   dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
   return r;
  }

  memset(hpd, 0, mec_hpd_size);

  amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
  amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 }

 return 0;
}

static const u32 vgpr_init_compute_shader[] =
{
 0x7e000209, 0x7e020208,
 0x7e040207, 0x7e060206,
 0x7e080205, 0x7e0a0204,
 0x7e0c0203, 0x7e0e0202,
 0x7e100201, 0x7e120200,
 0x7e140209, 0x7e160208,
 0x7e180207, 0x7e1a0206,
 0x7e1c0205, 0x7e1e0204,
 0x7e200203, 0x7e220202,
 0x7e240201, 0x7e260200,
 0x7e280209, 0x7e2a0208,
 0x7e2c0207, 0x7e2e0206,
 0x7e300205, 0x7e320204,
 0x7e340203, 0x7e360202,
 0x7e380201, 0x7e3a0200,
 0x7e3c0209, 0x7e3e0208,
 0x7e400207, 0x7e420206,
 0x7e440205, 0x7e460204,
 0x7e480203, 0x7e4a0202,
 0x7e4c0201, 0x7e4e0200,
 0x7e500209, 0x7e520208,
 0x7e540207, 0x7e560206,
 0x7e580205, 0x7e5a0204,
 0x7e5c0203, 0x7e5e0202,
 0x7e600201, 0x7e620200,
 0x7e640209, 0x7e660208,
 0x7e680207, 0x7e6a0206,
 0x7e6c0205, 0x7e6e0204,
 0x7e700203, 0x7e720202,
 0x7e740201, 0x7e760200,
 0x7e780209, 0x7e7a0208,
 0x7e7c0207, 0x7e7e0206,
 0xbf8a0000, 0xbf810000,
};

static const u32 sgpr_init_compute_shader[] =
{
 0xbe8a0100, 0xbe8c0102,
 0xbe8e0104, 0xbe900106,
 0xbe920108, 0xbe940100,
 0xbe960102, 0xbe980104,
 0xbe9a0106, 0xbe9c0108,
 0xbe9e0100, 0xbea00102,
 0xbea20104, 0xbea40106,
 0xbea60108, 0xbea80100,
 0xbeaa0102, 0xbeac0104,
 0xbeae0106, 0xbeb00108,
 0xbeb20100, 0xbeb40102,
 0xbeb60104, 0xbeb80106,
 0xbeba0108, 0xbebc0100,
 0xbebe0102, 0xbec00104,
 0xbec20106, 0xbec40108,
 0xbec60100, 0xbec80102,
 0xbee60004, 0xbee70005,
 0xbeea0006, 0xbeeb0007,
 0xbee80008, 0xbee90009,
 0xbefc0000, 0xbf8a0000,
 0xbf810000, 0x00000000,
};

static const u32 vgpr_init_regs[] =
{
 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
 mmCOMPUTE_NUM_THREAD_X, 256*4,
 mmCOMPUTE_NUM_THREAD_Y, 1,
 mmCOMPUTE_NUM_THREAD_Z, 1,
 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
 mmCOMPUTE_PGM_RSRC2, 20,
 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
};

static const u32 sgpr1_init_regs[] =
{
 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
 mmCOMPUTE_NUM_THREAD_X, 256*5,
 mmCOMPUTE_NUM_THREAD_Y, 1,
 mmCOMPUTE_NUM_THREAD_Z, 1,
 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
 mmCOMPUTE_PGM_RSRC2, 20,
 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
};

static const u32 sgpr2_init_regs[] =
{
 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
 mmCOMPUTE_NUM_THREAD_X, 256*5,
 mmCOMPUTE_NUM_THREAD_Y, 1,
 mmCOMPUTE_NUM_THREAD_Z, 1,
 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
 mmCOMPUTE_PGM_RSRC2, 20,
 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
};

static const u32 sec_ded_counter_registers[] =
{
 mmCPC_EDC_ATC_CNT,
 mmCPC_EDC_SCRATCH_CNT,
 mmCPC_EDC_UCODE_CNT,
 mmCPF_EDC_ATC_CNT,
 mmCPF_EDC_ROQ_CNT,
 mmCPF_EDC_TAG_CNT,
 mmCPG_EDC_ATC_CNT,
 mmCPG_EDC_DMA_CNT,
 mmCPG_EDC_TAG_CNT,
 mmDC_EDC_CSINVOC_CNT,
 mmDC_EDC_RESTORE_CNT,
 mmDC_EDC_STATE_CNT,
 mmGDS_EDC_CNT,
 mmGDS_EDC_GRBM_CNT,
 mmGDS_EDC_OA_DED,
 mmSPI_EDC_CNT,
 mmSQC_ATC_EDC_GATCL1_CNT,
 mmSQC_EDC_CNT,
 mmSQ_EDC_DED_CNT,
 mmSQ_EDC_INFO,
 mmSQ_EDC_SEC_CNT,
 mmTCC_EDC_CNT,
 mmTCP_ATC_EDC_GATCL1_CNT,
 mmTCP_EDC_CNT,
 mmTD_EDC_CNT
};

static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
{
 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
 struct amdgpu_ib ib;
 struct dma_fence *f = NULL;
 int r, i;
 u32 tmp;
 unsigned total_size, vgpr_offset, sgpr_offset;
 u64 gpu_addr;

 /* only supported on CZ */
 if (adev->asic_type != CHIP_CARRIZO)
  return 0;

 /* bail if the compute ring is not ready */
 if (!ring->sched.ready)
  return 0;

 tmp = RREG32(mmGB_EDC_MODE);
 WREG32(mmGB_EDC_MODE, 0);

 total_size =
  (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
 total_size +=
  (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
 total_size +=
  (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
 total_size = ALIGN(total_size, 256);
 vgpr_offset = total_size;
 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
 sgpr_offset = total_size;
 total_size += sizeof(sgpr_init_compute_shader);

 /* allocate an indirect buffer to put the commands in */
 memset(&ib, 0, sizeof(ib));
 r = amdgpu_ib_get(adev, NULL, total_size,
     AMDGPU_IB_POOL_DIRECT, &ib);
 if (r) {
  DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
  return r;
 }

 /* load the compute shaders */
 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
  ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];

 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
  ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];

 /* init the ib length to 0 */
 ib.length_dw = 0;

 /* VGPR */
 /* write the register state for the compute dispatch */
 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
  ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
  ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
  ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
 }
 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

 /* write dispatch packet */
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
 ib.ptr[ib.length_dw++] = 8; /* x */
 ib.ptr[ib.length_dw++] = 1; /* y */
 ib.ptr[ib.length_dw++] = 1; /* z */
 ib.ptr[ib.length_dw++] =
  REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

 /* write CS partial flush packet */
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);

 /* SGPR1 */
 /* write the register state for the compute dispatch */
 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
  ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
  ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
  ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
 }
 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

 /* write dispatch packet */
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
 ib.ptr[ib.length_dw++] = 8; /* x */
 ib.ptr[ib.length_dw++] = 1; /* y */
 ib.ptr[ib.length_dw++] = 1; /* z */
 ib.ptr[ib.length_dw++] =
  REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

 /* write CS partial flush packet */
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);

 /* SGPR2 */
 /* write the register state for the compute dispatch */
 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
  ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
  ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
  ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
 }
 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

 /* write dispatch packet */
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
 ib.ptr[ib.length_dw++] = 8; /* x */
 ib.ptr[ib.length_dw++] = 1; /* y */
 ib.ptr[ib.length_dw++] = 1; /* z */
 ib.ptr[ib.length_dw++] =
  REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

 /* write CS partial flush packet */
 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);

 /* shedule the ib on the ring */
 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 if (r) {
  DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
  goto fail;
 }

 /* wait for the GPU to finish processing the IB */
 r = dma_fence_wait(f, false);
 if (r) {
  DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
  goto fail;
 }

 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
 WREG32(mmGB_EDC_MODE, tmp);

 tmp = RREG32(mmCC_GC_EDC_CONFIG);
 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
 WREG32(mmCC_GC_EDC_CONFIG, tmp);


 /* read back registers to clear the counters */
 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
  RREG32(sec_ded_counter_registers[i]);

fail:
 amdgpu_ib_free(&ib, NULL);
 dma_fence_put(f);

 return r;
}

static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
{
 u32 gb_addr_config;
 u32 mc_arb_ramcfg;
 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
 u32 tmp;
 int ret;

 switch (adev->asic_type) {
 case CHIP_TOPAZ:
  adev->gfx.config.max_shader_engines = 1;
  adev->gfx.config.max_tile_pipes = 2;
  adev->gfx.config.max_cu_per_sh = 6;
  adev->gfx.config.max_sh_per_se = 1;
  adev->gfx.config.max_backends_per_se = 2;
  adev->gfx.config.max_texture_channel_caches = 2;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 32;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
  break;
 case CHIP_FIJI:
  adev->gfx.config.max_shader_engines = 4;
  adev->gfx.config.max_tile_pipes = 16;
  adev->gfx.config.max_cu_per_sh = 16;
  adev->gfx.config.max_sh_per_se = 1;
  adev->gfx.config.max_backends_per_se = 4;
  adev->gfx.config.max_texture_channel_caches = 16;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 32;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
  break;
 case CHIP_POLARIS11:
 case CHIP_POLARIS12:
  ret = amdgpu_atombios_get_gfx_info(adev);
  if (ret)
   return ret;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 32;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
  break;
 case CHIP_POLARIS10:
 case CHIP_VEGAM:
  ret = amdgpu_atombios_get_gfx_info(adev);
  if (ret)
   return ret;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 32;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
  break;
 case CHIP_TONGA:
  adev->gfx.config.max_shader_engines = 4;
  adev->gfx.config.max_tile_pipes = 8;
  adev->gfx.config.max_cu_per_sh = 8;
  adev->gfx.config.max_sh_per_se = 1;
  adev->gfx.config.max_backends_per_se = 2;
  adev->gfx.config.max_texture_channel_caches = 8;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 32;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
  break;
 case CHIP_CARRIZO:
  adev->gfx.config.max_shader_engines = 1;
  adev->gfx.config.max_tile_pipes = 2;
  adev->gfx.config.max_sh_per_se = 1;
  adev->gfx.config.max_backends_per_se = 2;
  adev->gfx.config.max_cu_per_sh = 8;
  adev->gfx.config.max_texture_channel_caches = 2;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 32;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
  break;
 case CHIP_STONEY:
  adev->gfx.config.max_shader_engines = 1;
  adev->gfx.config.max_tile_pipes = 2;
  adev->gfx.config.max_sh_per_se = 1;
  adev->gfx.config.max_backends_per_se = 1;
  adev->gfx.config.max_cu_per_sh = 3;
  adev->gfx.config.max_texture_channel_caches = 2;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 16;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
  break;
 default:
  adev->gfx.config.max_shader_engines = 2;
  adev->gfx.config.max_tile_pipes = 4;
  adev->gfx.config.max_cu_per_sh = 2;
  adev->gfx.config.max_sh_per_se = 1;
  adev->gfx.config.max_backends_per_se = 2;
  adev->gfx.config.max_texture_channel_caches = 4;
  adev->gfx.config.max_gprs = 256;
  adev->gfx.config.max_gs_threads = 32;
  adev->gfx.config.max_hw_contexts = 8;

  adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
  break;
 }

 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;

 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
    MC_ARB_RAMCFG, NOOFBANK);
 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
    MC_ARB_RAMCFG, NOOFRANKS);

 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
 adev->gfx.config.mem_max_burst_length_bytes = 256;
 if (adev->flags & AMD_IS_APU) {
  /* Get memory bank mapping mode. */
  tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
  dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
  dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);

  tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
  dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
  dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);

  /* Validate settings in case only one DIMM installed. */
  if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
   dimm00_addr_map = 0;
  if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
   dimm01_addr_map = 0;
  if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
   dimm10_addr_map = 0;
  if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
   dimm11_addr_map = 0;

  /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
  /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
  if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
   adev->gfx.config.mem_row_size_in_kb = 2;
  else
   adev->gfx.config.mem_row_size_in_kb = 1;
 } else {
  tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
  adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
  if (adev->gfx.config.mem_row_size_in_kb > 4)
   adev->gfx.config.mem_row_size_in_kb = 4;
 }

 adev->gfx.config.shader_engine_tile_size = 32;
 adev->gfx.config.num_gpus = 1;
 adev->gfx.config.multi_gpu_tile_size = 64;

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