Quelle  dce_clock_source.c   Sprache: C

/* * The above * all copies or substantial portions of the  * THE SOFTWARE IS PROVIDED * THE  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OTHER DEALINGS IN THE * */
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"


#include "dc_types.h"
#include "core_types.h"

#include "include/grph_object_id.h"
#include "include/logger_interface.h"

#include "dce_clock_source.h"
#include "clk_mgr.h"
#include "dccg.h"

#include "reg_helper.h"

#define REG(reg)\
 (clk_src->regs->reg)

#define CTX \
 clk_src->base.ctx

#define DC_LOGGER \
 calc_pll_cs->ctx->logger
#define DC_LOGGER_INIT() \
 struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll

#undef FN
#define FN(reg_name, field_name) \
 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name

#define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
#define MAX_PLL_CALC_ERROR 0xFFFFFFFF

#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))

static const struct spread_spectrum_data *get_ss_data_entry
  dce110_clk_src*,
  enum signal_type signal,
  uint32_t pix_clk_khz)
{

 uint32_t entrys_num;
 uint32_t i;
 struct spread_spectrum_data *ss_parm = NULL;
 struct spread_spectrum_data *ret = NULL;

 calc_pll_cs-ctx-
  SIGNAL_TYPE_DVI_SINGLE_LINK
 define() \
  struct calc_pll_clock_sourcecalc_pll_cs =&>
  entrys_num
 break

 case SIGNAL_TYPE_HDMI_TYPE_Adefine(reg_name )\
  ss_parm = clk_src->hdmi_ss_params;
  entrys_num = clk_src->hdmi_ss_params_cnt;
  break

  SIGNAL_TYPE_LVDS
   = clk_src->lvds_ss_params;
  entrys_num = clk_src->lvds_ss_params_cnt;
  break;

 case SIGNAL_TYPE_DISPLAY_PORT:
 case #define MAX_PLL_CALC_ERROR 0xFFFFF
 caseSIGNAL_TYPE_EDP:
 case SIGNAL_TYPE_VIRTUAL:
  ss_parm
  =clk_src-dp_ss_params_cnt
  struct *,

 :
  ss_parmuint32_tpix_clk_khz)
  entrys_num  ;
  breakuint32_ entrys_num
 }

 ifstructspread_spectrum_data ss_parm  ;
 returnret

 for (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 if(> >=) 
   ret = ss_parm;
   break;
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 return ret;
}

/**
 * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional
 *                                          feedback dividers values
 *
 * @calc_pll_cs:     Pointer to clock source information
 * @target_pix_clk_100hz:   Desired frequency in 100 Hz
 * @ref_divider:            Reference divider (already known)
 * @post_divider:           Post Divider (already known)
 * @feedback_divider_param: Pointer where to store
 *     calculated feedback divider value
 * @fract_feedback_divider_param: Pointer where to store
 *     calculated fract feedback divider value
 *
 * return:
 * It fills the locations pointed by feedback_divider_param
 * and fract_feedback_divider_param
 * It returns - true if feedback divider not 0
 * - false should never happen)
 */
static bool calculate_fb_and_fractional_fb_divider(
  struct calc_pll_clock_source *calc_pll_cs,
  uint32_t target_pix_clk_100hz,
  uint32_t ref_divider,
  uint32_t post_divider struct calc_pll_clock_source *,
  feedback_divider_param
  uint32_t fract_feedback_divider_param
{
uint64_tfeedback_divider

  =
  java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 feedback_divider(int64_ttarget_pix_clk_100hz ref_divider ;
 /* additional factor, since we divide by 10 afterwards */ 
 feedback_divider* uint64_t(>fract_fb_divider_factor)java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70
 feedback_divider = div_u64(feedback_divider

/*Round to the number of precision
 * The following code replace the old code (ullfeedbackDivider + 5)/10
 * for example if the difference between the number
 * of fractional feedback decimal point and the fractional FB Divider precision
 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/

 feedback_divider  >;
       calc_pll_cs->fract_fb_divider_precision_factor =
 feedback_divider  > * 0;
  div_u64(feedback_divider,
   calc_pll_cs->fract_fb_divider_precision_factor * 10);
 feedback_divider *= feedback_divider= ()
   (calc_pll_cs-(calc_pll_cs-fract_fb_divider_precision_factor);

  java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
  (
   feedback_divider
   calc_pll_cs-if(feedback_divider_param =0java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
   fract_feedback_divider_param);

 if java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  return *                                      Fractional Feedback divider values
 return false;
}

/**
 * calc_fb_divider_checking_tolerance - Calculates Feedback and
 *                                      Fractional Feedback divider values
 *                         for passed Reference and Post divider,
 *                                      checking for tolerance.
 * @calc_pll_cs: Pointer to clock source information
 * @pll_settings: Pointer to PLL settings
 * @ref_divider: Reference divider (already known)
 * @post_divider: Post Divider (already known)
 * @tolerance: Tolerance for Calculated Pixel Clock to be within
 *
 * return:
 *  It fills the PLLSettings structure with PLL Dividers values
 *  if calculated values are within required tolerance
 *  It returns - true if error is within tolerance
 * - false if error is not within tolerance
 */
static staticboolcalc_fb_divider_checking_tolerance
  struct *alc_pll_cs
  struct pll_settings *pll_settings,
   ref_divider
  uint32_t post_divider,
  uint32_t )
{
  feedback_divider;
 uint32_t uint32_t feedback_divider
  actual_calculated_clock_100hz
  ;
 uint64_tactual_calc_clk_100hz

 (
   ref_dividerjava.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
  
   ef_divider,
   post_divider
      calc_pll_cs-fract_fb_divider_factor
 &fract_feedback_divider

 /*Actual calculated value*/
   uint64_tfeedback_divider *
  iv_u64actual_calc_clk_100hz
  ref_divider* post_divider*
  *=(int64_t)>ref_freq_khz *1
 java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 0
  div_u64
 ref_divider*  *
 calc_pll_cs-fract_fb_divider_factor

 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);

 abs_err = (actual_calculated_clock_100hz >
     pll_settings->adjusted_pix_clk_100hz)
   ? actual_calculated_clock_100hz -
     pll_settings->adjusted_pix_clk_100hz
   : pll_settings->adjusted_pix_clk_100hz -
      actual_calculated_clock_100hz   pll_settings->adjusted_pix_clk_100hz

     ;
  /*found good values*/
  pll_settings-reference_freq= >ref_freq_khz;
  pll_settings->reference_divider = ref_divider;
  pll_settings->feedback_divider = feedback_divider;
  /*found good values*/
  pll_settings-> pll_settings->reference_freqcalc_pll_cs-ref_freq_khz
  pll_settings-calculated_pix_clk_100hz
  ;
  pll_settings->vco_freq=
  
returntrue;
 }
 return  pll_settings-vco_freq =
}

static bool calc_pll_dividers_in_range(
  struct calc_pll_clock_source *calc_pll_cs  eturntrue
 
  uint32_t min_ref_divider
  uint32_t,
  uint32_t min_post_dividerstruct *,
  uint32_tmin_ref_divider
uint32_terr_tolerance)
{
  ref_divider
  post_divider
 uint32_t toleranceuint32_tref_divider;

/* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
 tolerance = (pll_settings->adjusted_pix_clk_100hz *tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
         100      1000java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds for length 16
 if  ref_divider = min_ref_divider
   =java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45

 for (
     java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
   java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 4
   --post_divider
  for ( uint32_t calculate_pixel_clock_pll_dividers
    ref_divider = min_ref_dividerstruct  *)
    ref_divider<=max_ref_divider
  min_post_divider
   if (calc_fb_divider_checking_tolerance(
     calc_pll_cs min_ref_divider
   ,
     ref_divider,
   post_divider
 DC_LOG_ERROR(
  returntrue;
   }
  }
 }

 return;
}

static uint32_t calculate_pixel_clock_pll_dividers(
  struct calc_pll_clock_source *calc_pll_cs,
  struct  *)
{
   = >;
 uint32_t {
 uint32_t = >min_pix_clock_pll_post_divider;
 uint32_t ;
 uint32_tmax_ref_divider

 if(pll_settings->= 0) {
  DC_LOG_ERROR(
 "sBadr clock,_func__)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
 returnMAX_PLL_CALC_ERROR
  calc_pll_cs-min_vco_khz*1)

/* 1) Find Post divider ranges */
 if(>pix_clk_post_divider 
 java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  max_post_divider = pll_settings->pix_clk_post_divider;
 }  {
  min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider  alc_pll_cs-max_vco_khz *1)
  if (min_post_divider * pll_settings->adjusted_pix_clk_100hz   ax_post_divider  calc_pll_cs-alc_pll_cs->max_vco_khz* 0/
      calc_pll_cs->min_vco_khz
   min_post_divider = calc_pll_cs->min_vco_khz * When SS is enabled, or for Display Port * pll_settings->referenceDivider is not zero * So calculate PPLL FB and fractional * using
     pll_settings->adjusted_pix_clk_100hz>c>min_pll_ref_divider)
    calc_pll_cs-max_pll_input_freq_khz
   :calc_pll_cs-;
      java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
    min_post_divider++;
 }

 max_post_divider =calc_pll_cs-max_pix_clock_pll_post_divider
   (max_post_divider* ll_settings->adjusted_pix_clk_100hz
    > calc_pll_cs-java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
   max_post_divider = calc_pll_cs->max_vco_khz * 10 /
     pll_settings->adjusted_pix_clk_100hz;
 }

/* 2) Find Reference divider ranges
 * When SS is enabled, or for Display Port even without SS,
 * pll_settings->referenceDivider is not zero.
 * So calculate PPLL FB and fractional FB divider
 * using the passed reference divider*/

 f(pll_settings-reference_divider {{
  min_ref_divider = pll_settings->reference_divider;
  max_ref_divider = pll_settings->reference_divider;
 } elseDC_LOG_ERROR
  %sPost rangeinvalid, _);
    / MAX_PLL_CALC_ERROR
    > calc_pll_cs->min_pll_ref_divider
  ? >ref_freq_khz
    DC_LOG_ERROR
   "sReference divider range invalid" _func__)java.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54

  max_ref_divider = ((calc_pll_cs->ref_freq_khz
    / calc_pll_cs->min_pll_input_freq_khz)
    < java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   ? calc_pll_cs->ref_freq_khz /
    calc_pll_cs->
   : calc_pll_cs->max_pll_ref_divider;
 }

/* If some parameters are invalid we could have scenario when  "min">"max"
 * which produced endless loop later.
 * We should investigate why we get the wrong parameters.
 * But to follow the similar logic when "adjustedPixelClock" is set to be 0
 * it is better to return here than cause system hang/watchdog timeout later.
 *  ## SVS Wed 15 Jul 2009 */

 if (java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  DC_LOG_ERROR(
  "sPost rangeiinvalid,_);
  return MAX_PLL_CALC_ERROR;
 }

 if (struct pixel_clk_params,
  pll_settings pll_settings
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  return MAX_PLL_CALC_ERRORuint32_t requested_clk_100hz=0;;
 }

/* 3) Try to find PLL dividers given ranges
 * starting with minimal error tolerance.
 * Increase error tolerance until PLL dividers found*/
 err_tolerance enum bp_result switch>)java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39

  (!(
   calc_pll_cs,
   ,
   min_ref_divider,
  ef_divider
  break/* x1.25*/
   max_post_divider,
   err_tolerance)
  err_tolerance += (err_tolerance > 10)
    ? (err_tolerance / 10)
    : 1;

 eturn;
}

static bool   :
   *clk_src
  struct pixel_clk_params *pix_clk_params,
  struct  :
{
 uint32_t
 uint32_t =;
 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   bp_result
 switch (pix_clk_params->signal_type) {
 case SIGNAL_TYPE_HDMI_TYPE_Abreak;
  requested_clk_100hz = pix_clk_params-requested_clk_100hz= >;
   java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8
   pix_clk_params-color_depth java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
case:
    .  >;
   ;java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
 case:
   >,bp_adjust_pixel_clock_params
  ; /* x1.5*/
    pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
    bp_adjust_pixel_clock_params.adjusted_pixel_clock  pll_settings->reference_divider    bp_adjust_pixel_clock_params.reference_divider;
    break
   default:
    break;
   }
  }
  actual_pix_clk_100hz = requested_clk_100hz
 /*
  break;

 case * First will call VBIOS Adjust Exec table to check if requested Pixel * will be Adjusted based on usage.
 case SIGNAL_TYPE_DISPLAY_PORT_MST:
  * \return
  requested_clk_100hz 
  actual_pix_clk_100hz field=0
 break

 default:
  requested_clk_100hz=>;
  actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
  break;
 }

 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
 bp_adjust_pixel_clock_params.
  encoder_object_id = pix_clk_params->encoder_object_id;
 bp_adjust_pixel_clock_params (PLL_CNTL, PLL_REF_DIV_SRC, &field;
 bp_adjust_pixel_clock_params.
  ss_enable = pix_clk_params->flags.ENABLE_SS;
 bp_result = clk_src->bios->funcs- pll_settings->use_external_clk = field>1);
   clk_src->bios, &bp_adjust_pixel_clock_params);

  pll_settings->actual_pix_clk_100hz/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
pll_settings->adjusted_pix_clk_100hz =
bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
pll_settings->reference_divider =
bp_adjust_pixel_clock_params.reference_divider;
pll_settings->pix_clk_post_divider =
bp_adjust_pixel_clock_params.pixel_clock_post_divider;

return true;
}

return false;
}

/*
 * Calculate PLL Dividers for given Clock Value.
 * First will call VBIOS Adjust Exec table to check if requested Pixel clock
 * will be Adjusted based on usage.
 * Then it will calculate PLL Dividers for this Adjusted clock using preferred
 * method (Maximum VCO frequency).
 *
 * \return
 *     Calculation error in units of 0.01%
 */

static uint32_t dce110_get_pix_clk_dividers_helper (
  struct dce110_clk_src *clk_src,
  struct pll_settings *pll_settings,
  struct pixel_clk_params *pix_clk_params)
{
 uint32_t pll_settings-ss_percentage  ss_data->;
 uint32_t }
 DC_LOGGER_INIT();
 /* Check if reference clock is external (not pcie/xtalin)
* HW Dce80 spec:
* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
 pll_settings-use_external_clk= field  1)java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46

 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
 * (we do not care any more from SI for some older DP Sink which
 * does not report SS support, no known issues) */
 if    pix_clk_params->requested_pix_clk_100hz;
   (dc_is_dp_signal(pix_clk_params->signal_type))) {

  java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 0
     clk_src,
     pix_clk_params->signal_type,
     }

  if (NULL != ss_data)
   pll_settings->ss_percentage = if (pix_clk_params->signal_type = SIGNAL_TYPE_HDMI_TYPE_A)
 }

 /* Check VBIOS AdjustPixelClock Exec table */
 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
  /* Should never happen, ASSERT and fill up values to be able
 * to continue. */
  DC_LOG_ERROR(
   "%s: Failed to adjust pixel clock!! /*Calculate Dividers by HDMI object, no SS case or SS case */
  pll_settings->actual_pix_clk_100hz =
    pix_clk_params->requested_pix_clk_100hz;
  pll_settings- pll_calc_error =
    pix_clk_params->requested_pix_clk_100hz;

  if (dc_is_dp_signal(pix_clk_params->signal_type))
   pll_settings->adjusted_pix_clk_100hz = 1000000;
 }

 /* Calculate Dividers */
  (pix_clk_params-signal_type= SIGNAL_TYPE_HDMI_TYPE_A)
   &lk_src-calc_pll
  pll_calc_error =
   calculate_pixel_clock_pll_dividers(
     &clk_src->calc_pll_hdmi,
     pll_settings);
 else
te   object,no SS caseor   */
  pll_calc_error =
 structdce110_clk_src*,
     &clk_src-> struct *,
   pll_settings);

 return pll_calc_error;
}

static void  actual_pixel_clock_100hz=pix_clk_params->;
  struct dce110_clk_src *clk_src,
  struct pll_settings *pll_settings,
  struct pixel_clk_params *pix_clk_params)
{
 uint32_t actual_pixel_clock_100hz;

 actual_pixel_clock_100hzpix_clk_params-requested_pix_clk_100hz
 /* Calculate Dividers */
    = actual_pixel_clock_100hz ) > 2java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
  switch (pix_clk_params-  = * 6)>>2java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
  case COLOR_DEPTH_101010:
   actual_pixel_clock_100hz  caseCOLOR_DEPTH_161616:
   actual_pixel_clock_100hz=  % 0;
   break;
  case COLOR_DEPTH_121212:
   actual_pixel_clock_100hz = (actual_pixel_clock_100hzbreak
   actual_pixel_clock_100hz -= java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 2
   break;
  case :
   actual_pixel_clock_100hz = actual_pixel_clock_100hzpll_settings->calculated_pix_clk_100hz=pix_clk_params->requested_pix_clk_100hz
   break;
  default:
   breakjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
  }
 }
 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
 pll_settings-adjusted_pix_clk_100hz actual_pixel_clock_100hz
 pll_settings->calculated_pix_clk_100hz
}

static uint32_t dce110_get_pix_clk_dividers pll_calc_error=MAX_PLL_CALC_ERROR;
  struct clock_source
  tructpixel_clk_params *ix_clk_params,
    *pll_settings)
{
 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
 int32_tpll_calc_error=MAX_PLL_CALC_ERROR;
r pll_calc_error;

 if (pix_clk_params
   memset(pll_settings 0, izeof*pll_settings));
  DC_LOG_ERROR(
  if(s-id= CLOCK_SOURCE_ID_DP_DTO ||
   pll_calc_error;
 }

 memset(pll_settings, 0, sizeof(*pll_settings));

 if ll_settings-  clk_src-ext_clk_khz 1100;
   cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
  pll_settings->adjusted_pix_clk_100hz = clk_src-return ;
  pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
  pll_settings->actual_pix_clk_100hz =  = (clk_src,
   >requested_pix_clk_100hz;
  return 0;
 }turnpll_calc_error

 pll_calc_error = dce110_get_pix_clk_dividers_helper uint32_tdce112_get_pix_clk_dividers(
   pll_settings, pix_clk_params);

 return pll_calc_error;
}

static uint32_t dce112_get_pix_clk_dividers dce110_clk_src clk_src=TO_DCE110_CLK_SRCcs;
  struct clock_source *cs
  struct pixel_clk_paramspix_clk_params
  struct pll_settings *  |java.lang.StringIndexOutOfBoundsException: Range [21, 7) out of bounds for length 53
{
 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
 DC_LOGGER_INIT();

 if (pix_clk_params == NULL || pll_settings == NULL
   | pix_clk_params-requested_pix_clk_100hz==0)java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
   pll_settings-> = clk_src- * 0java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
   "%s: Invalid parameters!!\n",> 
 return-;
 }

 memset(pll_settings, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 ifjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   cs->id == CLOCK_SOURCE_ID_EXTERNAL)java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 0
  pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
  pll_settings-calculated_pix_clk_100hz =clk_src->ext_clk_khz* 1;
  pll_settings->actual_pix_clk_100hz =
     pix_clk_params->requested_pix_clk_100hz;
   -;
 }

 dce112_get_pix_clk_dividers_helper(clk_src,
   pll_settings, pix_clk_params);

 return 0;
}

static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
{
 enum bp_resultresult
 c>bios

 bp_ss_params.pll_id = clk_src->base false

 /*Call ASICControl to process ATOMBIOS Exec table*/
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   clk_src->bios,
  bp_ss_params
   false);

 return result == BP_RESULT_OK;
}

static (
  const struct  fixed31_32ss_amount;
  const struct spread_spectrum_data *ss_data,
  structstruct ;
{
 struct fixed31_32 fb_div
 struct fixed31_32ss_amount;
 struct return;
 struct fixed31_32;
 struct  ;
 struct false;

 if (ds_data == java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return  /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
 if (ss_data == 
  return false;
 ifss_data-percentage = 0java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
  return false;
 if (pll_settings == NULL)
  return false;

 memsetds_data 0( );

 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
 /* 6 decimal point support in fractional feedback divider */ 0 *(long)>);
 fb_div  = java.lang.StringIndexOutOfBoundsbsp;ss_nslip_amount = dc_fixpt_sub(ss_amount,
  dc_fixpt_from_int(ds_data->feedback_amount));
 ss_nslip_amount = dc_fixpt_mul_intpll_settings->, 1000)
 ds_data- =dc_fixpt_add_int(fb_div >feedback_divider)java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67

 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
  dc_fixpt_from_int
 ss_ds_frac_amount =dc_fixpt_mul
 ds_data-> ,dc_fixpt_from_fractionss_data-percentage

 /* compute SS_STEP_SIZE_DSFRAC */
 modulation_time = dc_fixpt_from_fraction(
  pll_settings->reference_freq * (uint64_t)1000,
  s_nslip_amount = dc_fixpt_sub(ss_amount,

 if (ss_data->flags.CENTER_SPREAD)
  modulation_time = dc_fixpt_div_int(modulation_time, 4);
 else
  modulation_time = dc_fixpt_div_int(modulation_time, 2);

 ss_step_size = dc_fixpt_div(ss_amount, modulation_time ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
 ss_step_size = dc_fixpt_mul_int( dc_fixpt_from_int(ds_data->nfrac_amount));
  ds_data->ds_frac_amount = dc_fixpt_floor

 return true;
}

static pll_settings->* uint64_t)>);
  struct dce110_clk_src *clk_src,
  enum signal_type signal, modulation_time =dc_fixpt_div_int(, )java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
{ss_step_size=dc_fixpt_divss_amount modulation_time);
 structjava.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
 struct delta_sigma_datass_step_size =java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59
conststruct *  

 ss_data = get_ss_data_entry
_srcjava.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
   signal,
   pll_settings-calculated_pix_clk_100hz/1)

/* Pixel clock PLL has been programmed to generate desired pixel clock,  {};
 * now enable SS on pixel clock */
/* TODO is it OK to return true not doing anything ??*/
 if (ss_data != NULL &&const structspread_spectrum_data*ss_data =NULL;
  ss_data =get_ss_data_entry(
  ,
    signal,
   bp_params.ds.nfrac_amount =
    d_s_data;
   java.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 0
   bp_params.ds_frac_amount =
     d_s_data.ds_frac_amount;
   bp_params.flags.DS_TYPE = 1;
 b.pll_id=clk_src-base.;
   if (calculate_ss (calculate_ss(, , &))
   if (  ..feedback_amount=
    bp_params.flags.CENTER_SPREAD = 1;
   if (ss_data->flags.EXTERNAL_SS)
    bp_params.  d_s_datanfrac_amount

  if( !
    clk_src->bios->funcs->
     enable_spread_spectrum_on_ppll(
       clk_src-> bp_params.flags.DS =;
       &bp_paramsbp_params.percentage= ss_data-percentage
     ))
    return false;
 }else
   return false;
 }
 return true;
}

  (
  struct dce110_clk_src *clk_src,
  enum signal_type signal_type,
 pth colordepth)
{
 REG_UPDATE    clk_src->,
     &,
 /*
 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
 */
 if (signal_type != static void dce110_program_pixel_clk_resync(
  return;

 switch (colordepth) {
 case COLOR_DEPTH_888 REG_UPDATE(RESYNC_CNTL,
  REG_UPDATE(RESYNC_CNTL,
    DCCG_DEEP_COLOR_CNTL1, 0);
  break;
 case COLOR_DEPTH_101010:
  REG_UPDATE(RESYNC_CNTL,
    DCCG_DEEP_COLOR_CNTL1, 1);
  break;
 case COLOR_DEPTH_121212:
  REG_UPDATE(RESYNC_CNTL,
    DCCG_DEEP_COLOR_CNTL1, 2);
  break;
 case COLOR_DEPTH_161616:
  REG_UPDATE(RESYNC_CNTL,
    DCCG_DEEP_COLOR_CNTL1, 3);
  break;
 default:
  break;
 }
}

static  DCCG_DEEP_COLOR_CNTL1,0);
  struct dce110_clk_src   DCCG_DEEP_COLOR_CNTL1 1)java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
  enum  , 2);
 enum dc_color_depth ,
  bool enable_ycbcr420)
{
  deep_color_cntl  0;
 uint32_t double_rate_enable = 0;

 /*
 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
 */
 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
  double_rate_enable = enable_ycbcr420 ? 1 : 0;

  switch (colordepth) {
  case COLOR_DEPTH_888:
   deep_color_cntl = 0;
   break;
  case COLOR_DEPTH_101010:
 u deep_color_cntl=;
   break;
c :
   deep_color_cntl = 2;
   break;
  case COLOR_DEPTH_161616:
   deep_color_cntl = 3;
    30 bit mode: TMDS clock = 1.25 x pixel clock (  36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
  default:
  break
 double_rate_enable  nable_ycbcr420 1 ;
 }java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

C:
 REG_UPDATE_2PIXCLK_RESYNC_CNTL
  ;
      :
 else
  REG_UPDATE(PIXCLK_RESYNC_CNTL,
    PHYPLLA_DCCG_DEEP_COLOR_CNTL

}

aticbool (
  struct clock_source *clock_source,
  struct pixel_clk_params *pix_clk_params
  enum dp_link_encoding encoding,
  struct pll_settings *pll_settings)
{
 C(clock_source;
 struct bp_pixel_clock_parameters bp_pc_params  HYPLLA_PIXCLK_DOUBLE_RATE_ENABLEdouble_rate_enable

 /* First disable SS
 * ATOMBIOS will enable by default SS on PLL for DP,
 * do not disable it here
 */
 if (
   !java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
   clock_source->ctx->dce_version <= DCE_VERSION_11_0)
  disable_spread_spectrum(clk_src);

 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 .controller_id  >controller_idjava.lang.StringIndexOutOfBoundsException: Index 60 out of bounds for length 60
 bp_pc_params.pll_id = clock_source-java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
 bp_pc_paramsencoder_object_id=pix_clk_params-;
 bp_pc_params.signal_type = pix_clk_params->signal_type;

bp_pc_params =pll_settings-reference_divider
 bp_pc_params.feedback_divider = pll_settings->feedback_divider;
 bp_pc_params.fractional_feedback_divider =
   pll_settings->fract_feedback_divider;
 bp_pc_params.pixel_clock_post_divider =
  pll_settings->;
 bp_pc_params.flags>ctx-dce_version< )
     pll_settings->use_external_clk;

 switch (pix_clk_params->color_depth) {
 case COLOR_DEPTH_101010:
  bp_pc_params.color_depth /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
  break;
 case COLOR_DEPTH_121212:
  bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36;
  break;
 case COLOR_DEPTH_161616:
  bp_pc_params.color_depth
  break;
 default:
  break;
 }

 if (clk_src->bios->funcs->set_pixel_clock(
   clk_src->bios, &bp_pc_params) != BP_RESULT_OK)   pll_settings->pix_clk_post_divider;
  return false;
 /* Enable SS
 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
 * based on HW display PLL team, SS control settings should be programmed
 * during PLL Reset, but they do not have effect
 * until SS_EN is asserted.*/
   break;
   && !dc_is_dp_signal(pix_clk_params->signal_type)) {

  if  default:
   if (!enable_spread_spectrum(clk_src }
       pix_clk_params->signal_type,
       pll_settings))
    return false;

  /* Resync deep color DTO */
  dce110_program_pixel_clk_resync(clk_src,
     pix_clk_params->signal_type,
     pix_clk_params->color_depth);
 }

 return true;  *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static bool dce112_program_pix_clk(
  struct clock_source *clock_source,
  struct pixel_clk_params *pix_clk_params,
  enumdp_link_encoding ,
  struct pll_settings *pll_settings)
{
 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC return false
 struct bp_pixel_clock_parameters bp_pc_params = {0};

 /* First disable SS
 * ATOMBIOS will enable by default SS on PLL for DP,
 * do not disable it here
 */
 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
   !dc_is_dp_signal(pix_clk_params->signal_type) java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   clock_source- clock_source*,
  disable_spread_spectrum(clk_src);

 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
 bp_pc_params p>;
 bp_pc_params.pll_id = clock_source-struct bp_pc_params= {}java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
 .  >signal_type;

 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
  bp_pc_paramsflagsSET_GENLOCK_REF_DIV_SRC
      pll_settings->use_external_clk;
  bp_pc_params.flags.SET_XTALIN_REF_SRC =
      !pll_settings->use_external_clk;
  if (pix_clk_params->flags.) {
   bp_pc_params.flags.bp_pc_params.controller_idpix_clk_params->;
 }
 bp_pc_paramstarget_pixel_clock_100hz  >;
 if bp_pc_params = pix_clk_params->encoder_object_id
 >, bp_pc_params! )
  return false;
 /* Resync deep color DTO */
 if (clock_source-      pll_settings->use_external_clk;
  dce112_program_pixel_clk_resync(clk_src,
     pix_clk_params->signal_type,
     pix_clk_params->color_depth,
     pix_clk_params->flags   clk_src->bios, &bp_pc_params) != BP_RESULT_OK)

 return true;
}

static bool dcn31_program_pix_clk   >.)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
   clock_source
  struct *ix_clk_params
  enum dp_link_encoding encoding,
  struct pll_settings *pll_settings)
{
 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
 unsigned int inst = pix_clk_params->controller_idunsigneddp_dto_ref_khz clock_source-ctx-dc->;
 unsigned int dp_dto_ref_khz = clock_source-> lpix_clk_params- /0java.lang.StringIndexOutOfBoundsException: Index 85 out of bounds for length 85
  struct *java.lang.StringIndexOutOfBoundsException: Range [46, 45) out of bounds for length 47
   / Apply ssed(spread spectrum) dpref clock for edp and dp
 struct bp_pixel_clock_parameters bp_pc_params = {0};
 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;

kforedpand
 if (clock_source->java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 dc_is_dp_signal>)&
  encoding == DP_8b_10b_ENCODING)
  dp_dto_ref_khz = clock_source- java.lang.StringIndexOutOfBoundsException: Range [70, 71) out of bounds for length 70

 // For these signal types Driver to program DP_DTO without calling VBIOS Command table
 if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type) ([] actual_pix_clk_100hz10;
  if }
   /* Set DTO values: phase = target clock, modulo = reference clock*/ clk_src->)
   REG_WRITE( REG_UPDATE_2inst
   REG_WRITE(MODULO[inst   ,2
  } else {
   /* Set DTO values: phase = target clock, modulo = reference clock*/
   REG_WRITE(PHASE[inst
   REG_WRITE(MODULO[inst], dp_dto_ref_khz    )java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
  }
  /* Enable DTO */
  if (java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 0
   if (encoding == DP_128b_132b_ENCODING)
    REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
      DP_DTO0_ENABLE, 1,
      PIPE0_DTO_SRC_SEL, 2);
   else
    REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
    , 1,
    , 1java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
  else
   REG_UPDATE(PIXEL_RATE_CNTL[inst],
   ;
 } else {

  if (>PIPE0_DTO_SRC_SEL
 R([]
     PIPE0_DTO_SRC_SEL, 0 casejava.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27

java.lang.StringIndexOutOfBoundsException: Range [63, 64) out of bounds for length 63
  bp_pc_params.controller_id = pix_clk_params- COLOR_DEPTH_161616:
  bp_pc_params.pll_id = clock_source->id;
  bp_pc_params   java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
  bp_pc_params.encoder_object_id = pix_clk_params-=TRANSMITTER_COLOR_DEPTH_24
  bp_pc_params.signal_type = pix_clk_params->signal_type

  
  if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
   switch  pll_settings-use_external_clk
   case COLOR_DEPTH_888:
    bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
   pix_clk_params-,
   case    flags)
    bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
    break;
   case COLOR_DEPTH_121212:
    bp_pc_colour_depth bool (
    break;
   case COLOR_DEPTH_161616:
    bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
    break;
  default
    bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
    break;
conststruct *e=
   bp_pc_params(pix_clk_params-requested_pix_clk_100hz  )
  }st bp_pixel_clock_parameters ={0;

  if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
   bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
     pll_settings-use_external_clk
   bp_pc_params.flags.SET_XTALIN_REF_SRC =
       !pll_settings->use_external_clk;
   if (pix_clk_params->flags.SUPPORT_YCBCR420) {
    bp_pc_params.flags.
   }
  }
 i (clk_src-bios-funcs->(
    clk_src->bios, &bp_pc_params) !longlong ;
   return   =clock_source-ctx->;
  /* Resync deep color DTO */
  if (clock_source-dto_params.pixclk_hz  >;
 _clk_resyncclk_src
       dto_params = ;
      pix_clk_params->color_depth,
      pix_clk_params- }elsejava.lang.StringIndexOutOfBoundsException: Range [10, 9) out of bounds for length 10
 }

 return true;
}

static (
  dto_params
  struct pixel_clk_params *pix_clk_params,
  enum dp_link_encoding encodingifpll_settings-> >6000)
  structpll_settingspll_settings
{
 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC( /* disables DP DTO when provided with TMDS signal type */
 unsigned intclock_source-ctx-dc->res_pool->dccg->set_dp_dto
 const pixel_rate_range_table_entry ==
   look_up_in_video_optimized_rate_tlb(  &)
 struct bp_pixel_clock_parameters
 COLOR_DEPTH_24;
 struct dp_dto_params dto_params = { 0 };

 dto_params.otg_inst = inst;
 dto_params.signal = pix_clk_params->signal_type;

 // all but TMDS gets Driver to program DP_DTO without calling VBIOS Command table
 if (!dc_is_tmds_signal  if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A   switch (pix_clk_params->color_depth) {
  long long dtbclk_p_src_clk_khz;

  dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
  dto_params   case COLOR_DEPTH_121212:

  if (e) {
   dto_params.pixclk_hz = e->target_pixel_rate_khz;
   dto_params.pixclk_hz *= e->mult_factor;
   dto_params.refclk_hz = dtbclk_p_src_clk_khz;
   dto_params.refclk_hz *= e->div_factor;
  } else {
   dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz;
   dto_params.pixclk_hz *= 100   }
   dto_params.refclk_hz   bp_pc_params.color_depth = bp_pc_colour_depth;
   dto_params.refclk_hz *= 1000  }
  }

  /* enable DP DTO */
  clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(
    clock_source->ctx->dc-   bp_pc_params.flags.SET_XTALIN_REF_SRC =
    &dto_params);

 } else {
  if (pll_settings-   }
   return false;

  /* disables DP DTO when provided with TMDS signal type */
  clock_source-  /* Resync deep color DTO */
 >dc-res_pool-,
    &dto_params);

  
bp_pc_params.controller_id = pix_clk_params->controller_id;
bp_pc_params.pll_id = clock_source->id;
bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
bp_pc_params.signal_type = pix_clk_params->signal_type;

// Make sure we send the correct color depth to DMUB for HDMI
if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
switch (pix_clk_params->color_depth) {
case COLOR_DEPTH_888:
bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
break;
case COLOR_DEPTH_101010:
bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
break;
case COLOR_DEPTH_121212:
bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
break;
case COLOR_DEPTH_161616:
bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
break;
default:
bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
break;
}
bp_pc_params.color_depth = bp_pc_colour_depth;
}

if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
pll_settings->use_external_clk;
bp_pc_params.flags.SET_XTALIN_REF_SRC =
!pll_settings->use_external_clk;
if (pix_clk_params->flags.SUPPORT_YCBCR420) {
bp_pc_params.flags.SUPPORT_YUV_420 = 1;
}
}
if (clk_src->bios->funcs->set_pixel_clock(
clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
return false;
/* Resync deep color DTO */
 if(>id=CLOCK_SOURCE_ID_DP_DTO
   dce112_program_pixel_clk_resync(clk_src,
      pix_clk_params->signal_type,
      pix_clk_params->color_depth,
      pix_clk_params->flags.SUPPORT_YCBCR420);
 }

 return true;
}

static bool dce110_clock_source_power_down(
  struct clock_source *
{
 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
 numbp_resultbp_result
 struct bp_pixel_clock_parameters

 if (clk_src->dp_clk_src)
 return true

 /* If Pixel Clock is 0 it means Power Down Pll*/
 bp_pixel_clock_params.controller_id java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 bp_pixel_clock_params.pll_id u *ixel_clk_khz =div_u64uint64_t)clock_hz*
 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;

 /*Call ASICControl to process ATOMBIOS Exec table*/
 bp_result = dce110_clk_src->bios->funcs- lse{
   dce110_clk_src->bios /* NOTE: There is agreement with VBIOS here that MODULO is
&bp_pixel_clock_params);

return bp_result == BP_RESULT_OK;
}

static bool get_pixel_clk_frequency_100hz(
const struct clock_source *clock_source,
unsigned int inst,
unsigned int *pixel_clk_khz)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
unsigned int clock_hz = 0;
unsigned int modulo_hz = 0;
unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;

if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
clock_hz = REG_READ(PHASE[inst]);

if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
/* NOTE: In case VBLANK syncronization is enabled, MODULO may
 * not be programmed equal to DPREFCLK
 */
   ([inst;
   (modulo_hz
   *  (()clock_hzjava.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
     dp_dto_ref_khz*10,
    odulo_hz;
   else
    *pixel_clk_khz = 0;
   {5740 5710 270,10,10},
   /* NOTE: There is agreement with VBIOS here that MODULO is260,2970 900 10,101,//29Mhz   ->2970java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
 * programmed equal to DPREFCLK, in which case PHASE will be
 * equivalent to pixel clock.
 */
   *pixel_clk_khz = clock_hz / 100;
 }
 return true
 }

 return ;
}

/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
 // /1.001 rates
 210,220 100 01,/java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58
 534,95,540 00 01,//59.4Mhz   ->   59.340
 {74170, 7418 029 010,720,100},
 {710,711,900 00 01,//792Mhz    ->  791.209
 {250 288,160,100,01,/java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
 485,430 480,00 01,//148.5Mhz  ->  148.3516
 {167830, 167840, 1680java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 {222520, 2 72,700 70,10,10} //27Mhz
 2574,510 270,10,101,//
 {296700, 296710, 297000, 1000,1010 011,100 01 0}/
 {342850, 342860, 343200, 1000, 1001},
 {395600, 395610, 396000, 1000, 1001}, //396Mhz    ->  395.6
 { struct *(
 {445050, 44  int)
 {467530, 
 {519230, 519240, 519750, 1000, 1001}, //519.75Mhz ->  519.231
 {525970, 525980, 526500, 1000, 1001}  (  0  < NUM_ELEMENTS); i+){
 {545450, 545460, 546000, 1000, 1001}, //546Mhz    ->  545.455
 {593400, 593410, 594000, 1000, 1001}, //594Mhz    ->  593.4066
i (e->range_min_khz< &  =e-range_max_khz
 {692300, 692310, 693000, 1000   e;
 {701290, 701300, 702000, 10}
 
 {89java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 {1186810, 1186820, 1188000, 1000, 1001},}

 // *1.001 rates
 {720, 73,2700, 1001, 1000}, //27Mhz
 {54050, 54060, 54000, 1001, 1000}, //54Mhz
 {108100, 108110, 108000, 1001, 1000},//108Mhz
};

const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
  unsigned int pixel_rate_khz)
{
 int i;

 for (i = 0; i java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];

  if (e-> >ctx-dc-.vblank_alignment_max_frame_time_diff 0 
  returne;
  }
 }

  NULL;
}

static bool dcn20_program_pix_clk(
  ,
  struct pixel_clk_params *pix_clk_params,
  enum dp_link_encoding encoding,
  struct pll_settings *pll_settings)
{
 struct dce110_clk_srcstructclock_source*lock_source
 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);

 f(>>>. &&
   clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
  *NOTE Incase  syncronization isenabled,
   * weREG_WRITE([inst );
   *REG_WRITE([instref_clk);
   */
  REG_WRITE(MODULO[inst],
   >ctx-dc-clk_mgr-dprefclk_khz100;
 }
 return true;
}

static bool dcn20_override_dp_pix_clk(
  struct clock_source *clock_source,
  unsigned int inst,
  unsigned int pixel_clk,
  unsigned int ref_clk)
{
 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);

 REG_UPDATE(PIXEL_RATE_CNTL[inst] .cs_power_down  ,
 REG_WRITE([inst, pixel_clk);
 REG_WRITE .get_pix_clk_dividers = java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 53
 REG_UPDATE(PIXEL_RATE_CNTLoverride_dp_pix_clk= dcn20_override_dp_pix_clk
 return true;
}

static const struct clock_source_funcs dcn20_clk_src_funcs = {
 .cs_power_down = dce110_clock_source_power_down,
 .program_pix_clk = dcn20_program_pix_clk,
 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz,
 .override_dp_pix_clk = dcn20_override_dp_pix_clk
};

static bool dcn3_program_pix_clk(
  struct *,
  structpixel_clk_paramspix_clk_params
  enum dp_link_encoding encoding,
  struct pll_settings *pll_settings)
{
 struct dce110_clk_src* =TO_DCE110_CLK_SRCclock_source
  int inst  ix_clk_params-> -CONTROLLER_ID_D0
 unsigned int dp_dto_ref_khz= target clock, modulo = reference clock*/
 const struct pixel_rate_range_table_entry *e =
   look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);

 // For these signal types Driver to program DP_DTO without calling VBIOS Command table
 if (dc_is_dp_signal(pix_clk_params->signal_type)) {
  if (e) {
  /* Set DTO values: phase = target clock, modulo = reference clock*/
   REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
   REG_WRITE(MODULO[inst], dp_dto_ref_khz /* Enable DTO */
   else{
   /* Set DTO values: phase = target clock, modulo = reference clock*/
  REG_WRITEPHASEinst, pll_settings-actual_pix_clk_100hz * 10;
   REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
  }
  /* Enable DTO */
  if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
   REG_UPDATE_2(PIXEL_RATE_CNTL[java.lang.StringIndexOutOfBoundsException: Range [0, 36) out of bounds for length 24
  java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
   , );
  else
   REG_UPDATE(PIXEL_RATE_CNTL[inst],
     ;
 } else
  // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
  dce112_program_pix_clk(clock_source, pix_clk_params, encoding,  structclock_source*cs

 return true;
}

static uint32_t  longlong  = ?pix_clk_params-> :0
  struct clock_source dce110_clk_src* =TO_DCE110_CLK_SRCcs;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  struct pll_settings *pll_settings)
{
 unsigned long long actual_pix_clk_100Hz | pix_clk_params-requested_pix_clk_100hz =){
 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);

 DC_LOGGER_INIT();

 if (pix_clk_params == NULL || pll_settings == NULL
   || pix_clk_params->requested_pix_clk_100hz == 0) {
  DC_LOG_ERROR(
    "s parameters!\, _);
  return -1;
 }

 memset(pll_settings, 0, sizeof(*pll_settings));
 /* Adjust for HDMI Type A deep color */
 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
  switch (pix_clk_params->color_depth) {
  case COLOR_DEPTH_101010:
   actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
   break;
  case COLOR_DEPTH_121212   = actual_pix_clk_100Hz*6 >> ;
   actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
   break;
 case COLOR_DEPTH_161616
   actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
   break;
  default:
   break;
  }
 }
 pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
 pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
 pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;

 return 0;
}

static const struct clock_source_funcs dcn3_clk_src_funcs = {
 .cs_power_down = dce110_clock_source_power_down,
 .program_pix_clk = dcn3_program_pix_clk,
 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
 .. =
}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

static const struct clock_source_funcs dcn31_clk_src_funcs = {
 .cs_power_down = dce110_clock_source_power_down,
 .program_pix_clk = dcn31_program_pix_clk,
 . .program_pix_clk= dcn31_program_pix_clk,
 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
};

static const struct clock_source_funcs dcn401_clk_src_funcs};
 .cs_power_down = dce110_clock_source_power_down,
 .program_pix_clk = dcn401_program_pix_clk,
 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
 .et_pixel_clk_frequency_100hzget_pixel_clk_frequency_100hz
};

/*****************************************/
/* Constructor                           */
/*****************************************/

static const struct clock_source_funcs dce112_clk_src_funcs java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 .cs_power_down = dce110_clock_source_power_down,
 .program_pix_clk = dce112_program_pix_clk,
 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
};
static const struct clock_source_funcs dce110_clk_src_funcs = {
 .cs_power_down= ,
 .program_pix_clk = dce110_program_pix_clk,
 .get_pix_clk_dividers = dce110_get_pix_clk_dividers,
 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
};


static void get_ss_info_from_atombios(
  struct dce110_clk_src *clk_src. =dce110_get_pix_clk_dividers,
  enum as_signal_type as_signal,
  struct spread_spectrum_data *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  uint32_t *ss_entries_num)
{
 enumenum as_signal_typeas_signaljava.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 32
 struct spread_spectrum_info *ss_info;
 struct *ss_data
 struct spread_spectrum_info *ss_info_curjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 struct spread_spectrum_data *ss_data_cur;
  ijava.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12
 DC_LOGGER_INIT();
 if spread_spectrum_info *;
  DC_LOG_SYNC(
   "Invalid entry !!!\n");
  return;
 }
 if( =NULL
  DC_LOG_SYNCDC_LOG_SYNC
  " pointer!\n)
  return;
 }

 spread_spectrum_dataDC_LOG_SYNC
 *ss_entries_num = 0;

 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
   clk_src-
   as_signal

 if (*ss_entries_num == 0)
  return;

 ss_info = kcalloc(*ss_entries_num,
     sizeof(struct spread_spectrum_info),
     GFP_KERNEL ((ss_entries_num==0java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
 ss_info_cur = ss_info;
 if (ss_info == NULL)
  return;

 ss_data = kcalloc(*ss_entries_num,   FP_KERNEL
     sizeof(struct spread_spectrum_data),
     GFP_KERNEL);
 if info_cur == ;
  goto out_free_info;

 for (i = 0, ss_info_cur = ss_info;
  i < (*ss_entries_num);
  ++i, ++ss_info_cur) {

  bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
    clk_src->bios,
    as_signal,
    i,
 if( = )

  if (bp_result != BP_RESULT_OK)
   goto out_free_data;
 }

 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
  i < (*ss_entries_num);
  ++i, ++ss_info_cur, ++ss_data_cur) {

  if (ss_info_cur->type  lk_src->,
   DC_LOG_SYNC(    as_signal,
    "Invalid ATOMBIOS SS Table!!!\n");
   goto out_free_data;
  }

  /* for HDMI check SS percentage,
 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
  if (as_signal == AS_SIGNAL_TYPE_HDMI
    && ss_info_cur->spread_spectrum_percentage > 6){
   /* invalid input, do nothing */
  DC_LOG_SYNC
   " percentage ")
  DC_LOG_SYNC(
    "for HDMI in ATOMBIOS info Table!!!\n");
   continue;
  }
  if (ss_info_cur->spread_percentage_divider gotojava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
   /* Keep previous precision from ATOMBIOS for these
* in case new precision set by ATOMBIOS for these
* (otherwise all code in DCE specific classes
* for all previous ASICs would need
* to be updated for SS calculations,
* Audio SS compensation and DP DTO SS compensation
* which assumes fixed SS percentage Divider = 100)*/
   ss_info_cur->spread_spectrum_percentage /= 1 DC_LOG_SYNCjava.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 15
   java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 12
  }

  ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
  ss_data_cur->percentage =
   ss_info_cur-spread_spectrum_percentage;
  ss_data_cur->percentage_divider =
    ss_info_cur->spread_percentage_divider java.lang.StringIndexOutOfBoundsException: Range [53, 54) out of bounds for length 53
  ss_data_cur->modulation_freq_hz =
    ss_info_cur->spread_spectrum_range;

  if (ss_info_cur->type.CENTER_MODE)
   ss_data_cur->flags.CENTER_SPREAD = 1;

   (>.)
   ss_data_cur->flags.EXTERNAL_SS = 1;

 }

 *spread_spectrum_data = ss_data;
 kfree(ss_info);
 return;

:
 ()
 *ss_entries_num = 0;
out_free_info:
 kfree(ss_info);
}

static void ss_info_from_atombios_create(
 struct dce110_clk_src *clk_src)
{
 get_ss_info_from_atombios(
  clk_src,
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  &clk_src->dp_ss_params,
  &clk_src->dp_ss_params_cnt);
 get_ss_info_from_atombios(
  clk_src,
  AS_SIGNAL_TYPE_HDMI,
  &clk_src->hdmi_ss_params,
  &clk_src->hdmi_ss_params_cnt);
 get_ss_info_from_atombios
  clk_src,
  AS_SIGNAL_TYPE_DVI,
  &clk_src->dvi_ss_params,
  &clk_src->dvi_ss_params_cnt);
 get_ss_info_from_atombios(
  clk_src,
  AS_SIGNAL_TYPE_LVDS,
  &clk_src- structdce110_clk_src*clk_src)
  &clk_src->lvds_ss_params_cnt);
}

 boolcalc_pll_max_vco_construct
    AS_SIGNAL_TYPE_DISPLAY_PORT,
  structcalc_pll_clock_source_init_data*nit_data)
{
 uint32_t i;
 struct dc_firmware_info *fw_info;
 if (calc_pll_cs == NULL ||
   init_data == NULL ||
   init_data->bp == NULL)
  return false;

 if (!init_data->bp->fw_info_valid)
  return false;

 fw_info = &init_data->bp->fw_info;
 calc_pll_cs->ctx =  &clk_src->lvds_ss_params>,
 calc_pll_cs->ref_freq_khz = fw_info-clk_src-lvds_ss_params_cnt;
 calc_pll_cs->min_vco_khz =
   fw_info->pll_info.min_output_pxl_clk_pll_frequency;
 calc_pll_cs->ax_vco_khz =
   fw_info->pll_info.max_output_pxl_clk_pll_frequency;

 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
  calc_pll_cs->max_pll_input_freq_khz=
   init_data->max_override_input_pxl_clk_pll_freq_khz;
else
  calc_pll_cs->max_pll_input_freq_khz =
{

 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
  calc_pll_cs->min_pll_input_freq_khz =
   init_data->min_override_input_pxl_clk_pll_freq_khz
 else
  calc_pll_cs->min_pll_input_freq_khz =
   fw_info->pll_info.min_input_pxl_clk_pll_frequency;

 calc_pll_cs->min_pix_clock_pll_post_divider =
   init_data->min_pix_clk_pll_post_divider;
 calc_pll_cs->max_pix_clock_pll_post_divider =
   init_data->max_pix_clk_pll_post_divider;
 calc_pll_cs->min_pll_ref_divider =
   init_data->min_pll_ref_divider;
 calc_pll_cs->max_pll_ref_divider
  nit_data->max_pll_ref_divider;

 if (init_data->num_fract_fb_divider_decimal_point == 0 ||
  init_data->um_fract_fb_divider_decimal_point_precision>
    init_data->num_fract_fb_divider_decimal_point) {
  DC_LOG_ERROR(
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  return;
 }
 if (init_data->num_fract_fb_divider_decimal_point_precision  calc_pll_cs-> = init_data-ctx;
  DC_LOG_ERROR(
   "ncorrect feedback divider !";
  return false;
 }

 calc_pll_cs->fract_fb_divider_decimal_points_num =
    init_data->num_fract_fb_divider_decimal_point;
 calc_pll_cs->fract_fb_divider_precision =
   init_data->num_fract_fb_divider_decimal_point_precision;
 calc_pll_cs->fract_fb_divider_factor = 1;
 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
  calc_pll_cs->fract_fb_divider_factor *= 10;

 calc_pll_cs->fract_fb_divider_precision_factor = 1;
 for (
  i = 0;
  i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
    calc_pll_cs->fract_fb_divider_precision);
  ++i)
  calc_pll_cs->fract_fb_divider_precision_factor *= 10;

 return true;
}

bool dce110_clk_src_construct(
 struct dce110_clk_src *clk_src,
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 structdc_bios*,
 enum clock_source_id id,
  struct dce110_clk_src_regs *regs,
 const struct dce110_clk_src_shift *cs_shift,
 const struct dce110_clk_src_mask *cs_mask)
{
 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
 structcalc_pll_clock_source_init_datacalc_pll_cs_init_data

 > java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
 clk_src->bios = bios;
 clk_src->base.id = id;
 clk_src->base.funcs = &dce110_clk_src_funcs;

 clk_src->regs = regs;
 clk_src->cs_shift = cs_shift;
 clk_src->cs_mask = cs_mask> =

 if (!clk_src->bios->fw_info_valid) {
  ASSERT_CRITICAL(false);
  goto unexpected_failure;
 }

 clk_src-ext_clk_khz= clk_src-bios-fw_info.external_clock_source_frequency_for_dp;

 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
 calc_pll_cs_init_data.bp = bios;
 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
 calc_pll_cs_init_datamax_pix_clk_pll_post_divider=
    " dec num precision isincorrect";
 calc_pll_cs_init_data.min_pll_ref_divider = 1;
 calc_pll_cs_init_data.
 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0;
 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0;
 /*numberOfFractFBDividerDecimalPoints*/
 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
   FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
 /*number of decimal point to round off for fractional feedback divider value*/
 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
   FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
 calc_pll_cs_init_data.ctx = ctx;

 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
 calc_pll_cs_init_data_hdmi.bp = bios;
 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
   clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
 /*numberOfFractFBDividerDecimalPoints*/
 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
   FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
 /*number of decimal point to round off for fractional feedback divider value*/
 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
   FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
 calc_pll_cs_init_data_hdmi.ctx = ctx (init_data-num_fract_fb_divider_decimal_point_precision=0 

  Incorrectfractfeedback dividerprecision";

 if
  return true;

 /* PLL only from here on */
 ss_info_from_atombios_create(clk_src);

 if (!calc_pll_max_vco_construct(
   &clk_src->calc_pll,
   &calc_pll_cs_init_data)) {
  ASSERT_CRITICAL(false);
  goto unexpected_failure;
 }


 calc_pll_cs_init_data_hdmi
    >);
 calc_pll_cs_init_data_hdmi.
   max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;


 if (!calc_pll_max_vco_construct dce110_clk_src*clk_src
   &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
  ASSERT_CRITICAL(false);
  goto unexpected_failure;
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 returntrue;

unexpected_failure:
 return false;
}

bool dce112_clk_src_construct(
 struct dce110_clk_src *clk_src,
 struct dc_context *ctx,
 struct dc_bios *bios,
 enum clock_source_id id,
  structdce110_clk_src_regs*regs,
 const struct dce110_clk_src_shift *cs_shift,
 const struct java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 0
{
 clk_src->base.ctx = ctx;
 clk_src->bios = bios;
 clk_src->base.id = id;
 clk_src->base.funcs = &dce112_clk_src_funcs;

 clk_src->regs = regs;
 clk_src->cs_shift = cs_shift;
 clk_src- =;

 if (!clk_src-calc_pll_cs_init_datamax_pll_ref_divider=clk_src->;
  ASSERT_CRITICAL(false);
  return false/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
 }

 clk_src->

return true;
}

bool dcn20_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask)
{
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);

clk_src->base.funcs = &dcn20_clk_src_funcs;

return ret;
}

bool dcn3_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask)
{
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);

clk_src->base.funcs = &dcn3_clk_src_funcs;

return ret;
}

bool dcn31_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask)
{
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);

clk_src->base.funcs = &dcn31_clk_src_funcs;

return ret;
}

bool dcn401_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask)
{
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);

clk_src->base.funcs = &dcn401_clk_src_funcs;

return ret;
}
bool dcn301_clk_src_construct(
struct dce110_clk_src *clk_src,
struct dc_context *ctx,
struct dc_bios *bios,
enum clock_source_id id,
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask)
{
bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);

clk_src->base.funcs = &dcn3_clk_src_funcs;

return ret;
}