/* * Get Replay state from firmware.
*/ staticvoid dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state *state, uint8_t panel_inst)
{
uint32_t retry_count = 0;
do { // Send gpint command and wait for ack if (!dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst,
(uint32_t *)state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) { // Return invalid state when GPINT times out
*state = REPLAY_STATE_INVALID;
}
} while (++retry_count <= 1000 && *state == REPLAY_STATE_INVALID);
// Assert if max retry hit if (retry_count >= 1000 && *state == REPLAY_STATE_INVALID) {
ASSERT(0); /* To-do: Add retry fail log */
}
}
/* Below loops 1000 x 500us = 500 ms. * Exit REPLAY may need to wait 1-2 frames to power up. Timeout after at * least a few frames. Should never hit the max retry assert below.
*/ if (wait) { for (retry_count = 0; retry_count <= 1000; retry_count++) {
dmub_replay_get_state(dmub, &state, panel_inst);
if (enable) { if (state != REPLAY_STATE_0) break;
} else { if (state == REPLAY_STATE_0) break;
}
/* must *not* be fsleep - this can be called from high irq levels */
udelay(500);
}
/* assert if max retry hit */ if (retry_count >= 1000)
ASSERT(0);
}
}
/* * Set REPLAY power optimization flags.
*/ staticvoid dmub_replay_set_power_opt(struct dmub_replay *dmub, unsignedint power_opt, uint8_t panel_inst)
{ union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx;
/* * Setup Replay by programming phy registers and sending replay hw context values to firmware.
*/ staticbool dmub_replay_copy_settings(struct dmub_replay *dmub, struct dc_link *link, struct replay_context *replay_context,
uint8_t panel_inst)
{ union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; struct dmub_cmd_replay_copy_settings_data *copy_settings_data
= &cmd.replay_copy_settings.replay_copy_settings_data; struct pipe_ctx *pipe_ctx = NULL; struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; int i = 0;
for (i = 0; i < MAX_PIPES; i++) { if (res_ctx &&
res_ctx->pipe_ctx[i].stream &&
res_ctx->pipe_ctx[i].stream->link &&
res_ctx->pipe_ctx[i].stream->link == link &&
res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
pipe_ctx = &res_ctx->pipe_ctx[i]; //TODO: refactor for multi edp support break;
}
}
switch (mode) { case PR_RESIDENCY_MODE_PHY:
param |= REPLAY_RESIDENCY_FIELD_MODE_PHY; break; case PR_RESIDENCY_MODE_ALPM:
param |= REPLAY_RESIDENCY_FIELD_MODE_ALPM; break; case PR_RESIDENCY_MODE_IPS2:
param |= REPLAY_RESIDENCY_REVISION_1;
param |= REPLAY_RESIDENCY_FIELD_MODE2_IPS; break; case PR_RESIDENCY_MODE_FRAME_CNT:
param |= REPLAY_RESIDENCY_REVISION_1;
param |= REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT; break; case PR_RESIDENCY_MODE_ENABLEMENT_PERIOD:
param |= REPLAY_RESIDENCY_REVISION_1;
param |= REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD; break; default: break;
}
if (is_start)
param |= REPLAY_RESIDENCY_ENABLE;
for (i = 0; i < GPINT_RETRY_NUM; i++) { // Send gpint command and wait for ack if (dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__REPLAY_RESIDENCY, param,
residency, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) return;
udelay(100);
}
// it means gpint retry many times
*residency = 0;
}
/* * Set REPLAY power optimization flags and coasting vtotal.
*/ staticvoid dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub, unsignedint power_opt, uint8_t panel_inst, uint32_t coasting_vtotal)
{ union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal *pCmd = NULL;
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