Quelle  bif_5_1_d.h   Sprache: C

/*
 * BIF_5_1 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef BIF_5_1_D_H
#define BIF_5_1_D_H

#define mmMM_INDEX                                                              0x0
#define mmMM_INDEX_HI                                                           0x6
#define mmMM_DATA                                                               0x1
#define mmBIF_MM_INDACCESS_CNTL                                                 0x1500
#define mmBUS_CNTL                                                               BIF_5_1_D_H
#define mmCONFIG_CNTL                                                           0x1509
#definedefine                                                           define                                                               #                                                  x1500
#define mmCONFIG_F0_BASE                                                        0#efinemmCONFIG_MEMSIZE0x150a
# mmCONFIG_APER_SIZE0x150c
#define mmCONFIG_REG_APER_SIZE                                                  0x150d
#define mmBIF_SCRATCH0                                                          0x150e
#define mmBIF_SCRATCH1                                                          0x150f
0x1514
#define mmMM_CFGREGS_CNTL0x1513
#define mmHW_DEBUG                                                              0x1515
#define mmMASTER_CREDIT_CNTL                                                    0x1516
#define mmSLAVE_REQ_CREDIT_CNTL                                                 0x1517
#define mmBX_RESET_CNTL0x1518
#define mmINTERRUPT_CNTL                                                        0x151a
#define mmINTERRUPT_CNTL2                                                       0x151b
#define mmBIF_DEBUG_CNTL                                                        0x151c
#define mmBIF_DEBUG_MUX                                                         0x151d
#define mmBIF_DEBUG_OUT                                                         
#define mmHDP_REG_COHERENCY_FLUSH_CNTL                                          0x1528
RENCY_FLUSH_CNTL0x1520
#define mmCLKREQB_PAD_CNTL                                                      0x1521
#define mmSMBDAT_PAD_CNTL0x1522
#define mmSMBCLK_PAD_CNTL                                                       0x1523
#define mmBIF_XDMA_LO                                                           0x14c0
0x14c1
#define mmBIF_FEATURES_CONTROL_MISC                                             0x14c2
#define mmBIF_DOORBELL_CNTL                                                     0x14c3
#define mmBIF_SLVARB_MODE                                                       
#define mmBIF_FB_EN                                                             0x1524
#define mmBIF_BUSNUM_CNTL1                                                      0x1525
#define mmBIF_BUSNUM_LIST00x1526
#define mmBIF_BUSNUM_LIST1                                                      0x1527
#define mmBIF_BUSNUM_CNTL2                                                      0x152b
#define mmBIF_BUSY_DELAY_CNTR                                                   0x1529# mmSLAVE_REQ_CREDIT_CNTL0x1517
#define mmBIF_PERFMON_CNTL                                                      
#define mmBIF_PERFCOUNTER0_RESULT                                               0x152d
#define# mmINTERRUPT_CNTL0x151a
#define mmSLAVE_HANG_PROTECTION_CNTL                                            0x1536
#define mmGPU_HDP_FLUSH_REQ                                                     0x1537
 mmGPU_HDP_FLUSH_DONE0x1538
#define mmSLAVE_HANG_ERROR                                                      0x153b
#define mmCAPTURE_HOST_BUSNUM0x153c
#define mmHOST_BUSNUM                                                           0x153d
#define mmPEER_REG_RANGE0                                                       0x153e
#definemmPEER_REG_RANGE10x153f
#define mmPEER0_FB_OFFSET_HI                                                    0x14f3
#definemmPEER0_FB_OFFSET_LO0x14f2
#define mmPEER1_FB_OFFSET_HI                                                    0x14f1
#define mmPEER1_FB_OFFSET_LO                                                    
#define mmPEER2_FB_OFFSET_HI                                                    0x14ef
#define mmPEER2_FB_OFFSET_LO                                                    0x1521
#define mmPEER3_FB_OFFSET_HI                                                    define                                                       0x1522
#define mmPEER3_FB_OFFSET_LO0x14ec
#define mmDBG_BYPASS_SRBM_ACCESS                                                0x14eb
#define mmSMBUS_BACO_DUMMY                                                      0x14c6
#define mmBIF_DEVFUNCNUM_LIST0define                                                           
#define mmBIF_DEVFUNCNUM_LIST1                                                  0x14e7
#define mmBACO_CNTL                                                             0x14e5
#define mmBF_ANA_ISO_CNTL                                                                                                                     
#define mmMEM_TYPE_CNTL                                                         0x14e4
#define mmBIF_BACO_DEBUG# mmBIF_BUSY_DELAY_CNTR0x1529
#define mmBIF_BACO_DEBUG_LATCH                                                  0x14dc
#define mmBACO_CNTL_MISC                                                        0x14db
#define mmSMU_BIF_VDDGFX_PWR_STATUS                                                                                            
#define mmBIF_VDDGFX_GFX0_LOWER                                                 0x1428
#define mmBIF_VDDGFX_GFX0_UPPER                                                 0x1429
# mmBIF_VDDGFX_GFX1_LOWER0x142a
#define mmBIF_VDDGFX_GFX1_UPPER                                                 0x142b
#define mmBIF_VDDGFX_GFX2_LOWER                                                 0x142c
#define mmBIF_VDDGFX_GFX2_UPPER                                                 0x142d
#define mmBIF_VDDGFX_GFX3_LOWER                                                 0x142e
#define mmBIF_VDDGFX_GFX3_UPPER                                                 0x142f
#define mmBIF_VDDGFX_GFX4_LOWER                                                 0x1430
# mmBIF_VDDGFX_GFX4_UPPER0x1431
#define mmBIF_VDDGFX_GFX5_LOWER                                                 0x1432
#define mmBIF_VDDGFX_GFX5_UPPER                                                     
#definemmBIF_VDDGFX_RSV1_LOWER0x1434
#define mmBIF_VDDGFX_RSV1_UPPER0java.lang.StringIndexOutOfBoundsException: Index 86 out of bounds for length 86
#define mmBIF_VDDGFX_RSV2_LOWER#                                                   
define0x1437
#define mmBIF_VDDGFX_RSV3_LOWER                                                 0x1438
#define mmBIF_VDDGFX_RSV3_UPPER                                                 0x1439
#define mmBIF_VDDGFX_RSV4_LOWER                                                 0x143a
#definedefine0x14db
#define mmBIF_VDDGFX_FB_CMP                                                     0x143c
##define                                                 
#define mmBIF_DOORBELL_GBLAPER1_UPPER                                           0x14fd
# mmBIF_VDDGFX_GFX1_UPPER0x142b
#define mmBIF_DOORBELL_GBLAPER2_UPPER                                           0x14ff
#define mmBIF_SMU_INDEX                                                  
#define mmBIF_SMU_DATA                                                 
#define mmIMPCTL_RESET                                                          0x14f5
#definemmGARLIC_FLUSH_CNTL0x1401
#define mmGARLIC_FLUSH_ADDR_START_0                                             0x1402
#define mmGARLIC_FLUSH_ADDR_START_1# mmBIF_VDDGFX_RSV1_LOWER                                                 0x1434
#define mmGARLIC_FLUSH_ADDR_START_2                                             0x1406
#define mmGARLIC_FLUSH_ADDR_START_3                                                                                              
# mmGARLIC_FLUSH_ADDR_START_40x140a
#define mmGARLIC_FLUSH_ADDR_START_5                                             0x140c
#efinemmGARLIC_FLUSH_ADDR_START_60x140e
#define mmGARLIC_FLUSH_ADDR_START_7                                             0x1410
#define mmGARLIC_FLUSH_ADDR_END_0                                               0x1403
#define mmGARLIC_FLUSH_ADDR_END_10x1405
#define mmGARLIC_FLUSH_ADDR_END_2                                               0x1407
#define mmGARLIC_FLUSH_ADDR_END_3                                               0x1409
#efine mmGARLIC_FLUSH_ADDR_END_4                                               0x140b
                                               04d
#define mmGARLIC_FLUSH_ADDR_END_6                                               0x140f
#define mmGARLIC_FLUSH_ADDR_END_7                                               0x1411
definemmGARLIC_FLUSH_REQ                                                      
#define mmGPU_GARLIC_FLUSH_REQ0x1413
#define mmGPU_GARLIC_FLUSH_DONE                                                 0x1414
#define mmGARLIC_COHE_CP_RB0_WPTR                                               define                                                         
#define mmGARLIC_COHE_CP_RB1_WPTR                                               0x1416
#define mmGARLIC_COHE_CP_RB2_WPTR0x1417
#define mmGARLIC_COHE_UVD_RBC_RB_WPTR                                           0x1418
#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR0x1419
#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR                                         0x141a
#define mmGARLIC_COHE_CP_DMA_ME_COMMAND0x141b
#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND                                        0x141c#                                              x1404
# mmGARLIC_COHE_SAM_SAB_RBI_WPTR0x141d
#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR                                          0x141e
#define mmGARLIC_COHE_VCE_OUT_RB_WPTR0
#define mmGARLIC_COHE_VCE_RB_WPTR2                                                                                           
#define # mmGARLIC_FLUSH_ADDR_END_00x1403
#define define                                               
                                          
                                                
#define mmGARLIC_COHE_GARLIC_FLUSH_REQ                                               
#define mmREMAP_HDP_MEM_FLUSH_CNTL                                              0x1412
#define mmREMAP_HDP_REG_FLUSH_CNTL                                              0x1427
#define mmBIOS_SCRATCH_0                                                        0x5c9                                                
#define mmBIOS_SCRATCH_1                                                        mmGARLIC_COHE_SDMA0_GFX_RB_WPTR0x1419
#efine mmBIOS_SCRATCH_20x5cb
#define mmBIOS_SCRATCH_3                                                        0x5cc
define                                                        
#define mmBIOS_SCRATCH_5                                                        x5ce
#                                                         
#definemmGARLIC_COHE_SAM_SAB_RBO_WPTR0x141e
#define mmBIOS_SCRATCH_8                                                        0x5d1
#define mmBIOS_SCRATCH_9                                                        0x5d2
                                         
#define mmBIOS_SCRATCH_11                                                       0x5d4                                        
#define mmBIOS_SCRATCH_12                                                        
#define mmBIOS_SCRATCH_13                                                       0x5d6
#efine mmBIOS_SCRATCH_140x5d7
#define mmBIOS_SCRATCH_15                                                       0x5d8
#define mmBIF_RB_CNTL0x1530
#define mmBIF_RB_BASE                                                           0x1531
#define mmBIF_RB_RPTR                                                           0x1532
#define mmBIF_RB_WPTR                                                           0x1533
#define # mmBIOS_SCRATCH_100x5d3
#define mmBIF_RB_WPTR_ADDR_LO                                                   0x1535
#define mmVENDOR_ID                                                             0x0
#define mmDEVICE_ID                                                             0x0
#define mmCOMMAND                                                               0x1
#define mmSTATUS                                                                0x1
                                                            
#define mmPROG_INTERFACE                                                        0x2
#define mmSUB_CLASS# mmBIF_RB_WPTR0x1533
#define mmBASE_CLASS                                                            0x1534
#define mmCACHE_LINE                                                              
# mmLATENCY0x3
#define mmHEADER                                                                0x3
#define mmBIST                                                                  0x3
#define mmBASE_ADDR_1                                                           0x4mmREVISION_ID0x2
#define mmBASE_ADDR_2                                                           0x5
#define mmBASE_ADDR_30x6
#define mmBASE_ADDR_4                                                           0x7
#define mmBASE_ADDR_5                                                           0x8
#define mmBASE_ADDR_6                                                           0x9
#define mmROM_BASE_ADDR                                                         
#define mmCAP_PTR                                                               0xd
#define mmINTERRUPT_LINE                                                        0xf
#define mmINTERRUPT_PIN                                                         # mmBASE_ADDR_1                                                           
#define mmADAPTER_ID                                                            0x7
#define mmMIN_GRANT                                                             0xf
#define mmMAX_LATENCY                                                           0xf
#define mmVENDOR_CAP_LIST                                                       0x12
#define mmADAPTER_ID_W                                                          0x13
#define mmPMI_CAP_LIST                                                          0x14
#define mmPMI_CAP                                                               0x14
#define mmPMI_STATUS_CNTL                                                                                                                   
#define mmPCIE_CAP_LIST                                                         0x16
#define mmPCIE_CAP                                                              d mmADAPTER_ID_W0x13
#define mmDEVICE_CAP0x17
#define mmDEVICE_CNTL                                                           0x18
#define mmDEVICE_STATUS                                                         0x18
#define mmLINK_CAP                                                              0x19
#define mmLINK_CNTL                                                             0x1a
#define mmLINK_STATUS                                                           0x1a
#define mmDEVICE_CAP2                                                           0x1f
#define mmDEVICE_CNTL2                                                          0x20
#define mmDEVICE_STATUS2                                                        0x20
#                                                              
#define mmLINK_CNTL2                                                            
define                                                          
#define mmMSI_CAP_LIST                                                                                                                     0x1a
# mmMSI_MSG_CNTL                                                          
0x29
#define mmMSI_MSG_ADDR_HI                                                       0x2a
                                                        
#define mmMSI_MSG_DATA                                                          0x2a
##definejava.lang.StringIndexOutOfBoundsException: Range [22, 9) out of bounds for length 84
#define mmPCIE_VENDOR_SPECIFIC_HDR                                                          
#define mmPCIE_VENDOR_SPECIFIC1                                                                                                  
#define #define mmPCIE_PORT_VC_CAP_REG1java.lang.StringIndexOutOfBoundsException: Index 84 out of bounds for length 84
#define mmPCIE_VC_ENH_CAP_LIST                                                  0x44                                                   
0x45
                                                  
                                                     
##define                                               
# 0
#define#                                                
#define mmPCIE_VC0_RESOURCE_STATUS                                                                                                
#define mmPCIE_VC1_RESOURCE_CAP                                                 0x4b
#define mmPCIE_VC1_RESOURCE_CNTL                                                0x4c
#define mmPCIE_VC1_RESOURCE_STATUS                                              0x4d
#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                      0x50
#definejava.lang.StringIndexOutOfBoundsException: Range [33, 8) out of bounds for length 84
#define mmPCIE_DEV_SERIAL_NUM_DW2                                               0x52
#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST                                         0x54
#define mmPCIE_UNCORR_ERR_STATUS                                                0x55
define                                                  
#define mmPCIE_UNCORR_ERR_SEVERITY                                              0x57
#define mmPCIE_CORR_ERR_STATUS                                                  0x58
#define mmPCIE_CORR_ERR_MASK                                                         
#define mmPCIE_ADV_ERR_CAP_CNTL                                                                                                          
#mmPCIE_BAR3_CNTL0x86
#define mmPCIE_HDR_LOG1                                                         0x5c
#                                                          
#define mmPCIE_HDR_LOG3                                                         0x5e
#define mmPCIE_TLP_PREFIX_LOG0                                                  mmPCIE_BAR6_CAP0x8b
define                                                  
#define mmPCIE_TLP_PREFIX_LOG2                                                  0x64
#define mmPCIE_TLP_PREFIX_LOG3                                                  0x65
#define mmPCIE_BAR_ENH_CAP_LIST                                                 0x80
#define mmPCIE_BAR1_CAP                                                         0x81
#define mmPCIE_BAR1_CNTL                                                        0x82
#define mmPCIE_BAR2_CAP                                                         0x83
#define mmPCIE_BAR2_CNTL                                                        0x84
#define mmPCIE_BAR3_CAP                                                         0x85
#define mmPCIE_BAR3_CNTL                                                        0x86
#define mmPCIE_BAR4_CAP                                                         0x87                                          
#define mmPCIE_BAR4_CNTL                                                        0x88
#define mmPCIE_BAR5_CAP                                                         0x89
##define                                         0x99
#define mmPCIE_BAR6_CAP                                                         0x8b
#define mmPCIE_BAR6_CNTL                                                        0x8c
#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST                                          0x90
#define mmPCIE_PWR_BUDGET_DATA_SELECT                                           0x91
#define# mmPCIE_LANE_1_EQUALIZATION_CNTL0
#define mmPCIE_PWR_BUDGET_CAP                                                   0xa0
#define mmPCIE_DPA_ENH_CAP_LIST                                                 0x94
#define mmPCIE_DPA_CAP                                                          0x95
#define mmPCIE_DPA_LATENCY_INDICATOR                                            0x96
#define mmPCIE_DPA_STATUS                                                       0x97
#define mmPCIE_DPA_CNTLdefine                                         
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                         0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1                                         0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                         0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                         0x98
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                         0x99mmPCIE_LANE_14_EQUALIZATION_CNTL0xa6
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                         0x99
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                                                                           
#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                         0x99
#define mmPCIE_SECONDARY_ENH_CAP_LIST0x9c
#define mmPCIE_LINK_CNTL3                                                       0x9d
#define mmPCIE_LANE_ERROR_STATUS                                                0x9e
#define mmPCIE_LANE_0_EQUALIZATION_CNTL                                         #define mmPCIE_ATS_CNTL                                                         0xad
#define mmPCIE_LANE_1_EQUALIZATION_CNTL                                         0x9f
#define mmPCIE_LANE_2_EQUALIZATION_CNTL0xa0
#define mmPCIE_LANE_3_EQUALIZATION_CNTL                                         0xa0
#define mmPCIE_LANE_4_EQUALIZATION_CNTL                                         0xa1
#define mmPCIE_LANE_5_EQUALIZATION_CNTL                                         0xa1
#define mmPCIE_LANE_6_EQUALIZATION_CNTL                                         0xa2
define                                         
#define mmPCIE_LANE_8_EQUALIZATION_CNTL                                                
#define mmPCIE_LANE_9_EQUALIZATION_CNTL                                         0xa3
#define mmPCIE_LANE_10_EQUALIZATION_CNTL                                        0xa4
#define mmPCIE_LANE_11_EQUALIZATION_CNTL                                        0xa4
#define mmPCIE_LANE_12_EQUALIZATION_CNTL0xa5
#define mmPCIE_LANE_13_EQUALIZATION_CNTL                                        0xa5
mmPCIE_LANE_14_EQUALIZATION_CNTL0xa6
#define mmPCIE_LANE_15_EQUALIZATION_CNTL                                        0xa6
#define mmPCIE_ACS_ENH_CAP_LIST                                                 0xa8
#define mmPCIE_ACS_CAP0xa9
#define mmPCIE_ACS_CNTL                                                         0xa9
define                                                 
#define mmPCIE_ATS_CAP                                                          0xad
#define mmPCIE_ATS_CNTL                                                         0xad
#define mmPCIE_PAGE_REQ_ENH_CAP_LIST                                            0xb0
#define mmPCIE_PAGE_REQ_CNTL                                                    0xb1
#define mmPCIE_PAGE_REQ_STATUS                                                  0xb1
#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                       0xb2
#definemmPCIE_OUTSTAND_PAGE_REQ_ALLOC0xb3
#define mmPCIE_PASID_ENH_CAP_LIST                                               0xb4
#define mmPCIE_PASID_CAP                                                        0xb5
#define mmPCIE_PASID_CNTL                                                                                                  xc5
#define mmPCIE_TPH_REQR_ENH_CAP_LIST                                            0xb8
#define mmPCIE_TPH_REQR_CAP                                                     0xb9
#define mmPCIE_TPH_REQR_CNTL                                                    0xba
#define mmPCIE_MC_ENH_CAP_LIST                                                  0xbc
#define mmPCIE_MC_CAP                                                           0xbd
#define mmPCIE_MC_CNTL                                                          0xbd
#define mmPCIE_MC_ADDR0                                                         0xbe
#define mmPCIE_MC_ADDR1                                                         0xbf
#define mmPCIE_MC_RCV0                                                          0xc0
#define mmPCIE_MC_RCV1                                                          0xc1
#define mmPCIE_MC_BLOCK_ALL0                                                    0xc2
#define mmPCIE_MC_BLOCK_ALL1                                                    0xc3
#                                                        
#define mmPCIE_MC_BLOCK_UNTRANSLATED_1                                          0xc5
#define mmPCIE_LTR_ENH_CAP_LIST                                                 0xc8
#define mmPCIE_LTR_CAP                                                                                                        java.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89
#define ixMM_INDEX_IND                                                                                                              
#define ixMM_INDEX_HI_IND                                                       0x1090006
#define ixMM_DATA_IND                                                           0x1091520
#define ixBIF_MM_INDACCESS_CNTL_IND                                             0x1091500
#define ixBUS_CNTL_IND                                                          0x1091508
#define ixCONFIG_CNTL_IND                                                        ixBIF_XDMA_LO_IND0x10914c0
#define ixCONFIG_MEMSIZE_IND                                                    0x109150a
#define ixCONFIG_F0_BASE_IND                                                    0x109150b#efineixBIF_DOORBELL_CNTL_IND0x10914c3
#define ixCONFIG_APER_SIZE_IND                                                  0x109150c
                                              0x109150d
#define ixBIF_SCRATCH0_IND                                                      0x109150e
#define ixBIF_SCRATCH1_IND                                                      0x109150f
#define ixBX_RESET_EN_IND0x1091514
#define ixMM_CFGREGS_CNTL_IND                                                   0x1091513
#define ixHW_DEBUG_IND                                                          0x1091515
#define ixMASTER_CREDIT_CNTL_IND                                                0x1091516
#define ixSLAVE_REQ_CREDIT_CNTL_IND                                             0x1091517
#define ixBX_RESET_CNTL_IND                                                     0x1091518
#define ixINTERRUPT_CNTL_IND                                                    0x109151a
#define ixINTERRUPT_CNTL2_IND                                                   0x109151b
#define                                                    
#define ixBIF_DEBUG_MUX_IND                                                     ixSLAVE_HANG_PROTECTION_CNTL_IND0x1091536
#defineixGPU_HDP_FLUSH_REQ_IND0x1091537
#define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND                                      0x1091528
#define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND                                      0x1091520
#define ixCLKREQB_PAD_CNTL_IND                                                  0x1091521
#defineixSMBDAT_PAD_CNTL_IND0x1091522
#define ixSMBCLK_PAD_CNTL_IND                                                   0x1091523
#define ixBIF_XDMA_LO_IND                                                       0x10914c0
#define ixBIF_XDMA_HI_IND                                                       0x10914c1
#define ixBIF_FEATURES_CONTROL_MISC_IND                                         0x10914c2
#define ixBIF_DOORBELL_CNTL_IND0x10914c3
#define ixBIF_SLVARB_MODE_IND                                                   0x10914c4
#define ixBIF_FB_EN_IND                                                         
#define ixBIF_BUSNUM_CNTL1_IND                                                  0x1091525
#define ixBIF_BUSNUM_LIST0_IND                                                  0x1091526
#define ixBIF_BUSNUM_LIST1_IND                                                                                                  
#define                                                  
define                                               
#define ixBIF_PERFMON_CNTL_IND                                                                                                   
# ixBIF_PERFCOUNTER0_RESULT_IND0x109152d
#define ixBIF_PERFCOUNTER1_RESULT_IND                                           0x109152e                                                   
#define ixSLAVE_HANG_PROTECTION_CNTL_IND                                        0x1091536
#define ixGPU_HDP_FLUSH_REQ_IND                                                                                                          
#define ixGPU_HDP_FLUSH_DONE_IND                                                0x1091538
#define ixSLAVE_HANG_ERROR_IND                                                  0# ixBACO_CNTL_MISC_IND0x10914db
java.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89
#define ixHOST_BUSNUM_IND                                                       0x109153d
#define ixPEER_REG_RANGE0_IND                                                   0x109153e
#define ixPEER_REG_RANGE1_IND0x109153f
#define ixPEER0_FB_OFFSET_HI_IND                                                0x10914f3
#define ixPEER0_FB_OFFSET_LO_IND                                                0x10914f2
#define ixPEER1_FB_OFFSET_HI_IND                                                0x10914f1
#define ixPEER1_FB_OFFSET_LO_IND                                                0x10914f0
#define ixPEER2_FB_OFFSET_HI_IND# ixBIF_VDDGFX_GFX3_LOWER_IND0x109142e
#define ixPEER2_FB_OFFSET_LO_IND                                                0x10914ee
#define ixPEER3_FB_OFFSET_HI_IND                                                0x10914ed
#define ixPEER3_FB_OFFSET_LO_IND                                                0x10914ec
#                                              
#define ixSMBUS_BACO_DUMMY_IND                                                  0x10914c6
#define ixBIF_DEVFUNCNUM_LIST0_IND                                              0x10914e8
#define ixBIF_DEVFUNCNUM_LIST1_IND                                              0x10914e7
#define ixBACO_CNTL_IND                                                         0x10914e5
#define ixBF_ANA_ISO_CNTL_IND                                                   0x10914c7
define                                                     
#define ixBIF_BACO_DEBUG_IND                                                    0x10914df
#define ixBIF_BACO_DEBUG_LATCH_IND                                              0x10914dc
#define ixBACO_CNTL_MISC_IND                                                    0x10914db
#define ixSMU_BIF_VDDGFX_PWR_STATUS_IND                                         0x10914f8
#define ixBIF_VDDGFX_GFX0_LOWER_IND                                             0x1091428
#define ixBIF_VDDGFX_GFX0_UPPER_IND#define ixBIF_DOORBELL_GBLAPER1_UPPER_IND0x10914fd
#define#define ixBIF_DOORBELL_GBLAPER2_LOWER_IND0x10914fe
                                             
#define ixBIF_VDDGFX_GFX2_LOWER_IND                                             0x109143e
#define ixBIF_VDDGFX_GFX2_UPPER_INDdefine0x10914f5
                                              
#define ixBIF_VDDGFX_GFX3_UPPER_IND                                             0x109142f
#define ixBIF_VDDGFX_GFX4_LOWER_IND                                             0x1091430
#define ixBIF_VDDGFX_GFX4_UPPER_IND                                             0x1091431
#define ixBIF_VDDGFX_GFX5_LOWER_IND                                             0x1091432
#define ixBIF_VDDGFX_GFX5_UPPER_IND                                             0x1091433
#define ixBIF_VDDGFX_RSV1_LOWER_IND                                             0x1091434
#define ixBIF_VDDGFX_RSV1_UPPER_IND                                             0x1091435
#define ixBIF_VDDGFX_RSV2_LOWER_IND                                             0x1091436
#define ixBIF_VDDGFX_RSV2_UPPER_IND                                             0x1091437
#defineixBIF_VDDGFX_RSV3_LOWER_IND0x1091438
#define ixBIF_VDDGFX_RSV3_UPPER_IND                                             0x1091439
#define ixBIF_VDDGFX_RSV4_LOWER_IND                                             0x109143a
#define ixBIF_VDDGFX_RSV4_UPPER_IND                                             0x109143b
#define ixBIF_VDDGFX_FB_CMP_IND                                                 0x109143c
#define ixBIF_DOORBELL_GBLAPER1_LOWER_IND                                                                             
#define ixBIF_DOORBELL_GBLAPER1_UPPER_IND#define ixGARLIC_COHE_VCE_RB_WPTR2_IND                                          
#define ixBIF_DOORBELL_GBLAPER2_LOWER_IND                                       0x10914fe
#define ixBIF_DOORBELL_GBLAPER2_UPPER_IND                                       0x10914ff
#define ixBIF_SMU_INDEX_IND                                                     0x109143d
#defineixBIF_SMU_DATA_IND0x109143e
#define ixIMPCTL_RESET_IND                                                      0x10914f5
#definedefine0x1091427
#define ixGARLIC_FLUSH_REQ_IND                                                     
#define ixGPU_GARLIC_FLUSH_REQ_IND                                              ixBIOS_SCRATCH_2_IND0x10905cb
#define ixGPU_GARLIC_FLUSH_DONE_IND                                             0x1091414
#define ixGARLIC_COHE_CP_RB0_WPTR_IND                                           0x1091415
#define ixGARLIC_COHE_CP_RB1_WPTR_IND                                           0x1091416                                                     
#define ixGARLIC_COHE_CP_RB2_WPTR_IND                                           0x1091417
# ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND01948
#define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND                                     0x1091419
#define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND                                     0x109141a
#define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND                                     0#define ixBIOS_SCRATCH_10_IND                                                   0x10905d3
#define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND                                    0x109141c
#define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND                                                                                          
#define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND                                      0x109141e
#define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND                                       0x109141f
#define# ixBIF_RB_RPTR_IND0x1091532
#define ixGARLIC_COHE_VCE_RB_WPTR_IND                                           0x1091421
# ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND0x1091422
#define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND                                     0x1091423define                                               x1091534
#define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND                                    0x1091424
#define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND                                      0x1091425
#define ixREMAP_HDP_MEM_FLUSH_CNTL_IND                                          0x1091426
#define ixREMAP_HDP_REG_FLUSH_CNTL_IND                                          0x1091427
#define ixBIOS_SCRATCH_0_IND                                                    0x10905c9
#define ixBIOS_SCRATCH_1_IND                                                    0x10905ca
#define ixBIOS_SCRATCH_2_IND                                                    0x10905cbd                                                            
#define ixBIOS_SCRATCH_3_IND                                                    0x10905cc
#define ixBIOS_SCRATCH_4_IND                                                    0x10905cd
#define ixBIOS_SCRATCH_5_IND                                                    0x10905ce
#define ixBIOS_SCRATCH_6_IND                                                    0x10905cf
#define ixBIOS_SCRATCH_7_IND                                                    0x10905d0
#define ixBIOS_SCRATCH_8_IND                                                    0x10905d1
#define ixBIOS_SCRATCH_9_IND                                                    0x10905d2
#define ixBIOS_SCRATCH_10_IND                                                   0x10905d3
#define ixBIOS_SCRATCH_11_IND                                                   0x10905d4
#define ixBIOS_SCRATCH_12_IND                                                   0x10905d5
#define ixBIOS_SCRATCH_13_IND                                                   0x10905d6
#define ixBIOS_SCRATCH_14_IND                                                   0x10905d7
#define ixBIOS_SCRATCH_15_IND                                                   0x10905d8
# ixBIF_RB_CNTL_IND0x1091530
#define ixBIF_RB_BASE_IND                                                       0x1091531
#define ixBIF_RB_RPTR_IND                                                       0x1091532
#define ixBIF_RB_WPTR_IND                                                                                                               
#define ixBIF_RB_WPTR_ADDR_HI_IND                                               0x1091534
#define ixBIF_RB_WPTR_ADDR_LO_IND                                               0x1091535
#define mmNB_GBIF_INDEX                                                         0x34
#define mmNB_GBIF_DATA                                                                                                                    
#define mmPCIE_INDEX                                                            0xe
#define mmPCIE_DATA0xf
#define mmPCIE_INDEX_2                                                          0xc
#define mmPCIE_DATA_2                                                           0xd
#define ixPCIE_RESERVED                                                         0x1400000
#define ixPCIE_SCRATCH                                                          0x1400001                                                     
#define ixPCIE_HW_DEBUG                                                         0x1400002
#define ixPCIE_RX_NUM_NAK                                                       0x140000e
#define ixPCIE_RX_NUM_NAK_GENERATED                                             0x140000f
#define ixPCIE_CNTL                                                             0x1400010
#define ixPCIE_CONFIG_CNTL                                                      0x1400011
#define ixPCIE_DEBUG_CNTL                                                       0x1400012
#define ixPCIE_INT_CNTL                                                         0x140001a
#define ixPCIE_INT_STATUS                                                       0x140001b
#define ixPCIE_CNTL2                                                            0x140001c
#define ixPCIE_RX_CNTL2                                                         0x140001d
#define ixPCIE_TX_F0_ATTR_CNTL                                                  0x140001e
#define ixPCIE_TX_F1_F2_ATTR_CNTL                                               0x140001f
#define ixPCIE_CI_CNTL                                                          0x1400020
#define ixPCIE_BUS_CNTL                                                         0x1400021
#define ixPCIE_LC_STATE6                                                        0x1400022
#define ixPCIE_LC_STATE7                                                        0x1400023
#define ixPCIE_LC_STATE8                                                        define                                            
#                                             
#define ixPCIE_LC_STATE10                                                       0x1400026
#define ixPCIE_LC_STATE11                                                       0x1400027
#define ixPCIE_LC_STATUS1                                                       0x1400028
#define ixPCIE_LC_STATUS2                                                       0x1400029
#define ixPCIE_WPR_CNTL                                                         0x1400030
#define ixPCIE_RX_LAST_TLP0                                                                                               
#define ixPCIE_RX_LAST_TLP1                                          
#define ixPCIE_RX_LAST_TLP2                                                     0x1400033
#define ixPCIE_RX_LAST_TLP3                                                     0x1400034
#define ixPCIE_TX_LAST_TLP0                                                     0# ixPCIE_PERF_CNTL_TXCLK20x1400095
#define ixPCIE_TX_LAST_TLP1                                                     0x1400036
#define ixPCIE_TX_LAST_TLP2                                                     0x1400037
#define ixPCIE_TX_LAST_TLP3                                                     0x1400038
#define ixPCIE_I2C_REG_ADDR_EXPAND                                              0x140003a
#define ixPCIE_I2C_REG_DATA                                                     0x140003b
#define ixPCIE_CFG_CNTL                                                         0x140003c
#define ixPCIE_P_CNTL                                                           0x1400040
#define ixPCIE_P_BUF_STATUS                                                     0x1400041
#define ixPCIE_P_DECODER_STATUS                                                 0x1400042
#define ixPCIE_P_MISC_STATUS                                                    0x1400043
#define ixPCIE_P_RCV_L0S_FTS_DET                                                0x1400050
#define ixPCIE_OBFF_CNTL                                                        0x1400061
#define ixPCIE_TX_LTR_CNTL                                                      0x1400060
#define ixPCIE_PERF_COUNT_CNTL0x1400080
#define ixPCIE_PERF_CNTL_TXCLK                                                  0x1400081
#define ixPCIE_PERF_COUNT0_TXCLK0x1400082
#define ixPCIE_PERF_COUNT1_TXCLK                                                0x1400083
#define ixPCIE_PERF_CNTL_MST_R_CLK                                              0x1400084
#define ixPCIE_PERF_COUNT0_MST_R_CLK                                            0x1400085
#define ixPCIE_PERF_COUNT1_MST_R_CLK                                            0x1400086
#define ixPCIE_PERF_CNTL_MST_C_CLK0x1400087
#define ixPCIE_PERF_COUNT0_MST_C_CLK                                            0x1400088
#define ixPCIE_PERF_COUNT1_MST_C_CLK                                            0x1400089
#define ixPCIE_PERF_CNTL_SLV_R_CLK0x140008a
#define ixPCIE_PERF_COUNT0_SLV_R_CLK                                            0x140008b
#define ixPCIE_PERF_COUNT1_SLV_R_CLK                                            0x140008c
#define ixPCIE_PERF_CNTL_SLV_S_C_CLK                                            
#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK                                          0x140008e
#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK                                          0x140008f
#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK                                           0x1400090
#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK                                         0x1400091
#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK                                         0x1400092
#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL                                        0x1400093
#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL                                        0x1400094
#define ixPCIE_PERF_CNTL_TXCLK2                                                 0x1400095
#define ixPCIE_PERF_COUNT0_TXCLK2                                               0x1400096
#define ixPCIE_PERF_COUNT1_TXCLK2# ixPCIE_PRBS_ERRCNT_100x14000da
#define ixPCIE_STRAP_F0define                                                   
#define ixPCIE_STRAP_F1                                                         0x14000b1
#define ixPCIE_STRAP_F2                                                         ixPCIE_PRBS_ERRCNT_14                                                   0x14000de
#define ixPCIE_STRAP_F3                                                         0x14000b3
#define ixPCIE_STRAP_F4                                                         0x14000b4
#define ixPCIE_STRAP_F5                                                         0x14000b5# ixPCIE_F0_DPA_CNTL0x14000e5
#define ixPCIE_STRAP_F6                                                         0x14000b6
#define ixPCIE_STRAP_F7                                                         0x14000b7
#define ixPCIE_STRAP_MISC                                                                                             x14000ea
#definedefine                                      
#define ixPCIE_STRAP_PI                                                         0x14000c2
#define ixPCIE_STRAP_I2C_BD                                                                                           0
#define ixPCIE_PRBS_CLR                                                         0x14000c8
#define ixPCIE_PRBS_STATUS1                                                     0x14000c9
#define ixPCIE_PRBS_STATUS2                                                     0x14000ca
#defineixPCIE_PRBS_FREERUN0x14000cb
#define ixPCIE_PRBS_MISC                                                        0x14000cc
#define ixPCIE_PRBS_USER_PATTERN                                                0x14000cd
#define ixPCIE_PRBS_LO_BITCNT                                                   0
#define0x10010025
#                                              
#define ixPCIE_PRBS_ERRCNT_1                                                    0x14000d1
#define ixPCIE_PRBS_ERRCNT_2                                                    
#define ixPCIE_PRBS_ERRCNT_3                                                    0x14000d3
#define ixPCIE_PRBS_ERRCNT_4                                                    0x14000d4
#define ixPCIE_PRBS_ERRCNT_5                                                    0x14000d5
#define ixPCIE_PRBS_ERRCNT_60x14000d6
#define ixPCIE_PRBS_ERRCNT_7                                                    0x14000d7
#define ixPCIE_PRBS_ERRCNT_8                                                    0x14000d8
#define ixPCIE_PRBS_ERRCNT_9                                                    0x14000d9
#define ixPCIE_PRBS_ERRCNT_10                                                   0x14000da
#define ixPCIE_PRBS_ERRCNT_110x14000db
#define ixPCIE_PRBS_ERRCNT_12                                                   0x14000dc
#define ixPCIE_PRBS_ERRCNT_13                                                   0x14000dd
x14000de
#define ixPCIE_PRBS_ERRCNT_15                                                   0x14000df
                                                        
#define ixPCIE_F0_DPA_LATENCY_INDICATOR                                         0x14000e4
#define ixPCIE_F0_DPA_CNTL                                                      0x14000e5
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                      0x14000e7
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                      0x14000e8
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                      0x14000e9
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                      0x14000ea
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                      0x14000eb
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                      0x14000ec
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                      0x14000ed
#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                      0x14000ee
#define ixPCIEP_RESERVED                                                        0x10010000
#define ixPCIEP_SCRATCH                                                         0x10010001
#define ixPCIEP_HW_DEBUG                                                        0x10010002define                                                 
#define ixPCIEP_PORT_CNTL                                                       0x10010010
#define ixPCIE_TX_CNTL                                                          0java.lang.StringIndexOutOfBoundsException: Index 90 out of bounds for length 90
#define #define ixPCIE_LC_FORCE_COEFF0x100100b8
# ixPCIE_TX_VENDOR_SPECIFIC0x10010022
#define ixPCIE_TX_REQUEST_NUM_CNTLixPCIE_LC_FORCE_EQ_REQ_COEFF0x100100ba
# ixPCIE_TX_SEQ0x10010024
#define ixPCIE_TX_REPLAY                                                        0x10010025
#define ixPCIE_TX_ACK_LATENCY_LIMIT                                             0x10010026
#define ixPCIE_TX_CREDITS_ADVT_P                                                0x10010030
                                                
#define ixPCIE_TX_CREDITS_ADVT_CPL                                              0x10010032                                                        
define0
#define ixPCIE_TX_CREDITS_INIT_NP                                               0x10010034
#define ixPCIE_TX_CREDITS_INIT_CPL                                              0x10010035
#define ixPCIE_TX_CREDITS_STATUS0x10010036
#define ixPCIE_TX_CREDITS_FCU_THRESHOLD                                         0x10010037
## mmBIF_RFE_WARMRST_CNTL0x1459
#define ixPCIE_FC_P# mmBIF_RFE_SOFTRST_CNTL                                                  
#defineixPCIE_FC_NP0x10010061
#define ixPCIE_FC_CPL                                                           0x10010062
#define ixPCIE_ERR_CNTL                                                         0x1001006a
#define ixPCIE_RX_CNTL                                                          0x10010070
#define ixPCIE_RX_EXPECTED_SEQNUM                                               0x10010071
#define ixPCIE_RX_VENDOR_SPECIFIC0x10010072
#define ixPCIE_RX_CNTL3                                                         0x10010074
#define ixPCIE_RX_CREDITS_ALLOCATED_P                                           define                                              
#define ixPCIE_RX_CREDITS_ALLOCATED_NP                                                     
#define ixPCIE_RX_CREDITS_ALLOCATED_CPL                                         0x10010082
#define ixPCIE_LC_CNTL                                                          0x100100a0
define                                                         
#define ixPCIE_LC_CNTL3                                                         0x100100b5
#define ixPCIE_LC_CNTL4                                                         0x100100b6
define                                                         
#define ixPCIE_LC_BW_CHANGE_CNTL                                                0x100100b2
#define ixPCIE_LC_TRAINING_CNTL                                                 0x100100a1
#define ixPCIE_LC_LINK_WIDTH_CNTLdefineixBIF_MEM_PG_CNTL_IND0x130148a
define                                                    
#define ixPCIE_LC_SPEED_CNTL                                                    0x100100a4
#define ixPCIE_LC_CDR_CNTL                                                      0x100100b3
define                                                     
                                                   
#define ixPCIE_LC_BEST_EQ_SETTINGS                                                                                            
#define ixPCIE_LC_FORCE_EQ_REQ_COEFF#definemmBIF_PIF_TXCLK_SWITCH_TIMER0x1481
                                                         
# ixPCIE_LC_STATE1                                                        
#define ixPCIE_LC_STATE2                                                        0x100100a7
#define ixPCIE_LC_STATE3                                                        define0x39
#define # ixD2F1_PCIE_PORT_INDEX0x2000038
#define ixPCIE_LC_STATE5                                                        0x100100aa
#define ixPCIEP_STRAP_LC                                                        0x100100c0
# ixPCIEP_STRAP_MISC0x100100c1
#define ixPCIEP_BCH_ECC_CNTL                                                    0java.lang.StringIndexOutOfBoundsException: Index 87 out of bounds for length 84
#define mmBIF_RFE_SNOOP_REG                                                     0x27
#define mmBIF_RFE_WARMRST_CNTL                                                  0x1459
#define mmBIF_RFE_SOFTRST_CNTL                                                  0x1441
#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER                                        0x1442
#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER                                        0x1443
#define mmBIF_PWDN_COMMAND                                                      0x1444
#define mmBIF_PWDN_STATUS                                                       0x1445                                         
#define mmBIF_RFE_MST_FBU_CMDSTATUS                                             0x1446
define                                  x1447
                                               
#define mmBIF_RFE_MST_TMOUT_STATUS                                              0x144b
#define mmBIF_RFE_MMCFG_CNTL                                                    0x144c
#define ixBIF_CLOCKS_BITS_IND                                                                                             
#define ixBIF_LNCNT_RESET_IND                                                   0x1301488
#defineixLNCNT_CONTROL_IND0x1301487
#define ixNEW_REFCLKB_TIMER_IND                                                 0x1301485
define                                               
#define ixBIF_CLK_PDWN_DELAY_TIMER_IND                                          0x1301483
#define ixBIF_RESET_EN_IND                                                      0x1301482
#define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND                                        0x1301481
#define ixBIF_BACO_MSIC_IND                                                     0x1301480
#define ixBIF_RESET_CNTL_IND                                                    0x1301486
#define ixBIF_RFE_CNTL_MISC_IND                                                    
#define ixBIF_MEM_PG_CNTL_IND 0xb7
#define mmNB_GBIF_INDEX                                                         0x34
#define mmNB_GBIF_DATA                                                          ixD2F1_PCIE_LC_BW_CHANGE_CNTLxb2
define                                                       
# mmBIF_LNCNT_RESET0x1488
#define mmLNCNT_CONTROL                                                         0x1487
#define mmNEW_REFCLKB_TIMER                                                     xb4
#define mmNEW_REFCLKB_TIMER_1                                                   0x1484
#define mmBIF_CLK_PDWN_DELAY_TIMERixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF0xba
#definedefine0xa5
#define mmBIF_PIF_TXCLK_SWITCH_TIMER                                            0x1481
#define mmBIF_BACO_MSIC0x1480
#define mmBIF_RESET_CNTL                                                        0x1486
#define mmBIF_RFE_CNTL_MISC                                                     0x148c
#define mmBIF_MEM_PG_CNTL                                                       0x148a
#define mmC_PCIE_P_INDEX                                                        0x38
#define mmC_PCIE_P_DATA                                                         0x39
#define ixD2F1_PCIE_PORT_INDEX                                                  0x2000038
#define ixD2F1_PCIE_PORT_DATA                                                   0x2000039
#define ixD2F1_PCIEP_RESERVED                                                   0x0
#define ixD2F1_PCIEP_SCRATCH                                                    0x1
#define ixD2F1_PCIEP_HW_DEBUG                                                   0x2
#define ixD2F1_PCIEP_PORT_CNTL                                                  0x10
#define ixD2F1_PCIE_TX_CNTL                                                     0x20
#define ixD2F1_PCIE_TX_REQUESTER_ID                                             0x21
#define ixD2F1_PCIE_TX_VENDOR_SPECIFIC                                          0x22
#define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL                                         0x23
#define ixD2F1_PCIE_TX_SEQ                                                      0x24
#define ixD2F1_PCIE_TX_REPLAY                                                   0x25
#define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT                                        0x26
#define ixD2F1_PCIE_TX_CREDITS_ADVT_P                                           0x30
#define ixD2F1_PCIE_TX_CREDITS_ADVT_NP                                          0x31
#define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL                                         0x32
#define ixD2F1_PCIE_TX_CREDITS_INIT_P                                           0x33
#define ixD2F1_PCIE_TX_CREDITS_INIT_NP                                          0x34
#define ixD2F1_PCIE_TX_CREDITS_INIT_CPL                                         0x35
#define ixD2F1_PCIE_TX_CREDITS_STATUS                                           0x36
#define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD                                    0x37
#define ixD2F1_PCIE_P_PORT_LANE_STATUS                                          0x50
#define ixD2F1_PCIE_FC_P                                                        0x60
#define ixD2F1_PCIE_FC_NP                                                       0x61
#define ixD2F1_PCIE_FC_CPL                                                      0x62
#define ixD2F1_PCIE_ERR_CNTL                                                    0x6a
#define ixD2F1_PCIE_RX_CNTL                                                     0x70
#define ixD2F1_PCIE_RX_EXPECTED_SEQNUM                                          0x71
#define ixD2F1_PCIE_RX_VENDOR_SPECIFIC                                          0x72
#define ixD2F1_PCIE_RX_CNTL3                                                    0x74
#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P                                      0x80
#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP                                     0x81
#define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL                                    0x82
#define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL                                      0x83
#define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION                                   0x84
#define ixD2F1_PCIE_LC_CNTL                                                     0xa0
#define ixD2F1_PCIE_LC_CNTL2                                                    0xb1
#define ixD2F1_PCIE_LC_CNTL3                                                    0xb5
#define ixD2F1_PCIE_LC_CNTL4                                                    0xb6
#define ixD2F1_PCIE_LC_CNTL5                                                    0xb7
#define ixD2F1_PCIE_LC_CNTL6                                                    0xbb
#define ixD2F1_PCIE_LC_BW_CHANGE_CNTL                                           0xb2
#define ixD2F1_PCIE_LC_TRAINING_CNTL                                            0xa1
#define ixD2F1_PCIE_LC_LINK_WIDTH_CNTL                                          0xa2
#define ixD2F1_PCIE_LC_N_FTS_CNTL                                               0xa3
#define ixD2F1_PCIE_LC_SPEED_CNTL                                               0xa4
#define ixD2F1_PCIE_LC_CDR_CNTL                                                 0xb3
#define ixD2F1_PCIE_LC_LANE_CNTL                                                0xb4
#define ixD2F1_PCIE_LC_FORCE_COEFF                                              0xb8
#define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS                                         0xb9
#define ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF                                       0xba
#define ixD2F1_PCIE_LC_STATE0                                                   0xa5
#define ixD2F1_PCIE_LC_STATE1                                                   0xa6
#define ixD2F1_PCIE_LC_STATE2                                                   0xa7
#define ixD2F1_PCIE_LC_STATE3                                                   0xa8
#define ixD2F1_PCIE_LC_STATE4                                                   0xa9
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