Quelle  dce_11_0_enum.h   Sprache: C

/*
 * DCE_11_0 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef DCE_11_0_ENUM_H
#define DCE_11_0_ENUM_H

typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
 CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL        = 0x0,
 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP            = 0x1,
} CRTC_CONTROL_CRTC_START_POINT_CNTL;
typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL       = 0x0,
 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP           = 0x1,
} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE     = 0x0,
 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED    = 0x2,
 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE    = 0x0,
 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE     = 0x1,
} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
 CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE              = 0x0,
 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE               = 0x1,
} CRTC_CONTROL_CRTC_SOF_PULL_EN;
typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE       = 0x0,
 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE        = 0x1,
} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x0,
 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE   = 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x0,
 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE   = 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
 CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
 CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
 CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE       = 0x0,
 CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE        = 0x1,
} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE     = 0x0,
 CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE      = 0x1,
} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x7,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x8,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x9,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0xa,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1    = 0xb,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2    = 0xc,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO   = 0xf,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0   = 0x10,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1   = 0x11,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2   = 0x12,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON   = 0x13,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE           = 0x0,
 CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE            = 0x1,
} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x7,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x8,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x9,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0xa,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1    = 0xb,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2    = 0xc,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO   = 0xf,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0   = 0x10,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1   = 0x11,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2   = 0x12,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON   = 0x13,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE           = 0x0,
 CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE            = 0x1,
} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
 CRTC_CONTROL_CRTC_MASTER_EN_FALSE                = 0x0,
 CRTC_CONTROL_CRTC_MASTER_EN_TRUE                 = 0x1,
} CRTC_CONTROL_CRTC_MASTER_EN;
typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE      = 0x0,
 CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE       = 0x1,
} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE      = 0x0,
 CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE       = 0x1,
} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
 CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x0,
 CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE   = 0x1,
} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
 CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
 CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
 CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
 CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE         = 0x0,
 CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE          = 0x1,
} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE   = 0x0,
 CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE    = 0x1,
} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
 CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
 CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
 CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE   = 0x0,
 CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE    = 0x1,
} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE   = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE   = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
 CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE          = 0x0,
 CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE           = 0x1,
} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
 CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
 CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
 CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE      = 0x0,
 MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE       = 0x1,
} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
 MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE   = 0x0,
 MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE    = 0x1,
} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN    = 0x0,
 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA     = 0x1,
 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA     = 0x2,
 MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE     = 0x3,
} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
 MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
 CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE        = 0x0,
 CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE         = 0x1,
} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
 CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
 CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
 CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
 CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE                  = 0x0,
 CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE                   = 0x1,
} CRTC_CRC_CNTL_CRTC_CRC_EN;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE             = 0x0,
 CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE              = 0x1,
} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT          = 0x0,
 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT         = 0x1,
 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES     = 0x2,
 CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS   = 0x3,
} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP        = 0x0,
 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM     = 0x1,
 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
 CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
 CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB          = 0x0,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B         = 0x1,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB         = 0x2,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B        = 0x3,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB          = 0x4,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B         = 0x5,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB         = 0x6,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B        = 0x7,
} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB          = 0x0,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B         = 0x1,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB         = 0x2,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B        = 0x3,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB          = 0x4,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B         = 0x5,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB         = 0x6,
 CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B        = 0x7,
} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
 CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
 CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
typedef enum CRTC_V_SYNC_A_POL {
 CRTC_V_SYNC_A_POL_HIGH                           = 0x0,
 CRTC_V_SYNC_A_POL_LOW                            = 0x1,
} CRTC_V_SYNC_A_POL;
typedef enum CRTC_H_SYNC_A_POL {
 CRTC_H_SYNC_A_POL_HIGH                           = 0x0,
 CRTC_H_SYNC_A_POL_LOW                            = 0x1,
} CRTC_H_SYNC_A_POL;
typedef enum CRTC_HORZ_REPETITION_COUNT {
 CRTC_HORZ_REPETITION_COUNT_0                     = 0x0,
 CRTC_HORZ_REPETITION_COUNT_1                     = 0x1,
 CRTC_HORZ_REPETITION_COUNT_2                     = 0x2,
 CRTC_HORZ_REPETITION_COUNT_3                     = 0x3,
 CRTC_HORZ_REPETITION_COUNT_4                     = 0x4,
 CRTC_HORZ_REPETITION_COUNT_5                     = 0x5,
 CRTC_HORZ_REPETITION_COUNT_6                     = 0x6,
 CRTC_HORZ_REPETITION_COUNT_7                     = 0x7,
 CRTC_HORZ_REPETITION_COUNT_8                     = 0x8,
 CRTC_HORZ_REPETITION_COUNT_9                     = 0x9,
 CRTC_HORZ_REPETITION_COUNT_10                    = 0xa,
 CRTC_HORZ_REPETITION_COUNT_11                    = 0xb,
 CRTC_HORZ_REPETITION_COUNT_12                    = 0xc,
 CRTC_HORZ_REPETITION_COUNT_13                    = 0xd,
 CRTC_HORZ_REPETITION_COUNT_14                    = 0xe,
 CRTC_HORZ_REPETITION_COUNT_15                    = 0xf,
} CRTC_HORZ_REPETITION_COUNT;
typedef enum PERFCOUNTER_CVALUE_SEL {
 PERFCOUNTER_CVALUE_SEL_47_0                      = 0x0,
 PERFCOUNTER_CVALUE_SEL_15_0                      = 0x1,
 PERFCOUNTER_CVALUE_SEL_31_16                     = 0x2,
 PERFCOUNTER_CVALUE_SEL_47_32                     = 0x3,
 PERFCOUNTER_CVALUE_SEL_11_0                      = 0x4,
 PERFCOUNTER_CVALUE_SEL_23_12                     = 0x5,
 PERFCOUNTER_CVALUE_SEL_35_24                     = 0x6,
 PERFCOUNTER_CVALUE_SEL_47_36                     = 0x7,
} PERFCOUNTER_CVALUE_SEL;
typedef enum PERFCOUNTER_INC_MODE {
 PERFCOUNTER_INC_MODE_MULTI_BIT                   = 0x0,
 PERFCOUNTER_INC_MODE_BOTH_EDGE                   = 0x1,
 PERFCOUNTER_INC_MODE_LSB                         = 0x2,
 PERFCOUNTER_INC_MODE_POS_EDGE                    = 0x3,
} PERFCOUNTER_INC_MODE;
typedef enum PERFCOUNTER_HW_CNTL_SEL {
 PERFCOUNTER_HW_CNTL_SEL_RUNEN                    = 0x0,
 PERFCOUNTER_HW_CNTL_SEL_CNTOFF                   = 0x1,
} PERFCOUNTER_HW_CNTL_SEL;
typedef enum PERFCOUNTER_RUNEN_MODE {
 PERFCOUNTER_RUNEN_MODE_LEVEL                     = 0x0,
 PERFCOUNTER_RUNEN_MODE_EDGE                      = 0x1,
} PERFCOUNTER_RUNEN_MODE;
typedef enum PERFCOUNTER_CNTOFF_START_DIS {
 PERFCOUNTER_CNTOFF_START_ENABLE                  = 0x0,
 PERFCOUNTER_CNTOFF_START_DISABLE                 = 0x1,
} PERFCOUNTER_CNTOFF_START_DIS;
typedef enum PERFCOUNTER_RESTART_EN {
 PERFCOUNTER_RESTART_DISABLE                      = 0x0,
 PERFCOUNTER_RESTART_ENABLE                       = 0x1,
} PERFCOUNTER_RESTART_EN;
typedef enum PERFCOUNTER_INT_EN {
 PERFCOUNTER_INT_DISABLE                          = 0x0,
 PERFCOUNTER_INT_ENABLE                           = 0x1,
} PERFCOUNTER_INT_EN;
typedef enum PERFCOUNTER_OFF_MASK {
 PERFCOUNTER_OFF_MASK_DISABLE                     = 0x0,
 PERFCOUNTER_OFF_MASK_ENABLE                      = 0x1,
} PERFCOUNTER_OFF_MASK;
typedef enum PERFCOUNTER_ACTIVE {
 PERFCOUNTER_IS_IDLE                              = 0x0,
 PERFCOUNTER_IS_ACTIVE                            = 0x1,
} PERFCOUNTER_ACTIVE;
typedef enum PERFCOUNTER_INT_TYPE {
 PERFCOUNTER_INT_TYPE_LEVEL                       = 0x0,
 PERFCOUNTER_INT_TYPE_PULSE                       = 0x1,
} PERFCOUNTER_INT_TYPE;
typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
 PERFCOUNTER_COUNTED_VALUE_TYPE_ACC               = 0x0,
 PERFCOUNTER_COUNTED_VALUE_TYPE_MAX               = 0x1,
} PERFCOUNTER_COUNTED_VALUE_TYPE;
typedef enum PERFCOUNTER_CNTL_SEL {
 PERFCOUNTER_CNTL_SEL_0                           = 0x0,
 PERFCOUNTER_CNTL_SEL_1                           = 0x1,
 PERFCOUNTER_CNTL_SEL_2                           = 0x2,
 PERFCOUNTER_CNTL_SEL_3                           = 0x3,
 PERFCOUNTER_CNTL_SEL_4                           = 0x4,
 PERFCOUNTER_CNTL_SEL_5                           = 0x5,
 PERFCOUNTER_CNTL_SEL_6                           = 0x6,
 PERFCOUNTER_CNTL_SEL_7                           = 0x7,
} PERFCOUNTER_CNTL_SEL;
typedef enum PERFCOUNTER_CNT0_STATE {
 PERFCOUNTER_CNT0_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT0_STATE_START                     = 0x1,
 PERFCOUNTER_CNT0_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT0_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT0_STATE;
typedef enum PERFCOUNTER_STATE_SEL0 {
 PERFCOUNTER_STATE_SEL0_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL0_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL0;
typedef enum PERFCOUNTER_CNT1_STATE {
 PERFCOUNTER_CNT1_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT1_STATE_START                     = 0x1,
 PERFCOUNTER_CNT1_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT1_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT1_STATE;
typedef enum PERFCOUNTER_STATE_SEL1 {
 PERFCOUNTER_STATE_SEL1_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL1_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL1;
typedef enum PERFCOUNTER_CNT2_STATE {
 PERFCOUNTER_CNT2_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT2_STATE_START                     = 0x1,
 PERFCOUNTER_CNT2_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT2_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT2_STATE;
typedef enum PERFCOUNTER_STATE_SEL2 {
 PERFCOUNTER_STATE_SEL2_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL2_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL2;
typedef enum PERFCOUNTER_CNT3_STATE {
 PERFCOUNTER_CNT3_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT3_STATE_START                     = 0x1,
 PERFCOUNTER_CNT3_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT3_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT3_STATE;
typedef enum PERFCOUNTER_STATE_SEL3 {
 PERFCOUNTER_STATE_SEL3_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL3_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL3;
typedef enum PERFCOUNTER_CNT4_STATE {
 PERFCOUNTER_CNT4_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT4_STATE_START                     = 0x1,
 PERFCOUNTER_CNT4_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT4_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT4_STATE;
typedef enum PERFCOUNTER_STATE_SEL4 {
 PERFCOUNTER_STATE_SEL4_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL4_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL4;
typedef enum PERFCOUNTER_CNT5_STATE {
 PERFCOUNTER_CNT5_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT5_STATE_START                     = 0x1,
 PERFCOUNTER_CNT5_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT5_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT5_STATE;
typedef enum PERFCOUNTER_STATE_SEL5 {
 PERFCOUNTER_STATE_SEL5_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL5_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL5;
typedef enum PERFCOUNTER_CNT6_STATE {
 PERFCOUNTER_CNT6_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT6_STATE_START                     = 0x1,
 PERFCOUNTER_CNT6_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT6_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT6_STATE;
typedef enum PERFCOUNTER_STATE_SEL6 {
 PERFCOUNTER_STATE_SEL6_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL6_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL6;
typedef enum PERFCOUNTER_CNT7_STATE {
 PERFCOUNTER_CNT7_STATE_RESET                     = 0x0,
 PERFCOUNTER_CNT7_STATE_START                     = 0x1,
 PERFCOUNTER_CNT7_STATE_FREEZE                    = 0x2,
 PERFCOUNTER_CNT7_STATE_HW                        = 0x3,
} PERFCOUNTER_CNT7_STATE;
typedef enum PERFCOUNTER_STATE_SEL7 {
 PERFCOUNTER_STATE_SEL7_GLOBAL                    = 0x0,
 PERFCOUNTER_STATE_SEL7_LOCAL                     = 0x1,
} PERFCOUNTER_STATE_SEL7;
typedef enum PERFMON_STATE {
 PERFMON_STATE_RESET                              = 0x0,
 PERFMON_STATE_START                              = 0x1,
 PERFMON_STATE_FREEZE                             = 0x2,
 PERFMON_STATE_HW                                 = 0x3,
} PERFMON_STATE;
typedef enum PERFMON_CNTOFF_AND_OR {
 PERFMON_CNTOFF_OR                                = 0x0,
 PERFMON_CNTOFF_AND                               = 0x1,
} PERFMON_CNTOFF_AND_OR;
typedef enum PERFMON_CNTOFF_INT_EN {
 PERFMON_CNTOFF_INT_DISABLE                       = 0x0,
 PERFMON_CNTOFF_INT_ENABLE                        = 0x1,
} PERFMON_CNTOFF_INT_EN;
typedef enum PERFMON_CNTOFF_INT_TYPE {
 PERFMON_CNTOFF_INT_TYPE_LEVEL                    = 0x0,
 PERFMON_CNTOFF_INT_TYPE_PULSE                    = 0x1,
} PERFMON_CNTOFF_INT_TYPE;
typedef enum LptNumBanks {
 LPT_NUM_BANKS_2BANK                              = 0x0,
 LPT_NUM_BANKS_4BANK                              = 0x1,
 LPT_NUM_BANKS_8BANK                              = 0x2,
 LPT_NUM_BANKS_16BANK                             = 0x3,
 LPT_NUM_BANKS_32BANK                             = 0x4,
} LptNumBanks;
typedef enum DCIO_DC_GENERICA_SEL {
 DCIO_GENERICA_SEL_DACA_STEREOSYNC                = 0x0,
 DCIO_GENERICA_SEL_STEREOSYNC                     = 0x1,
 DCIO_GENERICA_SEL_DACA_PIXCLK                    = 0x2,
 DCIO_GENERICA_SEL_DACB_PIXCLK                    = 0x3,
 DCIO_GENERICA_SEL_DVOA_CTL3                      = 0x4,
 DCIO_GENERICA_SEL_P1_PLLCLK                      = 0x5,
 DCIO_GENERICA_SEL_P2_PLLCLK                      = 0x6,
 DCIO_GENERICA_SEL_DVOA_STEREOSYNC                = 0x7,
 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER              = 0x8,
 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER              = 0x9,
 DCIO_GENERICA_SEL_GENERICA_DCCG                  = 0xa,
 DCIO_GENERICA_SEL_SYNCEN                         = 0xb,
 DCIO_GENERICA_SEL_GENERICA_SCG                   = 0xc,
 DCIO_GENERICA_SEL_RESERVED_VALUE13               = 0xd,
 DCIO_GENERICA_SEL_RESERVED_VALUE14               = 0xe,
 DCIO_GENERICA_SEL_RESERVED_VALUE15               = 0xf,
 DCIO_GENERICA_SEL_GENERICA_DPRX                  = 0x10,
 DCIO_GENERICA_SEL_GENERICB_DPRX                  = 0x11,
} DCIO_DC_GENERICA_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
 DCIO_UNIPHYA_TEST_REFDIV_CLK                     = 0x0,
 DCIO_UNIPHYB_TEST_REFDIV_CLK                     = 0x1,
 DCIO_UNIPHYC_TEST_REFDIV_CLK                     = 0x2,
 DCIO_UNIPHYD_TEST_REFDIV_CLK                     = 0x3,
 DCIO_UNIPHYE_TEST_REFDIV_CLK                     = 0x4,
 DCIO_UNIPHYF_TEST_REFDIV_CLK                     = 0x5,
 DCIO_UNIPHYG_TEST_REFDIV_CLK                     = 0x6,
 DCIO_UNIPHYLPA_TEST_REFDIV_CLK                   = 0x7,
 DCIO_UNIPHYLPB_TEST_REFDIV_CLK                   = 0x8,
} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
 DCIO_UNIPHYA_FBDIV_CLK                           = 0x0,
 DCIO_UNIPHYB_FBDIV_CLK                           = 0x1,
 DCIO_UNIPHYC_FBDIV_CLK                           = 0x2,
 DCIO_UNIPHYD_FBDIV_CLK                           = 0x3,
 DCIO_UNIPHYE_FBDIV_CLK                           = 0x4,
 DCIO_UNIPHYF_FBDIV_CLK                           = 0x5,
 DCIO_UNIPHYG_FBDIV_CLK                           = 0x6,
 DCIO_UNIPHYLPA_FBDIV_CLK                         = 0x7,
 DCIO_UNIPHYLPB_FBDIV_CLK                         = 0x8,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
 DCIO_UNIPHYA_FBDIV_SSC_CLK                       = 0x0,
 DCIO_UNIPHYB_FBDIV_SSC_CLK                       = 0x1,
 DCIO_UNIPHYC_FBDIV_SSC_CLK                       = 0x2,
 DCIO_UNIPHYD_FBDIV_SSC_CLK                       = 0x3,
 DCIO_UNIPHYE_FBDIV_SSC_CLK                       = 0x4,
 DCIO_UNIPHYF_FBDIV_SSC_CLK                       = 0x5,
 DCIO_UNIPHYG_FBDIV_SSC_CLK                       = 0x6,
 DCIO_UNIPHYLPA_FBDIV_SSC_CLK                     = 0x7,
 DCIO_UNIPHYLPB_FBDIV_SSC_CLK                     = 0x8,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2                 = 0x0,
 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2                 = 0x1,
 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2                 = 0x2,
 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2                 = 0x3,
 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2                 = 0x4,
 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2                 = 0x5,
 DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2                 = 0x6,
 DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2               = 0x7,
 DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2               = 0x8,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
typedef enum DCIO_DC_GENERICB_SEL {
 DCIO_GENERICB_SEL_DACA_STEREOSYNC                = 0x0,
 DCIO_GENERICB_SEL_STEREOSYNC                     = 0x1,
 DCIO_GENERICB_SEL_DACA_PIXCLK                    = 0x2,
 DCIO_GENERICB_SEL_DACB_PIXCLK                    = 0x3,
 DCIO_GENERICB_SEL_DVOA_CTL3                      = 0x4,
 DCIO_GENERICB_SEL_P1_PLLCLK                      = 0x5,
 DCIO_GENERICB_SEL_P2_PLLCLK                      = 0x6,
 DCIO_GENERICB_SEL_DVOA_STEREOSYNC                = 0x7,
 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER              = 0x8,
 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER              = 0x9,
 DCIO_GENERICB_SEL_GENERICB_DCCG                  = 0xa,
 DCIO_GENERICB_SEL_SYNCEN                         = 0xb,
 DCIO_GENERICB_SEL_GENERICA_SCG                   = 0xc,
 DCIO_GENERICB_SEL_RESERVED_VALUE13               = 0xd,
 DCIO_GENERICB_SEL_RESERVED_VALUE14               = 0xe,
 DCIO_GENERICB_SEL_RESERVED_VALUE15               = 0xf,
} DCIO_DC_GENERICB_SEL;
typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
 DCIO_DC_PAD_EXTERN_SIG_SEL_MVP                   = 0x0,
 DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA                = 0x1,
 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK             = 0x2,
 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC           = 0x3,
 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA              = 0x4,
 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB              = 0x5,
 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC              = 0x6,
 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1                  = 0x7,
 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2                  = 0x8,
 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK               = 0x9,
 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA              = 0xa,
 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK               = 0xb,
 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA              = 0xc,
 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1                 = 0xd,
 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0                 = 0xe,
 DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL                = 0xf,
} DCIO_DC_PAD_EXTERN_SIG_SEL;
typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA                 = 0x0,
 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE       = 0x1,
 DCIO_MVP_PIXEL_SRC_STATUS_CRTC                   = 0x2,
 DCIO_MVP_PIXEL_SRC_STATUS_LB                     = 0x3,
} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
 DCIO_HSYNCA_OUTPUT_SEL_DISABLE                   = 0x0,
 DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
 DCIO_HSYNCA_OUTPUT_SEL_PPLL2                     = 0x2,
 DCIO_HSYNCA_OUTPUT_SEL_RESERVED                  = 0x3,
} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE                = 0x0,
 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1                  = 0x1,
 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3        = 0x3,
} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
typedef enum DCIO_DC_GPIO_VIP_DEBUG {
 DCIO_DC_GPIO_VIP_DEBUG_NORMAL                    = 0x0,
 DCIO_DC_GPIO_VIP_DEBUG_CG_BIG                    = 0x1,
} DCIO_DC_GPIO_VIP_DEBUG;
typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
 DCIO_DC_GPIO_MACRO_DEBUG_NORMAL                  = 0x0,
 DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF                = 0x1,
 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2         = 0x2,
 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3         = 0x3,
} DCIO_DC_GPIO_MACRO_DEBUG;
typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL       = 0x0,
 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP         = 0x1,
} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS            = 0x0,
 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE            = 0x1,
} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
 DCIO_DPRX_LOOPBACK_ENABLE_NORMAL                 = 0x0,
 DCIO_DPRX_LOOPBACK_ENABLE_LOOP                   = 0x1,
} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
 DCIO_UNIPHY_CHANNEL_NO_INVERSION                 = 0x0,
 DCIO_UNIPHY_CHANNEL_INVERTED                     = 0x1,
} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW        = 0x0,
 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW           = 0x1,
 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0              = 0x0,
 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1              = 0x1,
 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2              = 0x2,
 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3              = 0x3,
} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
 DCIO_VIP_MUX_EN_DVO                              = 0x0,
 DCIO_VIP_MUX_EN_VIP                              = 0x1,
} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
 DCIO_VIP_ALTER_MAPPING_EN_DEFAULT                = 0x0,
 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
 DCIO_DVO_ALTER_MAPPING_EN_DEFAULT                = 0x0,
 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF           = 0x0,
 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON            = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
 DCIO_LVTMA_SYNCEN_POL_NON_INVERT                 = 0x0,
 DCIO_LVTMA_SYNCEN_POL_INVERT                     = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
 DCIO_LVTMA_DIGON_OFF                             = 0x0,
 DCIO_LVTMA_DIGON_ON                              = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
 DCIO_LVTMA_DIGON_POL_NON_INVERT                  = 0x0,
 DCIO_LVTMA_DIGON_POL_INVERT                      = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
 DCIO_LVTMA_BLON_OFF                              = 0x0,
 DCIO_LVTMA_BLON_ON                               = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
 DCIO_LVTMA_BLON_POL_NON_INVERT                   = 0x0,
 DCIO_LVTMA_BLON_POL_INVERT                       = 0x1,
} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON              = 0x0,
 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE          = 0x1,
} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
 DCIO_BL_PWM_FRACTIONAL_DISABLE                   = 0x0,
 DCIO_BL_PWM_FRACTIONAL_ENABLE                    = 0x1,
} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
 DCIO_BL_PWM_DISABLE                              = 0x0,
 DCIO_BL_PWM_ENABLE                               = 0x1,
} DCIO_BL_PWM_CNTL_BL_PWM_EN;
typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL       = 0x0,
 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1       = 0x1,
 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2       = 0x2,
 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3       = 0x3,
} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
 DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE              = 0x0,
 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE               = 0x1,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL      = 0x0,
 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM         = 0x1,
} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
 DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE                = 0x0,
 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE                 = 0x1,
} DCIO_BL_PWM_GRP1_REG_LOCK;
typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE   = 0x0,
 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE    = 0x1,
} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE       = 0x0,
 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE      = 0x1,
} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
typedef enum DCIO_GSL_SEL {
 DCIO_GSL_SEL_GROUP_0                             = 0x0,
 DCIO_GSL_SEL_GROUP_1                             = 0x1,
 DCIO_GSL_SEL_GROUP_2                             = 0x2,
} DCIO_GSL_SEL;
typedef enum DCIO_GENLK_CLK_GSL_MASK {
 DCIO_GENLK_CLK_GSL_MASK_NO                       = 0x0,
 DCIO_GENLK_CLK_GSL_MASK_TIMING                   = 0x1,
 DCIO_GENLK_CLK_GSL_MASK_STEREO                   = 0x2,
} DCIO_GENLK_CLK_GSL_MASK;
typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
 DCIO_GENLK_VSYNC_GSL_MASK_NO                     = 0x0,
 DCIO_GENLK_VSYNC_GSL_MASK_TIMING                 = 0x1,
 DCIO_GENLK_VSYNC_GSL_MASK_STEREO                 = 0x2,
} DCIO_GENLK_VSYNC_GSL_MASK;
typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
 DCIO_SWAPLOCK_A_GSL_MASK_NO                      = 0x0,
 DCIO_SWAPLOCK_A_GSL_MASK_TIMING                  = 0x1,
 DCIO_SWAPLOCK_A_GSL_MASK_STEREO                  = 0x2,
} DCIO_SWAPLOCK_A_GSL_MASK;
typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
 DCIO_SWAPLOCK_B_GSL_MASK_NO                      = 0x0,
 DCIO_SWAPLOCK_B_GSL_MASK_TIMING                  = 0x1,
 DCIO_SWAPLOCK_B_GSL_MASK_STEREO                  = 0x2,
} DCIO_SWAPLOCK_B_GSL_MASK;
typedef enum DCIO_GSL_VSYNC_SEL {
 DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
 DCIO_GSL_VSYNC_SEL_PIPE1                         = 0x1,
 DCIO_GSL_VSYNC_SEL_PIPE2                         = 0x2,
 DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
 DCIO_GSL_VSYNC_SEL_PIPE4                         = 0x4,
 DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
} DCIO_GSL_VSYNC_SEL;
typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
 DCIO_GSL0_TIMING_SYNC_SEL_PIPE                   = 0x0,
 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
} DCIO_GSL0_TIMING_SYNC_SEL;
typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
 DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
 DCIO_GSL1_TIMING_SYNC_SEL_PIPE                   = 0x0,
 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
} DCIO_GSL1_TIMING_SYNC_SEL;
typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
 DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
 DCIO_GSL2_TIMING_SYNC_SEL_PIPE                   = 0x0,
 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
} DCIO_GSL2_TIMING_SYNC_SEL;
typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
 DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
 DCIO_GPU_TIMER_START_0_END_27                    = 0x0,
 DCIO_GPU_TIMER_START_1_END_28                    = 0x1,
 DCIO_GPU_TIMER_START_2_END_29                    = 0x2,
 DCIO_GPU_TIMER_START_3_END_30                    = 0x3,
 DCIO_GPU_TIMER_START_4_END_31                    = 0x4,
 DCIO_GPU_TIMER_START_6_END_33                    = 0x5,
 DCIO_GPU_TIMER_START_8_END_35                    = 0x6,
 DCIO_GPU_TIMER_START_10_END_37                   = 0x7,
} DCIO_DC_GPU_TIMER_START_POSITION;
typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
 DCIO_TEST_CLK_SEL_DISPCLK                        = 0x0,
 DCIO_TEST_CLK_SEL_GATED_DISPCLK                  = 0x1,
 DCIO_TEST_CLK_SEL_SCLK                           = 0x2,
} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
 DCIO_DISPCLK_R_DCIO_GATE_DISABLE                 = 0x0,
 DCIO_DISPCLK_R_DCIO_GATE_ENABLE                  = 0x1,
} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
 DCIO_EXT_VSYNC_MUX_SWAPLOCKB                     = 0x0,
 DCIO_EXT_VSYNC_MUX_CRTC0                         = 0x1,
 DCIO_EXT_VSYNC_MUX_CRTC1                         = 0x2,
 DCIO_EXT_VSYNC_MUX_CRTC2                         = 0x3,
 DCIO_EXT_VSYNC_MUX_CRTC3                         = 0x4,
 DCIO_EXT_VSYNC_MUX_CRTC4                         = 0x5,
 DCIO_EXT_VSYNC_MUX_CRTC5                         = 0x6,
 DCIO_EXT_VSYNC_MUX_GENERICB                      = 0x7,
} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
typedef enum DCIO_DCO_EXT_VSYNC_MASK {
 DCIO_EXT_VSYNC_MASK_NONE                         = 0x0,
 DCIO_EXT_VSYNC_MASK_PIPE0                        = 0x1,
 DCIO_EXT_VSYNC_MASK_PIPE1                        = 0x2,
 DCIO_EXT_VSYNC_MASK_PIPE2                        = 0x3,
 DCIO_EXT_VSYNC_MASK_PIPE3                        = 0x4,
 DCIO_EXT_VSYNC_MASK_PIPE4                        = 0x5,
 DCIO_EXT_VSYNC_MASK_PIPE5                        = 0x6,
 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE               = 0x7,
} DCIO_DCO_EXT_VSYNC_MASK;
typedef enum DCIO_DBG_OUT_PIN_SEL {
 DCIO_DBG_OUT_PIN_SEL_LOW_12BIT                   = 0x0,
 DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT                  = 0x1,
} DCIO_DBG_OUT_PIN_SEL;
typedef enum DCIO_DBG_OUT_12BIT_SEL {
 DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT                 = 0x0,
 DCIO_DBG_OUT_12BIT_SEL_MID_12BIT                 = 0x1,
 DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT                = 0x2,
 DCIO_DBG_OUT_12BIT_SEL_OVERRIDE                  = 0x3,
} DCIO_DBG_OUT_12BIT_SEL;
typedef enum DCIO_DSYNC_SOFT_RESET {
 DCIO_DSYNC_SOFT_RESET_DEASSERT                   = 0x0,
 DCIO_DSYNC_SOFT_RESET_ASSERT                     = 0x1,
} DCIO_DSYNC_SOFT_RESET;
typedef enum DCIO_DACA_SOFT_RESET {
 DCIO_DACA_SOFT_RESET_DEASSERT                    = 0x0,
 DCIO_DACA_SOFT_RESET_ASSERT                      = 0x1,
} DCIO_DACA_SOFT_RESET;
typedef enum DCIO_DCRXPHY_SOFT_RESET {
 DCIO_DCRXPHY_SOFT_RESET_DEASSERT                 = 0x0,
 DCIO_DCRXPHY_SOFT_RESET_ASSERT                   = 0x1,
} DCIO_DCRXPHY_SOFT_RESET;
typedef enum DCIO_DPHY_LANE_SEL {
 DCIO_DPHY_LANE_SEL_LANE0                         = 0x0,
 DCIO_DPHY_LANE_SEL_LANE1                         = 0x1,
 DCIO_DPHY_LANE_SEL_LANE2                         = 0x2,
 DCIO_DPHY_LANE_SEL_LANE3                         = 0x3,
} DCIO_DPHY_LANE_SEL;
typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE     = 0x0,
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