| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/drivers/gpu/drm/amd/include/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 171 kB |
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Quelle atomfirmware.h Sprache: C |
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/****************************************************************************\ * * File Name atomfirmware.h * Project This is an interface header file between atombios and OS GPU drivers for SoC15 product * * Description header file of general definitions for OS and pre-OS video drivers * * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restri * including without limitation the rights to use, copy, modify, merge, publish, distribute, s * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to d * subject to the following conditions: * * The above copyright notice and this permission notice shall be included in all copies or subst * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * \****************************************************************************/ /*IMPORTANT NOTES * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, t * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the * If a change is needed for both pre and post SoC15 products, then the change has to be made separat */ #ifndef _ATOMFIRMWARE_H_ #define _ATOMFIRMWARE_H_ enum atom_bios_header_version_def{ ATOM_MAJOR_VERSION =0x0003, ATOM_MINOR_VERSION =0x0003, }; #ifdef _H2INC #ifndef uint32_t typedef unsigned long uint32_t; #endif #ifndef uint16_t typedef unsigned short uint16_t; #endif #ifndef uint8_t typedef unsigned char uint8_t; #endif #endif enum atom_crtc_def{ ATOM_CRTC1 =0, ATOM_CRTC2 =1, ATOM_CRTC3 =2, ATOM_CRTC4 =3, ATOM_CRTC5 =4, ATOM_CRTC6 =5, ATOM_CRTC_INVALID =0xff, }; enum atom_ppll_def{ ATOM_PPLL0 =2, ATOM_GCK_DFS =8, ATOM_FCH_CLK =9, ATOM_DP_DTO =11, ATOM_COMBOPHY_PLL0 =20, ATOM_COMBOPHY_PLL1 =21, ATOM_COMBOPHY_PLL2 =22, ATOM_COMBOPHY_PLL3 =23, ATOM_COMBOPHY_PLL4 =24, ATOM_COMBOPHY_PLL5 =25, ATOM_PPLL_INVALID =0xff, }; // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel enum atom_dig_def{ ASIC_INT_DIG1_ENCODER_ID =0x03, ASIC_INT_DIG2_ENCODER_ID =0x09, ASIC_INT_DIG3_ENCODER_ID =0x0a, ASIC_INT_DIG4_ENCODER_ID =0x0b, ASIC_INT_DIG5_ENCODER_ID =0x0c, ASIC_INT_DIG6_ENCODER_ID =0x0d, ASIC_INT_DIG7_ENCODER_ID =0x0e, }; //ucEncoderMode enum atom_encode_mode_def { ATOM_ENCODER_MODE_DP =0, ATOM_ENCODER_MODE_DP_SST =0, ATOM_ENCODER_MODE_LVDS =1, ATOM_ENCODER_MODE_DVI =2, ATOM_ENCODER_MODE_HDMI =3, ATOM_ENCODER_MODE_DP_AUDIO =5, ATOM_ENCODER_MODE_DP_MST =5, ATOM_ENCODER_MODE_CRT =15, ATOM_ENCODER_MODE_DVO =16, }; enum atom_encoder_refclk_src_def{ ENCODER_REFCLK_SRC_P1PLL =0, ENCODER_REFCLK_SRC_P2PLL =1, ENCODER_REFCLK_SRC_P3PLL =2, ENCODER_REFCLK_SRC_EXTCLK =3, ENCODER_REFCLK_SRC_INVALID =0xff, }; enum atom_scaler_def{ ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ }; enum atom_operation_def{ ATOM_DISABLE = 0, ATOM_ENABLE = 1, ATOM_INIT = 7, ATOM_GET_STATUS = 8, }; enum atom_embedded_display_op_def{ ATOM_LCD_BL_OFF = 2, ATOM_LCD_BL_OM = 3, ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, ATOM_LCD_SELFTEST_START = 5, ATOM_LCD_SELFTEST_STOP = 6, }; enum atom_spread_spectrum_mode{ ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, ATOM_SS_DOWN_SPREAD_MODE = 0x00, ATOM_SS_CENTRE_SPREAD_MODE = 0x01, ATOM_INT_OR_EXT_SS_MASK = 0x02, ATOM_INTERNAL_SS_MASK = 0x00, ATOM_EXTERNAL_SS_MASK = 0x02, }; /* define panel bit per color */ enum atom_panel_bit_per_color{ PANEL_BPC_UNDEFINE =0x00, PANEL_6BIT_PER_COLOR =0x01, PANEL_8BIT_PER_COLOR =0x02, PANEL_10BIT_PER_COLOR =0x03, PANEL_12BIT_PER_COLOR =0x04, PANEL_16BIT_PER_COLOR =0x05, }; //ucVoltageType enum atom_voltage_type { VOLTAGE_TYPE_VDDC = 1, VOLTAGE_TYPE_MVDDC = 2, VOLTAGE_TYPE_MVDDQ = 3, VOLTAGE_TYPE_VDDCI = 4, VOLTAGE_TYPE_VDDGFX = 5, VOLTAGE_TYPE_PCC = 6, VOLTAGE_TYPE_MVPP = 7, VOLTAGE_TYPE_LEDDPM = 8, VOLTAGE_TYPE_PCC_MVDD = 9, VOLTAGE_TYPE_PCIE_VDDC = 10, VOLTAGE_TYPE_PCIE_VDDR = 11, VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, }; enum atom_dgpu_vram_type { ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80, ATOM_DGPU_VRAM_TYPE_HBM3E = 0x81, }; enum atom_dp_vs_preemph_def{ DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, }; #define BIOS_ATOM_PREFIX "ATOMBIOS" #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" #define BIOS_STRING_LENGTH 43 /* enum atom_string_def{ asic_bus_type_pcie_string = "PCI_EXPRESS", atom_fire_gl_string = "FGL", atom_bios_string = "ATOM" }; */ #pragma pack(1) /* BIOS data must use byte aligment*/ enum atombios_image_offset{ OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002, OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94, MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/ OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f, OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e, OFFSET_TO_VBIOS_PART_NUMBER = 0x80, OFFSET_TO_VBIOS_DATE = 0x50, }; /**************************************************************************** * Common header for all tables (Data table, Command function). * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. * And the pointer actually points to this header. ****************************************************************************/ struct atom_common_table_header { uint16_t structuresize; uint8_t format_revision; //mainly used for a hw function, when the parser is not backward comp uint8_t content_revision; //change it when a data table has a structure change, or a hw functio }; /**************************************************************************** * Structure stores the ROM header. ****************************************************************************/ struct atom_rom_header_v2_2 { struct atom_common_table_header table_header; uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to di uint16_t bios_segment_address; uint16_t protectedmodeoffset; uint16_t configfilenameoffset; uint16_t crc_block_offset; uint16_t vbios_bootupmessageoffset; uint16_t int10_offset; uint16_t pcibusdevinitcode; uint16_t iobaseaddress; uint16_t subsystem_vendor_id; uint16_t subsystem_id; uint16_t pci_info_offset; uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don' uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change uint16_t reserved; uint32_t pspdirtableoffset; }; /*==============================hw function portion=============================== /**************************************************************************** * Structures used in Command.mtb, each function name is not given here since those function cou * The real functionality of each function is associated with the parameter structure version w * For all internal cmd function definitions, please reference to atomstruct.h ****************************************************************************/ struct atom_master_list_of_command_functions_v2_1{ uint16_t asic_init; //Function uint16_t cmd_function1; //used as an internal one uint16_t cmd_function2; //used as an internal one uint16_t cmd_function3; //used as an internal one uint16_t digxencodercontrol; //Function uint16_t cmd_function5; //used as an internal one uint16_t cmd_function6; //used as an internal one uint16_t cmd_function7; //used as an internal one uint16_t cmd_function8; //used as an internal one uint16_t cmd_function9; //used as an internal one uint16_t setengineclock; //Function uint16_t setmemoryclock; //Function uint16_t setpixelclock; //Function uint16_t enabledisppowergating; //Function uint16_t cmd_function14; //used as an internal one uint16_t cmd_function15; //used as an internal one uint16_t cmd_function16; //used as an internal one uint16_t cmd_function17; //used as an internal one uint16_t cmd_function18; //used as an internal one uint16_t cmd_function19; //used as an internal one uint16_t cmd_function20; //used as an internal one uint16_t cmd_function21; //used as an internal one uint16_t cmd_function22; //used as an internal one uint16_t cmd_function23; //used as an internal one uint16_t cmd_function24; //used as an internal one uint16_t cmd_function25; //used as an internal one uint16_t cmd_function26; //used as an internal one uint16_t cmd_function27; //used as an internal one uint16_t cmd_function28; //used as an internal one uint16_t cmd_function29; //used as an internal one uint16_t cmd_function30; //used as an internal one uint16_t cmd_function31; //used as an internal one uint16_t cmd_function32; //used as an internal one uint16_t cmd_function33; //used as an internal one uint16_t blankcrtc; //Function uint16_t enablecrtc; //Function uint16_t cmd_function36; //used as an internal one uint16_t cmd_function37; //used as an internal one uint16_t cmd_function38; //used as an internal one uint16_t cmd_function39; //used as an internal one uint16_t cmd_function40; //used as an internal one uint16_t getsmuclockinfo; //Function uint16_t selectcrtc_source; //Function uint16_t cmd_function43; //used as an internal one uint16_t cmd_function44; //used as an internal one uint16_t cmd_function45; //used as an internal one uint16_t setdceclock; //Function uint16_t getmemoryclock; //Function uint16_t getengineclock; //Function uint16_t setcrtc_usingdtdtiming; //Function uint16_t externalencodercontrol; //Function uint16_t cmd_function51; //used as an internal one uint16_t cmd_function52; //used as an internal one uint16_t cmd_function53; //used as an internal one uint16_t processi2cchanneltransaction;//Function uint16_t cmd_function55; //used as an internal one uint16_t cmd_function56; //used as an internal one uint16_t cmd_function57; //used as an internal one uint16_t cmd_function58; //used as an internal one uint16_t cmd_function59; //used as an internal one uint16_t computegpuclockparam; //Function uint16_t cmd_function61; //used as an internal one uint16_t cmd_function62; //used as an internal one uint16_t dynamicmemorysettings; //Function function uint16_t memorytraining; //Function function uint16_t cmd_function65; //used as an internal one uint16_t cmd_function66; //used as an internal one uint16_t setvoltage; //Function uint16_t cmd_function68; //used as an internal one uint16_t readefusevalue; //Function uint16_t cmd_function70; //used as an internal one uint16_t cmd_function71; //used as an internal one uint16_t cmd_function72; //used as an internal one uint16_t cmd_function73; //used as an internal one uint16_t cmd_function74; //used as an internal one uint16_t cmd_function75; //used as an internal one uint16_t dig1transmittercontrol; //Function uint16_t cmd_function77; //used as an internal one uint16_t processauxchanneltransaction;//Function uint16_t cmd_function79; //used as an internal one uint16_t getvoltageinfo; //Function }; struct atom_master_command_function_v2_1 { struct atom_common_table_header table_header; struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; }; /**************************************************************************** * Structures used in every command function ****************************************************************************/ struct atom_function_attribute { uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util }; /**************************************************************************** * Common header for all hw functions. * Every function pointed by _master_list_of_hw_function has this common header. * And the pointer actually points to this header. ****************************************************************************/ struct atom_rom_hw_function_header { struct atom_common_table_header func_header; struct atom_function_attribute func_attrib; }; /*==============================sw data table portion============================== /**************************************************************************** * Structures used in data.mtb, each data table name is not given here since those data table coul * The real name of each table is given when its data structure version is defined ****************************************************************************/ struct atom_master_list_of_data_tables_v2_1{ uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this posi uint16_t multimedia_info; uint16_t smc_dpm_info; uint16_t sw_datatable3; uint16_t firmwareinfo; /* Shared by various SW components */ uint16_t sw_datatable5; uint16_t lcd_info; /* Shared by various SW components */ uint16_t sw_datatable7; uint16_t smu_info; uint16_t sw_datatable9; uint16_t sw_datatable10; uint16_t vram_usagebyfirmware; /* Shared by various SW components */ uint16_t gpio_pin_lut; /* Shared by various SW components */ uint16_t sw_datatable13; uint16_t gfx_info; uint16_t powerplayinfo; /* Shared by various SW components */ uint16_t sw_datatable16; uint16_t sw_datatable17; uint16_t sw_datatable18; uint16_t sw_datatable19; uint16_t sw_datatable20; uint16_t sw_datatable21; uint16_t displayobjectinfo; /* Shared by various SW components */ uint16_t indirectioaccess; /* used as an internal one */ uint16_t umc_info; /* Shared by various SW components */ uint16_t sw_datatable25; uint16_t sw_datatable26; uint16_t dce_info; /* Shared by various SW components */ uint16_t vram_info; /* Shared by various SW components */ uint16_t sw_datatable29; uint16_t integratedsysteminfo; /* Shared by various SW components */ uint16_t asic_profiling_info; /* Shared by various SW components */ uint16_t voltageobject_info; /* shared by various SW components */ uint16_t sw_datatable33; uint16_t sw_datatable34; }; struct atom_master_data_table_v2_1 { struct atom_common_table_header table_header; struct atom_master_list_of_data_tables_v2_1 listOfdatatables; }; struct atom_dtd_format { uint16_t pixclk; uint16_t h_active; uint16_t h_blanking_time; uint16_t v_active; uint16_t v_blanking_time; uint16_t h_sync_offset; uint16_t h_sync_width; uint16_t v_sync_offset; uint16_t v_syncwidth; uint16_t reserved; uint16_t reserved0; uint8_t h_border; uint8_t v_border; uint16_t miscinfo; uint8_t atom_mode_id; uint8_t refreshrate; }; /* atom_dtd_format.modemiscinfo defintion */ enum atom_dtd_format_modemiscinfo{ ATOM_HSYNC_POLARITY = 0x0002, ATOM_VSYNC_POLARITY = 0x0004, ATOM_H_REPLICATIONBY2 = 0x0010, ATOM_V_REPLICATIONBY2 = 0x0020, ATOM_INTERLACE = 0x0080, ATOM_COMPOSITESYNC = 0x0040, }; /* utilitypipeline * when format_revision==1 && content_revision==1, then this an info table for atomworks to use d * the location of it can't change */ /* *************************************************************************** Data Table firmwareinfo structure *************************************************************************** */ struct atom_firmware_info_v3_1 { struct atom_common_table_header table_header; uint32_t firmware_revision; uint32_t bootup_sclk_in10khz; uint32_t bootup_mclk_in10khz; uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint16_t bootup_vddc_mv; uint16_t bootup_vddci_mv; uint16_t bootup_mvddc_mv; uint16_t bootup_vddgfx_mv; uint8_t mem_module_id; uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ uint8_t reserved1[2]; uint32_t mc_baseaddr_high; uint32_t mc_baseaddr_low; uint32_t reserved2[6]; }; /* Total 32bit cap indication */ enum atombios_firmware_capability { ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, }; enum atom_cooling_solution_id{ AIR_COOLING = 0x00, LIQUID_COOLING = 0x01 }; struct atom_firmware_info_v3_2 { struct atom_common_table_header table_header; uint32_t firmware_revision; uint32_t bootup_sclk_in10khz; uint32_t bootup_mclk_in10khz; uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint16_t bootup_vddc_mv; uint16_t bootup_vddci_mv; uint16_t bootup_mvddc_mv; uint16_t bootup_vddgfx_mv; uint8_t mem_module_id; uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ uint8_t reserved1[2]; uint32_t mc_baseaddr_high; uint32_t mc_baseaddr_low; uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id uint8_t board_i2c_feature_slave_addr; uint8_t reserved3; uint16_t bootup_mvddq_mv; uint16_t bootup_mvpp_mv; uint32_t zfbstartaddrin16mb; uint32_t reserved2[3]; }; struct atom_firmware_info_v3_3 { struct atom_common_table_header table_header; uint32_t firmware_revision; uint32_t bootup_sclk_in10khz; uint32_t bootup_mclk_in10khz; uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint16_t bootup_vddc_mv; uint16_t bootup_vddci_mv; uint16_t bootup_mvddc_mv; uint16_t bootup_vddgfx_mv; uint8_t mem_module_id; uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ uint8_t reserved1[2]; uint32_t mc_baseaddr_high; uint32_t mc_baseaddr_low; uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id uint8_t board_i2c_feature_slave_addr; uint8_t reserved3; uint16_t bootup_mvddq_mv; uint16_t bootup_mvpp_mv; uint32_t zfbstartaddrin16mb; uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside dri uint32_t reserved2[2]; }; struct atom_firmware_info_v3_4 { struct atom_common_table_header table_header; uint32_t firmware_revision; uint32_t bootup_sclk_in10khz; uint32_t bootup_mclk_in10khz; uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint16_t bootup_vddc_mv; uint16_t bootup_vddci_mv; uint16_t bootup_mvddc_mv; uint16_t bootup_vddgfx_mv; uint8_t mem_module_id; uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ uint8_t reserved1[2]; uint32_t mc_baseaddr_high; uint32_t mc_baseaddr_low; uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id uint8_t board_i2c_feature_slave_addr; uint8_t ras_rom_i2c_slave_addr; uint16_t bootup_mvddq_mv; uint16_t bootup_mvpp_mv; uint32_t zfbstartaddrin16mb; uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside dri uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. uint32_t pspbl_init_done_reg_addr; uint32_t pspbl_init_done_value; uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init don uint32_t reserved[2]; }; struct atom_firmware_info_v3_5 { struct atom_common_table_header table_header; uint32_t firmware_revision; uint32_t bootup_clk_reserved[2]; uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t fw_protect_region_size_in_kb; /* FW allocate a write protect region at top of FB. */ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint32_t bootup_voltage_reserved[2]; uint8_t mem_module_id; uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_BLT_PCI_ uint8_t reserved1; uint32_t mc_baseaddr_high; uint32_t mc_baseaddr_low; uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id uint8_t board_i2c_feature_slave_addr; uint8_t ras_rom_i2c_slave_addr; uint32_t bootup_voltage_reserved1; uint32_t zfb_reserved; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS uint32_t pplib_pptable_id; uint32_t hw_voltage_reserved[3]; uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. uint32_t pspbl_init_reserved[3]; uint32_t spi_rom_size; // GPU spi rom size uint16_t support_dev_in_objinfo; uint16_t disp_phy_tunning_size; uint32_t reserved[16]; }; /* *************************************************************************** Data Table lcd_info structure *************************************************************************** */ struct lcd_info_v2_1 { struct atom_common_table_header table_header; struct atom_dtd_format lcd_timing; uint16_t backlight_pwm; uint16_t special_handle_cap; uint16_t panel_misc; uint16_t lvds_max_slink_pclk; uint16_t lvds_ss_percentage; uint16_t lvds_ss_rate_10hz; uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ uint8_t pwr_on_de_to_vary_bl; uint8_t pwr_down_vary_bloff_to_de; uint8_t pwr_down_de_to_digoff; uint8_t pwr_off_delay; uint8_t pwr_on_vary_bl_to_blon; uint8_t pwr_down_bloff_to_vary_bloff; uint8_t panel_bpc; uint8_t dpcd_edp_config_cap; uint8_t dpcd_max_link_rate; uint8_t dpcd_max_lane_count; uint8_t dpcd_max_downspread; uint8_t min_allowed_bl_level; uint8_t max_allowed_bl_level; uint8_t bootup_bl_level; uint8_t dplvdsrxid; uint32_t reserved1[8]; }; /* lcd_info_v2_1.panel_misc defintion */ enum atom_lcd_info_panel_misc{ ATOM_PANEL_MISC_FPDI =0x0002, }; //uceDPToLVDSRxId enum atom_lcd_info_dptolvds_rx_id { eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init }; /* *************************************************************************** Data Table gpio_pin_lut structure *************************************************************************** */ struct atom_gpio_pin_assignment { uint32_t data_a_reg_index; uint8_t gpio_bitshift; uint8_t gpio_mask_bitshift; uint8_t gpio_id; uint8_t reserved; }; /* atom_gpio_pin_assignment.gpio_id definition */ enum atom_gpio_pin_assignment_gpio_id { I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, ot /* gpio_id pre-define id for multiple usage */ /* GPIO use to control PCIE_VDDC in certain SLT board */ PCIE_VDDC_CONTROL_GPIO_PINID = 56, /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ PP_AC_DC_SWITCH_GPIO_PINID = 60, /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ VDDC_VRHOT_GPIO_PINID = 61, /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ VDDC_PCC_GPIO_PINID = 62, /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ EFUSE_CUT_ENABLE_GPIO_PINID = 63, /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-r DRAM_SELF_REFRESH_GPIO_PINID = 64, /* Thermal interrupt output->system thermal chip GPIO pin */ THERMAL_INT_OUTPUT_GPIO_PINID =65, }; struct atom_gpio_pin_lut_v2_1 { struct atom_common_table_header table_header; /*the real number of this included in the structure is calcualted by using the (whole structure struct atom_gpio_pin_assignment gpio_pin[]; }; /* * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write * access that region. driver can allocate their own reservation region as long as it does not * overlap firwmare's reservation region. * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3: * in this case, atom data table vram_usagebyfirmwareTable version always <= 2.1 * if VBIOS/UEFI GOP is posted: * VBIOS/UEFIGOP update used_by_firmware_in_kb = total reserved size by VBIOS * update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; * ( total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) * driver can allocate driver reservation region under firmware reservation, * used_by_driver_in_kb = driver reservation size * driver reservation start address = (start_address_in_kb - used_by_driver_in_kb) * Comment1[hchan]: There is only one reservation at the beginning of the FB reserved by * host driver. Host driver would overwrite the table with the following * used_by_firmware_in_kb = total reserved size for pf-vf info exchange and * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0 * else there is no VBIOS reservation region: * driver must allocate driver reservation region at top of FB. * driver set used_by_driver_in_kb = driver reservation size * driver reservation start address = (total_mem_size_in_kb - used_by_driver_in_kb) * same as Comment1 * else (NV1X and after): * if VBIOS/UEFI GOP is posted: * VBIOS/UEFIGOP update: * used_by_firmware_in_kb = atom_firmware_Info_v3_3.fw_reserved_size_in_kb; * start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; * (total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) * if vram_usagebyfirmwareTable version <= 2.1: * driver can allocate driver reservation region under firmware reservation, * driver set used_by_driver_in_kb = driver reservation size * driver reservation start address = start_address_in_kb - used_by_driver_in_kb * same as Comment1 * else driver can: * allocate it reservation any place as long as it does overlap pre-OS FW reservation area * set used_by_driver_region0_in_kb = driver reservation size * set driver_region0_start_address_in_kb = driver reservation region start address * Comment2[hchan]: Host driver can set used_by_firmware_in_kb and start_address_in_kb to * zero as the reservation for VF as it doesn’t exist. And Host driver should also * update atom_firmware_Info table to remove the same VBIOS reservation as well. */ struct vram_usagebyfirmware_v2_1 { struct atom_common_table_header table_header; uint32_t start_address_in_kb; uint16_t used_by_firmware_in_kb; uint16_t used_by_driver_in_kb; }; struct vram_usagebyfirmware_v2_2 { struct atom_common_table_header table_header; uint32_t fw_region_start_address_in_kb; uint16_t used_by_firmware_in_kb; uint16_t reserved; uint32_t driver_region0_start_address_in_kb; uint32_t used_by_driver_region0_in_kb; uint32_t reserved32[7]; }; /* *************************************************************************** Data Table displayobjectinfo structure *************************************************************************** */ enum atom_object_record_type_id { ATOM_I2C_RECORD_TYPE = 1, ATOM_HPD_INT_RECORD_TYPE = 2, ATOM_CONNECTOR_CAP_RECORD_TYPE = 3, ATOM_CONNECTOR_SPEED_UPTO = 4, ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9, ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16, ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17, ATOM_ENCODER_CAP_RECORD_TYPE = 20, ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21, ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22, ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23, ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25, ATOM_RECORD_END_TYPE = 0xFF, }; struct atom_common_record_header { uint8_t record_type; //An emun to indicate the record type uint8_t record_size; //The size of the whole record in byte }; struct atom_i2c_record { struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE uint8_t i2c_id; uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector f }; struct atom_hpd_int_record { struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_T uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info uint8_t plugin_pin_state; }; struct atom_connector_caps_record { struct atom_common_record_header record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; }; struct atom_connector_speed_record { struct atom_common_record_header record_header; //record_type = ATOM_CONN_SPEED_UPTO uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP co uint16_t reserved; }; // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap enum atom_encoder_caps_def { ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired i ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be en ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by boa ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. }; struct atom_encoder_caps_record { struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECO uint32_t encodercaps; }; enum atom_connector_caps_def { ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal d }; struct atom_disp_connector_caps_record { struct atom_common_record_header record_header; uint32_t connectcaps; }; //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_C struct atom_gpio_pin_control_pair { uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table uint8_t gpio_pinstate; // Pin state showing how to set-up the pin }; struct atom_object_gpio_cntl_record { struct atom_common_record_header record_header; uint8_t flag; // Future expnadibility uint8_t number_of_pins; // Number of GPIO pins used to control the object struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of }; //Definitions for GPIO pin state enum atom_gpio_pin_control_pinstate_def { GPIO_PIN_TYPE_INPUT = 0x00, GPIO_PIN_TYPE_OUTPUT = 0x10, GPIO_PIN_TYPE_HW_CONTROL = 0x20, //For GPIO_PIN_TYPE_OUTPUT the following is defined GPIO_PIN_OUTPUT_STATE_MASK = 0x01, GPIO_PIN_OUTPUT_STATE_SHIFT = 0, GPIO_PIN_STATE_ACTIVE_LOW = 0x0, GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, }; // Indexes to GPIO array in GLSync record // GLSync record is for Frame Lock/Gen Lock feature. enum atom_glsync_record_gpio_index_def { ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, ATOM_GPIO_INDEX_GLSYNC_MAX = 9, }; struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECOR { struct atom_common_record_header record_header; uint8_t hpd_pin_map[8]; }; struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECOR { struct atom_common_record_header record_header; uint8_t aux_ddc_map[8]; }; struct atom_connector_forced_tmds_cap_record { struct atom_common_record_header record_header; // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = uint8_t maxtmdsclkrate_in2_5mhz; uint8_t reserved; }; struct atom_connector_layout_info { uint16_t connectorobjid; uint8_t connector_type; uint8_t position; }; // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector s enum atom_connector_layout_info_connector_type_def { CONNECTOR_TYPE_DVI_D = 1, CONNECTOR_TYPE_HDMI = 4, CONNECTOR_TYPE_DISPLAY_PORT = 5, CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, }; struct atom_bracket_layout_record { struct atom_common_record_header record_header; uint8_t bracketlen; uint8_t bracketwidth; uint8_t conn_num; uint8_t reserved; struct atom_connector_layout_info conn_info[1]; }; struct atom_bracket_layout_record_v2 { struct atom_common_record_header record_header; //record_type = ATOM_BRACKET_LAYOUT_RECORD_TYPE uint8_t bracketlen; //Bracket Length in mm uint8_t bracketwidth; //Bracket Width in mm uint8_t conn_num; //Connector numbering uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini) uint8_t reserved1; uint8_t reserved2; }; enum atom_connector_layout_info_mini_type_def { MINI_TYPE_NORMAL = 0, MINI_TYPE_MINI = 1, }; enum atom_display_device_tag_def{ ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal typ ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compabilit ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, }; struct atom_display_object_path_v2 { uint16_t display_objid; //Connector Object ID or Misc Object ID uint16_t disp_recordoffset; uint16_t encoderobjid; //first encoder closer to the connector, could be either an external o uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of uint16_t encoder_recordoffset; uint16_t extencoder_recordoffset; uint16_t device_tag; //a supported device vector, each display path starts with this.the pat uint8_t priority_id; uint8_t reserved; }; struct atom_display_object_path_v3 { uint16_t display_objid; //Connector Object ID or Misc Object ID uint16_t disp_recordoffset; uint16_t encoderobjid; //first encoder closer to the connector, could be either an external o uint16_t reserved1; //only on USBC case, otherwise always = 0 uint16_t reserved2; //reserved and always = 0 uint16_t reserved3; //reserved and always = 0 //a supported device vector, each display path starts with this.the paths are enumerated in th //a path appears first uint16_t device_tag; uint16_t reserved4; //reserved and always = 0 }; struct display_object_info_table_v1_4 { struct atom_common_table_header table_header; uint16_t supporteddevices; uint8_t number_of_path; uint8_t reserved; struct atom_display_object_path_v2 display_path[]; //the real number of this included in t }; struct display_object_info_table_v1_5 { struct atom_common_table_header table_header; uint16_t supporteddevices; uint8_t number_of_path; uint8_t reserved; // the real number of this included in the structure is calculated by using the // (whole structure size - the header size- number_of_path)/size of atom_display_object_pa struct atom_display_object_path_v3 display_path[]; }; /* *************************************************************************** Data Table dce_info structure *************************************************************************** */ struct atom_display_controller_info_v4_1 { struct atom_common_table_header table_header; uint32_t display_caps; uint32_t bootup_dispclk_10khz; uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; uint16_t dvi_ss_percentage; // in unit of 0.001% uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; uint16_t dp_ss_percentage; // in unit of 0.001% uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable w uint8_t reserved1[3]; uint16_t dpphy_refclk_10khz; uint16_t reserved2; uint8_t dceip_min_ver; uint8_t dceip_max_ver; uint8_t max_disp_pipe_num; uint8_t max_vbios_active_disp_pipe_num; uint8_t max_ppll_num; uint8_t max_disp_phy_num; uint8_t max_aux_pairs; uint8_t remotedisplayconfig; uint8_t reserved3[8]; }; struct atom_display_controller_info_v4_2 { struct atom_common_table_header table_header; uint32_t display_caps; uint32_t bootup_dispclk_10khz; uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; uint16_t dvi_ss_percentage; // in unit of 0.001% uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; uint16_t dp_ss_percentage; // in unit of 0.001% uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_Timing uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVES uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_Timing uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_Tim uint16_t dpphy_refclk_10khz; uint16_t reserved2; uint8_t dcnip_min_ver; uint8_t dcnip_max_ver; uint8_t max_disp_pipe_num; uint8_t max_vbios_active_disp_pipe_num; uint8_t max_ppll_num; uint8_t max_disp_phy_num; uint8_t max_aux_pairs; uint8_t remotedisplayconfig; uint8_t reserved3[8]; }; struct atom_display_controller_info_v4_3 { struct atom_common_table_header table_header; uint32_t display_caps; uint32_t bootup_dispclk_10khz; uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; uint16_t dvi_ss_percentage; // in unit of 0.001% uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; uint16_t dp_ss_percentage; // in unit of 0.001% uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_Timing uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVES uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_Timing uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_Tim uint16_t dpphy_refclk_10khz; uint16_t reserved2; uint8_t dcnip_min_ver; uint8_t dcnip_max_ver; uint8_t max_disp_pipe_num; uint8_t max_vbios_active_disp_pipe_num; uint8_t max_ppll_num; uint8_t max_disp_phy_num; uint8_t max_aux_pairs; uint8_t remotedisplayconfig; uint8_t reserved3[8]; }; struct atom_display_controller_info_v4_4 { struct atom_common_table_header table_header; uint32_t display_caps; uint32_t bootup_dispclk_10khz; uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; uint16_t dvi_ss_percentage; // in unit of 0.001% uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; uint16_t dp_ss_percentage; // in unit of 0.001% uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_Timing uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVES uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_Timing uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_Tim uint16_t dpphy_refclk_10khz; uint16_t hw_chip_id; uint8_t dcnip_min_ver; uint8_t dcnip_max_ver; uint8_t max_disp_pipe_num; uint8_t max_vbios_active_disp_pipum; uint8_t max_ppll_num; uint8_t max_disp_phy_num; uint8_t max_aux_pairs; uint8_t remotedisplayconfig; uint32_t dispclk_pll_vco_freq; uint32_t dp_ref_clk_freq; uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-s uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0. uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immedia uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx uint16_t dc_golden_table_ver; uint32_t reserved3[3]; }; struct atom_dc_golden_table_v1 { uint32_t aux_dphy_rx_control0_val; uint32_t aux_dphy_tx_control_val; uint32_t aux_dphy_rx_control1_val; uint32_t dc_gpio_aux_ctrl_0_val; uint32_t dc_gpio_aux_ctrl_1_val; uint32_t dc_gpio_aux_ctrl_2_val; uint32_t dc_gpio_aux_ctrl_3_val; uint32_t dc_gpio_aux_ctrl_4_val; uint32_t dc_gpio_aux_ctrl_5_val; uint32_t reserved[23]; }; enum dce_info_caps_def { // only for VBIOS DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02, // only for VBIOS DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04, // only for VBIOS DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08, // only for VBIOS DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20, DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, }; struct atom_display_controller_info_v4_5 { struct atom_common_table_header table_header; uint32_t display_caps; uint32_t bootup_dispclk_10khz; uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; uint16_t dvi_ss_percentage; // in unit of 0.001% uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; uint16_t dp_ss_percentage; // in unit of 0.001% uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available uint8_t dfp_hardcode_mode_num; // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not availa uint8_t dfp_hardcode_refreshrate; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable uint8_t vga_hardcode_refreshrate; uint16_t dpphy_refclk_10khz; uint16_t hw_chip_id; uint8_t dcnip_min_ver; uint8_t dcnip_max_ver; uint8_t max_disp_pipe_num; uint8_t max_vbios_active_disp_pipe_num; uint8_t max_ppll_num; uint8_t max_disp_phy_num; uint8_t max_aux_pairs; uint8_t remotedisplayconfig; uint32_t dispclk_pll_vco_freq; uint32_t dp_ref_clk_freq; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of uint32_t max_mclk_chg_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) uint32_t max_sr_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0. uint32_t max_sr_enter_exit_lat; uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx uint16_t dc_golden_table_ver; uint32_t aux_dphy_rx_control0_val; uint32_t aux_dphy_tx_control_val; uint32_t aux_dphy_rx_control1_val; uint32_t dc_gpio_aux_ctrl_0_val; uint32_t dc_gpio_aux_ctrl_1_val; uint32_t dc_gpio_aux_ctrl_2_val; uint32_t dc_gpio_aux_ctrl_3_val; uint32_t dc_gpio_aux_ctrl_4_val; uint32_t dc_gpio_aux_ctrl_5_val; uint32_t reserved[26]; }; /* *************************************************************************** Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure *************************************************************************** */ struct atom_ext_display_path { uint16_t device_tag; //A bit vector to show what devices are supported uint16_t device_acpi_enum; //16bit device ACPI id. uint16_t connectorobjid; //A physical connector for displays to plug in, using object connec uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT uint8_t hpdlut_index; //An index into external HPD pin LUT uint16_t ext_encoder_objid; //external encoder object id uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted uint16_t caps; uint16_t reserved; }; //usCaps enum ext_display_path_cap_def { EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007E, AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007E, AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = (0x01 << 1), AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x02 << 1), AMD_EXT_DISPLAY_PATH_CAPS__DP_EARLY_8B10B_TPS2 = (0x03 << 1), AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x04 << 1), AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x06 << 1), EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = (0x07 << 1), EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x08 << 1), //PI redriver chip EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x09 << 1), //TI retimer chip EXT_DISPLAY_PATH_CAPS__AMD_INTERNAL = (0x0a << 1), //AMD internal customer chip placeholder }; struct atom_external_display_connection_info { struct atom_common_table_header table_header; uint8_t guid[16]; // a GUID is a 16 byte long string struct atom_ext_display_path path[7]; // total of fixed 7 entries. uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. uint8_t stereopinid; // use for eDP panel uint8_t remotedisplayconfig; uint8_t edptolvdsrxid; uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value uint8_t reserved[3]; // for potential expansion }; /* *************************************************************************** Data Table integratedsysteminfo structure *************************************************************************** */ struct atom_camera_dphy_timing_param { uint8_t profile_id; // SENSOR_PROFILES uint32_t param; }; struct atom_camera_dphy_elec_param { uint16_t param[3]; }; struct atom_camera_module_info { uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user uint8_t module_name[8]; struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation }; struct atom_camera_flashlight_info { uint8_t flashlight_id; // 0: Rear, 1: Front uint8_t name[8]; }; struct atom_camera_data { uint32_t versionCode; struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max struct atom_camera_dphy_elec_param dphy_param; uint32_t crc_val; // CRC }; struct atom_14nm_dpphy_dvihdmi_tuningset { uint32_t max_symclk_in10khz; uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_ uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [ uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL }; struct atom_14nm_dpphy_dp_setting{ uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_ uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [ }; struct atom_14nm_dpphy_dp_tuningset{ uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t version; uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset uint16_t reserved; struct atom_14nm_dpphy_dp_setting dptuning[10]; }; struct atom_14nm_dig_transmitter_info_header_v4_0{ struct atom_common_table_header table_header; uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroS uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl }; struct atom_14nm_combphy_tmds_vs_set { uint8_t sym_clk; uint8_t dig_mode; uint8_t phy_sel; uint16_t common_mar_deemph_nom__margin_deemph_val; uint8_t common_seldeemph60__deemph_6db_4_val; uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; uint8_t margin_deemph_lane0__deemph_sel_val; }; struct atom_DCN_dpphy_dvihdmi_tuningset { uint32_t max_symclk_in10khz; uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) uint8_t reserved1; uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_ uint8_t reserved2; }; struct atom_DCN_dpphy_dp_setting{ uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_ }; struct atom_DCN_dpphy_dp_tuningset{ uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t version; uint16_t table_size; // size of atom_14nm_dpphy_dp_setting uint16_t reserved; struct atom_DCN_dpphy_dp_setting dptunings[10]; }; struct atom_i2c_reg_info { uint8_t ucI2cRegIndex; uint8_t ucI2cRegVal; }; struct atom_hdmi_retimer_redriver_set { uint8_t HdmiSlvAddr; uint8_t HdmiRegNum; uint8_t Hdmi6GRegNum; struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. }; struct atom_integrated_system_info_v1_11 { struct atom_common_table_header table_header; uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def uint32_t system_config; uint32_t cpucapinfo; uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t gpuclk_ss_type; uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t lvds_ss_rate_10hz; uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t hdmi_ss_rate_10hz; uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t dvi_ss_rate_10hz; uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def uint16_t backlight_pwm_hz; // pwm frequency in hz uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. uint8_t umachannelnumber; // number of memory channels uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ uint8_t pwr_on_de_to_vary_bl; uint8_t pwr_down_vary_bloff_to_de; uint8_t pwr_down_de_to_digoff; uint8_t pwr_off_delay; uint8_t pwr_on_vary_bl_to_blon; uint8_t pwr_down_bloff_to_vary_bloff; uint8_t min_allowed_bl_level; uint8_t htc_hyst_limit; uint8_t htc_tmp_limit; uint8_t reserved1; uint8_t reserved2; struct atom_external_display_connection_info extdispconninfo; struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set struct atom_camera_data camera_info; struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set uint32_t reserved[66]; }; struct atom_integrated_system_info_v1_12 { struct atom_common_table_header table_header; uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def uint32_t system_config; uint32_t cpucapinfo; uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t gpuclk_ss_type; uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t lvds_ss_rate_10hz; uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t hdmi_ss_rate_10hz; uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t dvi_ss_rate_10hz; uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def uint16_t backlight_pwm_hz; // pwm frequency in hz uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. uint8_t umachannelnumber; // number of memory channels uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // uint8_t pwr_on_de_to_vary_bl; uint8_t pwr_down_vary_bloff_to_de; uint8_t pwr_down_de_to_digoff; uint8_t pwr_off_delay; uint8_t pwr_on_vary_bl_to_blon; uint8_t pwr_down_bloff_to_vary_bloff; uint8_t min_allowed_bl_level; uint8_t htc_hyst_limit; uint8_t htc_tmp_limit; uint8_t reserved1; uint8_t reserved2; struct atom_external_display_connection_info extdispconninfo; --> -------------------- --> maximum size reached --> --------------------
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2026-04-04