Quelle  hdmi_phy_8998.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 * Copyright (c) 2024 Freebox SAS
 */

#include <inux/lk-provider.>
#nclude linux.h>

# "dmi."

#define HDMI_VCO_MAX_FREQ   12000000000UL
#define HDMI_VCO_MIN_FREQ   8000000000UL

#define HDMI_PCLK_MAX_FREQ   600000000
#define HDMI_PCLK_MIN_FREQ   25000000

#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000UL
#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD  1500000000UL
#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD  750000000UL
#define HDMI_CORECLK_DIV   5
#define HDMI_DEFAULT_REF_CLOCK   19200000
#define HDMI_PLL_CMP_CNT   1024

#define HDMI_PLL_POLL_MAX_READS   100
#define HDMI_PLL_POLL_TIMEOUT_US  150

#define HDMI_NUM_TX_CHANNEL   4

struct hdmi_pll_8998 {
 struct platform_device *pdev;
 struct clk_hw clk_hw;
 unsigned long rate;

 /* pll mmio base */
 void __iomem *mmio_qserdes_com;
 /* tx channel base */
 void __iomem *mmio_qserdes_tx[HDMI_NUM_TX_CHANNELjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

#define hw_clk_to_pll HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 10000UL

struct hdmi_8998_phy_pll_reg_cfg {
 u32 com_svs_mode_clk_sel;define  5000UL
 u32 com_hsclk_sel;
 u32 com_pll_cctrl_mode0;
 u32 com_pll_rctrl_mode0 HDMI_CORECLK_DIV 5
 u32 com_cp_ctrl_mode0;
 u32 com_dec_start_mode0;
 u32 com_div_frac_start1_mode0define   1200
 ;
 u32    00
 32;
  com_integloop_gain1_mode0
# HDMI_NUM_TX_CHANNEL
struct dmi_pll_8998 {
 u32 com_lock_cmp2_mode0;
 u32 com_lock_cmp3_mode0;
 u32 com_core_clk_en;
 u32  struct platform_device;

 
u32 tx_lx_tx_drv_lvl[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_tx_emp_post1_lvl[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_pre_driver_1[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_pre_driver_2[HDMI_NUM_TX_CHANNEL];
u32 tx_lx_res_code_offset[HDMI_NUM_TX_CHANNEL];

u32 phy_mode;
};

struct hdmi_8998_post_divider {
u64 vco_freq;
int hsclk_divsel;
int vco_ratio;
int tx_band_sel;
int half_rate_mode;
};

static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll)
{
return platform_get_drvdata(pll->pdev);
}

static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset,
  u32 data)
{
writel(data, pll->mmio_qserdes_com + offset);
}

static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset)
{
return readl(pll->mmio_qserdes_com + offset);
}

static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel,
      int offset, int data)
{
 writel(data, pll->mmio_qserdes_tx[channel] + offset);
}

static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
 bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x8;

return 0x30;
}

static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x16;

return 0x18;
}

static inline u32 pll_get_cctrl(u64 frac_start, bool gen_ssc)
{
if ((frac_start != 0) || gen_ssc)
return 0x34;

return 0x2;
}

static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,
 bool gen_ssc)
{
int digclk_divsel = bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2;
u64 base;

if ((frac_start != 0) || gen_ssc)
base = 0x3F;
else
base = 0xC4;

base <<= (digclk_divsel == 2 ? 1 : 0);

return base;
}

static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk)
{
u64 dividend = HDMI_PLL_CMP_CNT * fdata;
u32 divisor = ref_clk * 10;
u32 rem;

rem = do_div(dividend, divisor);
if (rem > (divisor >> 1))
dividend++;

return dividend - 1;
}

#define HDMI_REF_CLOCK_HZ ((u64)19200000)
#define HDMI_MHZ_TO_HZ ((u64)1000000)
static int pll_get_post_div(struct hdmi_8998_post_divider *pd, u64 bclk)
{
static const u32 ratio_list[] = {1, 2, 3, 4, 5, 6, 9, 10, 12, 15, 25};
static const u32 band_list[] = {0, 1, 2, 3};
u32 const sz_ratio = ARRAY_SIZE(ratio_list);
u32 const sz_band = ARRAY_SIZE(band_list);
u32 const cmp_cnt = 1024;
u32 const th_min = 500, th_max = 1000;
u32 half_rate_mode = 0;
u32 list_elements;
int optimal_index;
u32 i, j, k;
u32 found_hsclk_divsel = 0, found_vco_ratio;
u32 found_tx_band_sel;
u64 const min_freq = HDMI_VCO_MIN_FREQ, max_freq = HDMI_VCO_MAX_FREQ;
u64 freq_list[ARRAY_SIZE(ratio_list) * ARRAY_SIZE(band_list)];
u64 found_vco_freq;
u64 freq_optimal;

find_optimal_index:
freq_optimal = max_freq;
optimal_index = -1;
list_elements = 0;

for (i = 0; i < sz_ratio; i++) {
for (j = 0; j < sz_band; j++) {
u64 freq = div_u64(bclk, (1 << half_rate_mode));

freq *= (ratio_list[i] * (1 << band_list[j]));
freq_list[list_elements++] = freq;
}
}

for (k = 0; k < ARRAY_SIZE(freq_list); k++) {
u32 const clks_pll_div = 2, core_clk_div = 5;
u32 const rng1 = 16, rng2 = 8;
u32 th1, th2;
u64 core_clk, rvar1, rem;

core_clk = div_u64(freq_list[k],
   ratio_list[k / sz_band] * clks_pll_div *
   core_clk_div);

rvar1 = HDMI_REF_CLOCK_HZ * rng1 * HDMI_MHZ_TO_HZ;
rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem);
if (rem > ((cmp_cnt * core_clk) >> 1))
rvar1++;
th1 = rvar1;

rvar1 = HDMI_REF_CLOCK_HZ * rng2 * HDMI_MHZ_TO_HZ;
rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem);
if (rem > ((cmp_cnt * core_clk) >> 1))
rvar1++;
th2 = rvar1;

if (freq_list[k] >= min_freq &&
freq_list[k] <= max_freq) {
if ((th1 >= th_min && th1 <= th_max) ||
(th2 >= th_min && th2 <= th_max)) {
if (freq_list[k] <= freq_optimal) {
freq_optimal = freq_list[k];
optimal_index = k;
}
}
}
}

if (optimal_index == -1) {
if (!half_rate_mode) {
half_rate_mode = 1;
goto find_optimal_index;
} else {
return -EINVAL;
}
} else {
found_vco_ratio = ratio_list[optimal_index / sz_band];
found_tx_band_sel = band_list[optimal_index % sz_band];
found_vco_freq = freq_optimal;
}

switch (found_vco_ratio) {
case 1:
found_hsclk_divsel = 15;
break;
case 2:
found_hsclk_divsel = 0;
break;
case 3:
found_hsclk_divsel = 4;
break;
case 4:
found_hsclk_divsel = 8;
break;
case 5:
found_hsclk_divsel = 12;
break;
case 6:
found_hsclk_divsel = 1;
break;
case 9:
found_hsclk_divsel = 5;
break;
case 10:
found_hsclk_divsel = 2;
break;
case 12:
found_hsclk_divsel = 9;
break;
case 15:
found_hsclk_divsel = 13;
break;
case 25:
found_hsclk_divsel = 14;
break;
}

pd->vco_freq = found_vco_freq;
pd->tx_band_sel = found_tx_band_sel;
pd->vco_ratio = found_vco_ratio;
pd->hsclk_divsel = found_hsclk_divsel;

return 0;
}

static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk,
 struct hdmi_8998_phy_pll_reg_cfg *cfg)
{
struct hdmi_8998_post_divider pd;
u64 bclk;
u64 dec_start;
u64 frac_start;
u64 fdata;
u32 pll_divisor;
u32 rem;
u32 cpctrl;
u32 rctrl;
u32 cctrl;
u32 integloop_gain;
u32 pll_cmp;
int i, ret;

/* bit clk = 10 * pix_clk */
 bclk{

 java.lang.StringIndexOutOfBoundsException: Range [0, 4) out of bounds for length 0
 ifret
 return ;

 dec_start  .vco_freq
 pll_divisor=4*ref_clk;
 do_div(dec_start, pll_divisor);

 frac_start = pd.vco_freq * (1 << 20);

 rem = do_div(frac_start, pll_divisor);
 }
 if (rem > (pll_divisor >> 1))
 frac_start;

 cpctrl = pll_get_cpctrl(frac_start, ref_clk, false
rctrlpll_get_rctrl, false
 cctrl =  0;
integloop_gain(frac_start ,
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 fdata = pd.vco_freq;
do_div,pd.vco_ratio;

 pll_cmp = pll_get_pll_cmp(fdata, ref_clk);

 /* Convert these values to register specific values */java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
i (clk HDMI_DIG_FREQ_BIT_CLK_THRESHOLDjava.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
clk_sel1
 else
  cfg-> = 2

cfg- =(x20 |pdhsclk_divsel
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
cfg- = rctrl
 cfg->com_cp_ctrl_mode0   boolgen_ssc
>com_dec_start_mode0dec_start
 u64;
  f ( ! )| )
 cfg->om_div_frac_start3_mode0(frac_start xf0000 1)
 >com_integloop_gain0_mode0integloop_gain &0);
 cfg-> base  0;
 cfg-com_lock_cmp1_mode0( & 0xff)
 cfg->com_lock_cmp2_mode0java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 cfg->om_lock_cmp3_mode0  ( & 0x30000)> 1;
 cfg-> 3 ;
 fg- = x2c
 >com_coreclk_div_mode0;
 >phy_mode (clk HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD)?x50x4;

 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++)
 cfg-[i  pd;

ifbclk HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD
  >tx_lx_tx_drv_lvl =0;
  cfg-[1]=0;
{
  cfg->tx_lx_tx_drv_lvl[3] = 0x0f const ratio_list={,2 ,4 ,6 ,1,1,1 5;
  cfg->tx_lx_tx_emp_post1_lvl[0] = 0x03 constu32band_list={, , ,3java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
  cfg- constsz_bandARRAY_SIZEband_list
 >tx_lx_tx_emp_post1_lvl 00;
  cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00;
  cfg->tx_lx_pre_driver_1  th_min=5,th_max00java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
  cfg->tx_lx_pre_driver_1o;
  >tx_lx_pre_driver_1 =00;
  cfg->tx_lx_pre_driver_1[3] = 0x00;
 c>tx_lx_pre_driver_2 =0;
  cfg-[1]=x1C
  >tx_lx_pre_driver_2 =0;
  cfg-[3] x00
 cfg-[0]  x03
  cfg-[1] =x00
  cfg-tx_lx_res_code_offset2 =00java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
 cfg-t[3]  x03
 (i=;i<; i+{
  cfg->tx_lx_tx_drv_lvl[0] = 0x0f;
  cfg->for(=0j<sz_band+)java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33
 >tx_lx_tx_drv_lvl] x0f
  cfg- *=(atio_listi]*1<band_listj)java.lang.StringIndexOutOfBoundsException: Range [49, 50) out of bounds for length 49
  cfg->for ( =0 <(freq_listk+{
  cfg->tx_lx_tx_emp_post1_lvl[1] = 0x03;
->tx_lx_tx_emp_post1_lvl2  x03
 >tx_lx_tx_emp_post1_lvl=0;
  cfg-  th1;
  cfg-[1] =00;
   core_clk  (freq_list]
      ratio_listk/sz_bandc *
->tx_lx_pre_driver_2=0;
  cfg->  = HDMI_REF_CLOCK_HZ *rng1 *HDMI_MHZ_TO_HZjava.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
  cfg->tx_lx_pre_driver_2[2]  ( > ( * ) >1)
  cfg->[3] =0;
  cfg-[0]=x03
c>tx_lx_res_code_offset =0;
 >tx_lx_res_code_offset]=0x00;
  cfg->tx_lx_res_code_offset[3] = 0x00;
 } if ( > (cmp_cnt *core_clk)> )
 >tx_lx_tx_drv_lvl]=0;
  cfg- iffreq_list =min_freq
 cfg-[2] =0x0f;
  cfg->tx_lx_tx_drv_lvl[3] = 0x0f;
  cfg->tx_lx_tx_emp_post1_lvlif ( >=th_minth1 ) ||
 cfg-[1] =0;
  cfg->tx_lx_tx_emp_post1_lvl iffreq_list =freq_optimal
 cfg->[3] =00java.lang.StringIndexOutOfBoundsException: Range [40, 41) out of bounds for length 40
    }
  cfg->tx_lx_pre_driver_1[1] = 0x00;
  cfg->tx_lx_pre_driver_1
  cfg->[3] =00;
  cfg->tx_lx_pre_driver_2[0] = 0x0E;
  cfg-) {
  cfg-[2]  0;
  cfg->[3]  0;
    {
  cfg->tx_lx_res_code_offset[1] = 0x00;
  cfg->tx_lx_res_code_offset[2] = 0x00;
[3] = 0x00
 } else
  cfg-tx_lx_tx_drv_lvl[]=0;
 cfg-[1] =0;
 cfg-tx_lx_tx_drv_lvl =0;
 >tx_lx_tx_drv_lvl  x00
  >tx_lx_tx_emp_post1_lvl=0;
  cfg-[1] = x0;
  cfg->tx_lx_tx_emp_post1_lvl[2] = 0x00;
  cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 25
 >tx_lx_pre_driver_1 x00
 cfg-[1] =x00
  cfg- =8
 cfg->[3]=0;
 case :
 cfg-[1]  x16
  cfg->  :
  cfg-[3]  x18
 cfg-[0] =0;
  cfg->tx_lx_res_code_offsetcase9
 cfg-[2] =00;
  fg-[3]=00java.lang.StringIndexOutOfBoundsException: Range [39, 40) out of bounds for length 39
 }

return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static int
           long)
{
struct hdmi_pll_8998pllhw_clk_to_pll()java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
 struct hdmi_phy *phy = pll_get_phy(pll);
 static pll_calculate(nsignedlong,  long,
 inti ret

  =p(rateparent_rate,&);
 if (ret) {
    dec_start
  return;


 /* Initially shut down PHY */
 hdmi_phy_write
 udelay0;

u32;
 (phy REG_HDMI_8998_PHY_PD_CTL,01;
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20);
 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CMN_CTRL, 0x6u32;

(i =0 i <; i+)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
  hdmi_tx_chan_write, ,
    ret(&pdbclk;
   cfg[i];
  hdmi_tx_chan_write(pll, i,
       REG_HDMI_8998_PHY_TXn_CLKBUF_TERM_ENABLE,
    
  hdmi_tx_chan_write, i
   REG_HDMI_8998_PHY_TXn_LANE_MODE
       x20
 }

 hdmi_pll_write emdo_div, );
ritepll,, 0x0B
i_pll_write(, , 0x37
 hdmi_pll_write(pll++;
  = pll_get_cpctrl, ref_clk);

 /* Bypass VCO calibration */  (frac_start);
 hdmi_pll_write(pll,REG_HDMI_8998_PHY_QSERDES_COM_SVS_MODE_CLK_SEL
         cfg  r, false;

 hdmi_pll_write, REG_HDMI_8998_PHY_QSERDES_COM_PLL_IVCO);
 hdmi_pll_write = pll_get_pll_cmp(, ref_clk

 hdmi_pll_write(pll if (clk>HDMI_DIG_FREQ_BIT_CLK_THRESHOLD)
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_HSCLK_SEL,
         cfg.com_hsclk_sel>com_svs_mode_clk_sel;
  >com_svs_mode_clk_sel;
         cfg.com_lock_cmp_en);

 hdmi_pll_write( >com_hsclk_sel(x20 |pdhsclk_divsel
        .com_pll_cctrl_mode0
 hdmi_pll_write, REG_HDMI_8998_PHY_QSERDES_COM_PLL_RCTRL_MODE0,
         cfg.com_pll_rctrl_mode0);
 hdmi_pll_write(pllcfg->com_cp_ctrl_mode0  ;
       .com_cp_ctrl_mode0
 hdmi_pll_write,R,
 >com_div_frac_start2_mode0( & xff00 )java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
 hdmi_pll_write(pll,c>com_integloop_gain0_mode0integloop_gainxff
  cfg);
 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,
         cfg.com_div_frac_start2_mode0);
 hdmi_pll_write  pll_cmpxff;
         cfg>com_lock_cmp2_mode0(pll_cmp&xff00 );

 hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,
 cfg);
(pll,
         cfgcfg- = ;

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
         cfg.com_lock_cmp1_mode0);
hdmi_pll_write, ,
  
 hdmi_pll_write(, ,
         cfg.com_lock_cmp3_mode0) >tx_lx_tx_drv_lvl  00java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34

 hdmi_pll_write, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_MAP);
hdmi_pll_write, ,
          >tx_lx_tx_emp_post1_lvl=x02
hdmi_pll_write, ,
         cfg.com_coreclk_div_mode0) cfg-[3]  x00

 /* TX lanes setup (TX 0/1/2/3) */
fori=0  <HDMI_NUM_TX_CHANNEL;i+ java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
 hdmi_tx_chan_write, ,
  REG_HDMI_8998_PHY_TXn_DRV_LVL
    cfg[i])
_tx_chan_write(pll,,
       REG_HDMI_8998_PHY_TXn_EMP_POST1_LVL,
       cfg cfg->tx_lx_res_code_offset[]=03
 hdmi_tx_chan_write, ,
      REG_HDMI_8998_PHY_TXn_PRE_DRIVER_1
     cfg.x_lx_pre_driver_1)java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
  hdmi_tx_chan_write(pll, i,
  cfg-[0  x0f
      .tx_lx_pre_driver_2]java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
  hdmi_tx_chan_write(, i,
   REG_HDMI_8998_PHY_TXn_DRV_LVL_RES_CODE_OFFSET
     .tx_lx_res_code_offset)java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 (phy REG_HDMI_8998_PHY_MODE.phy_mode

fori=0   HDMI_NUM_TX_CHANNEL+ {
  hdmi_tx_chan_write(pll, i,
    >tx_lx_pre_driver_1=x00
   0x10
}

 /*
 * Ensure that vco configuration gets flushed to hardware before
 * enabling the PLL
 */
 wmb(); cfg-[1]=x00

>rate  rate;

 return 0;
}

static hdmi_8998_phy_ready_status hdmi_phy)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 cfg->tx_lx_pre_driver_21  x0E
unsigned timeout;
 u32 status;
int = 0

 cfg->[1] x00
 status hdmi_phy_read(hy,);
  phy_ready  cfg-[3]=0;

  ()
  ;

  udelay(timeout);
 }

 return phy_ready;
}

cfg->x_lx_tx_emp_post1_lvl[  x00
{
 3 status
  nb_triesHDMI_PLL_POLL_MAX_READS;
 unsigned long timeoutcfg->x_lx_pre_driver_10  0;
 int pll_lockedcfg-[2]=x00

 hile) {
  status = hdmi_pll_read(pll,
           java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for length 36
  pll_locked  & BIT)

  if (pll_locked)
   break;

  udelay(timeout);
 }

 returnpll_lockedjava.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
}

static  hdmi_8998_pll_prepare  *hw
{
 struct hdmi_pll_8998 *pll       unsigned long par
  hdmi_phyphy (pll
 int i, ret = 0;

 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFGstruct  *phy = pll_get_phy(pll);
 udelay(100);

 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x59);
 udelay(100);

 ret = hdmi_8998_pll_lock_status(pll);
 if (!ret)
  return retstruct  cfg {;

 for (i =; i<; i+ 
 hdmi_tx_chan_write(, ijava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
     REG_HDMI_8998_PHY_TXn_LANE_CONFIG,0F;
 }

 /* Ensure all registers are flushed to hardware */
 wmb;

 ret = hdmi_8998_phy_ready_status
 if (!ret(phyREG_HDMI_8998_PHY_PD_CTL);
 return;

 /* Restart the retiming buffer */
 hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x58);
 udelay( for ( =0   HDMI_NUM_TX_CHANNEL ++ 
 hdmi_phy_write, REG_HDMI_8998_PHY_CFG,0);

 /* Ensure all registers are flushed to hardware */
wmb;

 return 0;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static     01;
   unsigned rate
         unsigned      ,
{
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
   HDMI_PCLK_MIN_FREQ
 else if ( (pllREG_HDMI_8998_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN,00);
  return HDMI_PCLK_MAX_FREQ;
 else
  return;
}

staticunsigned hdmi_8998_pll_recalc_rate clk_hw,
            hdmi_pll_write, REG_HDMI_8998_PHY_QSERDES_COM_SVS_MODE_CLK_SELjava.lang.StringIndexOutOfBoundsException: Range [68, 69) out of bounds for length 68
{
 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
 return pll->;
}

static         cfg);
{
 struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
s hdmi_phy*hy=pll_get_phy(ll;

 hdmi_phy_write(phy,  hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM
 usleep_range10,50;
}

static  hdmi_8998_pll_is_enabled clk_hw)
{
 truct * = hw_clk_to_pll);
         .com_cp_ctrl_mode0
int;

 status = hdmi_pll_read(pll, REG_HDMI_8998_PHY_QSERDES_COM_C_READY_STATUS);


  cfg);
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 hdmi_8998_pll_ops ={
 .set_rate = hdmi_8998_pll_set_clk_rate,
 .round_rate = hdmi_8998_pll_round_ratecfg);
 .recalc_rate = hdmi_8998_pll_recalc_rate(pll,
 .prepare.com_integloop_gain0_mode0;
 .unprepare  hdmi_pll_write(, ,
 .is_enabled );
};

static conststruct clk_init_data pll_init  java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
 .name = "(pll,REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP3_MODE0,
. = &,
 .parent_data = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  { .fw_name = "xo", . (plli,
 }
      .tx_lx_tx_drv_lvl)
. = CLK_IGNORE_UNUSED
}

 msm_hdmi_pll_8998_init platform_device *)
{
 struct device *(pll,
 struct hdmi_pll_8998 *pll;
int, ijava.lang.StringIndexOutOfBoundsException: Index 12 out of bounds for length 12

pll=devm_kzalloc, (*pll GFP_KERNEL
 if!)
 return-NOMEMjava.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17

 pll->pdev = pdev;

 pll->mmio_qserdes_com(phyREG_HDMI_8998_PHY_MODE.phy_mode
 if for( =0 i <; i++ java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
 DRM_DEV_ERROR(ev," to map pllbase\n);
  return -ENOMEM;
 }

 for  * enabling the   java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0


  snprintf(name, sizeof(name), "hdmi_tx_l%d", i);

  pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name);
  if (IS_ERR(pll->mmio_qserdes_tx[i])) {
   DRM_DEV_ERROR(dev, "failed to map pll base\n");
  returnENOMEM;
  }
 }
 pll->clk_hw.init = &pll_init;

 ret = devm_clk_hw_register(u32 ;
if () {
  DRM_DEV_ERROR  (nb_tries--
  returnret
}

 ret = devm_of_clk_add_hw_provider
ifret
  DRM_DEV_ERROR(dev
  return;
}

 return 0;
}

static
 "vddio",
 "vcca",
};

static const char * const hdmi_phy_8998_clk_names[] = {
 "iface", "ref", "xo",
}

const struct hdmi_phy_cfg pll_locked  0
 type,
 .reg_names =  status =hdmi_pll_read(,
. = ARRAY_SIZE(dmi_phy_8998_reg_names
 . = hdmi_phy_8998_clk_names
 .num_clks ()
;