if (sbridge->next_bridge->ops & DRM_BRIDGE_OP_EDID) {
drm_edid = drm_bridge_edid_read(sbridge->next_bridge, connector); if (!drm_edid)
DRM_INFO("EDID read failed. Fallback to standard modes\n");
} else {
drm_edid = NULL;
}
drm_edid_connector_update(connector, drm_edid);
if (!drm_edid) { /* * In case we cannot retrieve the EDIDs (missing or broken DDC * bus from the next bridge), fallback on the XGA standards and * prefer a mode pretty much anyone can handle.
*/
ret = drm_add_modes_noedid(connector, 1920, 1200);
drm_set_preferred_mode(connector, 1024, 768); return ret;
}
ret = drm_edid_connector_add_modes(connector);
drm_edid_free(drm_edid);
if (!sbridge->next_bridge) {
dev_dbg(&pdev->dev, "Next bridge not found, deferring probe\n"); return -EPROBE_DEFER;
}
/* Get the regulator and GPIO resources. */
sbridge->vdd = devm_regulator_get_optional(&pdev->dev, "vdd"); if (IS_ERR(sbridge->vdd)) { int ret = PTR_ERR(sbridge->vdd); if (ret == -EPROBE_DEFER) return -EPROBE_DEFER;
sbridge->vdd = NULL;
dev_dbg(&pdev->dev, "No vdd regulator found: %d\n", ret);
}
sbridge->enable = devm_gpiod_get_optional(&pdev->dev, "enable",
GPIOD_OUT_LOW); if (IS_ERR(sbridge->enable)) return dev_err_probe(&pdev->dev, PTR_ERR(sbridge->enable), "Unable to retrieve enable GPIO\n");
/* * We assume the ADV7123 DAC is the "default" for historical reasons * Information taken from the ADV7123 datasheet, revision D. * NOTE: the ADV7123EP seems to have other timings and need a new timings * set if used.
*/ staticconststruct drm_bridge_timings default_bridge_timings = { /* Timing specifications, datasheet page 7 */
.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
.setup_time_ps = 500,
.hold_time_ps = 1500,
};
/* * Information taken from the THS8134, THS8134A, THS8134B datasheet named * "SLVS205D", dated May 1990, revised March 2000.
*/ staticconststruct drm_bridge_timings ti_ths8134_bridge_timings = { /* From timing diagram, datasheet page 9 */
.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, /* From datasheet, page 12 */
.setup_time_ps = 3000, /* I guess this means latched input */
.hold_time_ps = 0,
};
/* * Information taken from the THS8135 datasheet named "SLAS343B", dated * May 2001, revised April 2013.
*/ staticconststruct drm_bridge_timings ti_ths8135_bridge_timings = { /* From timing diagram, datasheet page 14 */
.input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, /* From datasheet, page 16 */
.setup_time_ps = 2000,
.hold_time_ps = 500,
};
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