Quelle  a6xx.xml   Sprache: XML

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>
<import file="adreno/a6xx_enums.xml"/>
<import file="adreno/a7xx_enums.xml"/>
<import file="adreno/a6xx_perfcntrs.xml"/>
<import file="adreno/a7xx_perfcntrs.xml"/>
<import file="adreno/a6xx_descriptors.xml"/>

<!--
Each register that is actually being used by driver should have "usage" defined,
currently there are following usages:
- "cmd" - the register is used outside of renderpass and blits,
roughly corresponds to registers used in ib1 for Freedreno
- "rp_blit" - the register is used inside renderpass or blits
(ib2 for Freedreno)

It is expected that register with "cmd" usage may be written into only at
the start of the command buffer (ib1), while "rp_blit" usage indicates that register
is either overwritten by renderpass/blit (ib2) or not used if not overwritten
by a particular renderpass/blit.
-->

<domain name="A6XX" width="32" prefix="variant" varset="chip">
 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip">
  <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
  <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
  <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
  <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
  <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
  <bitfield name="CP_SW" pos="8" type="boolean"/>
  <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
  <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
  <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
  <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
  <bitfield name="CP_IB2" pos="13" type="boolean"/>
  <bitfield name="CP_IB1" pos="14" type="boolean"/>
  <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>
  <!-- Same as above but different name??: -->
  <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>
  <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
  <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
  <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
  <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>
  <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
  <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
  <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
  <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
  <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
  <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
  <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
  <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/>
  <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
  <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
 </bitset>

 <!--
Note the _LPAC bits probably *actually* first appeared in a660, but the
_BV bits are new in a7xx
 -->
 <bitset name="A6XX_CP_INT" varset="chip">
  <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
  <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
  <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
  <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
  <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
  <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
  <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
  <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>
  <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
 </bitset>

 <reg64 offset="0x0800" name="CP_RB_BASE"/>
 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
  <bitfield name="IFPC" pos="0" type="boolean"/>
 </reg32>
 <reg32 offset="0x0821" name="CP_HW_FAULT"/>
 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
 <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
 <reg32 offset="0x0825" name="CP_STATUS_1"/>
 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
 <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
 <reg32 offset="0x0844" name="CP_APRIV_CNTL">
  <!-- Crashdumper writes -->
  <bitfield pos="6" name="CDWRITE" type="boolean"/>
  <!-- Crashdumper reads -->
  <bitfield pos="5" name="CDREAD" type="boolean"/>

  <!-- 4 is unknown -->

  <!-- RPTR shadow writes -->
  <bitfield pos="3" name="RBRPWB" type="boolean"/>
  <!-- Memory accesses from PM4 packets in the ringbuffer -->
  <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/>
  <!-- Ringbuffer reads -->
  <bitfield pos="1" name="RBFETCH" type="boolean"/>
  <!-- Instruction cache fetches -->
  <bitfield pos="0" name="ICACHE" type="boolean"/>
 </reg32>
 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
 <reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>
 <!-- all the threshold values seem to be in units of quad-dwords: -->
 <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
  <doc>
   b0..7 identifies where MRB data starts (and RB data ends)
   b8.15 identifies where VSD data starts (and MRB data ends)
   b16..23 identifies where IB1 data starts (and RB data ends)
   b24..31 identifies where IB2 data starts (and IB1 data ends)
  </doc>
  <bitfield name="MRB_START" low="0" high="7" shr="2"/>
  <bitfield name="VSD_START" low="8" high="15" shr="2"/>
  <bitfield name="IB1_START" low="16" high="23" shr="2"/>
  <bitfield name="IB2_START" low="24" high="31" shr="2"/>
 </reg32>
 <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
  <doc>
   low bits identify where CP_SET_DRAW_STATE stateobj
   processing starts (and IB2 data ends). I'm guessing
   b8 is part of this since (from downstream kgsl):

    /* ROQ sizes are twice as big on a640/a680 than on a630 */
    if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
     kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
     kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
    } ...
  </doc>
  <bitfield name="SDS_START" low="0" high="8" shr="2"/>
  <!-- total ROQ size: -->
  <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
 </reg32>
 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
 <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
 <reg32 offset="0x084F" name="CP_PROTECT_CNTL">
  <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
  <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
  <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
 </reg32>

 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
  <reg32 offset="0x0" name="REG" type="uint"/>
 </array>
 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
  <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
 </array>

 <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL">
  <bitfield name="STOP" pos="0" type="boolean"/>
  <bitfield name="LEVEL" low="6" high="7"/>
  <bitfield name="USES_GMEM" pos="8" type="boolean"/>
  <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/>
 </reg32>
 <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
 <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
 <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
 <reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
 <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
 <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE"/>
 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
 <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
 <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
 <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
 <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
 <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
 <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
 <reg64 offset="0x0928" name="CP_IB1_BASE"/>
 <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
 <reg64 offset="0x092B" name="CP_IB2_BASE"/>
 <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
 <!-- SDS == CP_SET_DRAW_STATE: -->
 <reg64 offset="0x092e" name="CP_SDS_BASE"/>
 <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
 <reg64 offset="0x0931" name="CP_MRB_BASE"/>
 <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
 <!--
VSD == Visibility Stream Decode
This is used by CP to read the draw stream and skip empty draws
-->
 <reg64 offset="0x0934" name="CP_VSD_BASE"/>

 <bitset name="a6xx_roq_status" inline="yes">
  <bitfield name="RPTR" low="0" high="9"/>
  <bitfield name="WPTR" low="16" high="25"/>
 </bitset>
 <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status"/>
 <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status"/>
 <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status"/>
 <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status"/>
 <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status"/>
 <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status"/>

 <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE"/>
 <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE"/>
 <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE"/>
 <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE"/>
 <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE"/>

 <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB">
  <doc>number of remaining dwords incl current dword being consumed?</doc>
  <bitfield name="REM" low="16" high="31"/>
 </reg32>
 <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1">
  <doc>number of remaining dwords incl current dword being consumed?</doc>
  <bitfield name="REM" low="16" high="31"/>
 </reg32>
 <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2">
  <doc>number of remaining dwords incl current dword being consumed?</doc>
  <bitfield name="REM" low="16" high="31"/>
 </reg32>
 <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS">
  <doc>number of remaining dwords incl current dword being consumed?</doc>
  <bitfield name="REM" low="16" high="31"/>
 </reg32>
 <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB">
  <doc>number of dwords that have already been read but haven't been consumed by $addr
  <bitfield name="REM" low="16" high="31"/>
 </reg32>
 <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD">
  <doc>number of remaining dwords incl current dword being consumed?</doc>
  <bitfield name="REM" low="16" high="31"/>
 </reg32>

 <bitset name="a7xx_aperture_cntl" inline="yes">
  <bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>
  <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>
  <bitfield name="CONTEXT" low="4" high="5"/>
 </bitset>
 <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
 <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>
 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
 <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/>
 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>
 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>

 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>

 <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX-"/>
 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>

 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>

 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
 <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
 <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
 <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>

 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>
 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>
 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>

 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>
 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>
 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>
 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>
 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>
 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>
 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>
 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>
 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>
 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>
 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>
 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>

 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 <reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
 <reg32 offset="0x0210" name="RBBM_STATUS">
  <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
  <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
  <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
  <bitfield pos="20" name="VSC_BUSY" type="boolean"/>
  <bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
  <bitfield pos="18" name="SP_BUSY" type="boolean"/>
  <bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
  <bitfield pos="16" name="VPC_BUSY" type="boolean"/>
  <bitfield pos="15" name="VFD_BUSY" type="boolean"/>
  <bitfield pos="14" name="TESS_BUSY" type="boolean"/>
  <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
  <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
  <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
  <bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
  <bitfield pos="9"  name="A2D_BUSY" type="boolean"/>
  <bitfield pos="8"  name="CCU_BUSY" type="boolean"/>
  <bitfield pos="7"  name="RB_BUSY" type="boolean"/>
  <bitfield pos="6"  name="RAS_BUSY" type="boolean"/>
  <bitfield pos="5"  name="TSE_BUSY" type="boolean"/>
  <bitfield pos="4"  name="VBIF_BUSY" type="boolean"/>
  <bitfield pos="3"  name="GFX_DBGC_BUSY" type="boolean"/>
  <bitfield pos="2"  name="CP_BUSY" type="boolean"/>
  <bitfield pos="1"  name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
  <bitfield pos="0"  name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
 </reg32>
 <reg32 offset="0x0211" name="RBBM_STATUS1"/>
 <reg32 offset="0x0212" name="RBBM_STATUS2"/>
 <reg32 offset="0x0213" name="RBBM_STATUS3">
  <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
 </reg32>
 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>

 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>

 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>

 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>
 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>
 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>
 <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>
 <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/>
 <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/>
 <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/>
 <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/>
 <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/>
 <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/>
 <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/>
 <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/>
 <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>
 <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>

 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>

 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
 <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
 <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
 <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
 <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
 <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
 <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/>
 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>

 <!---
    This block of registers aren't tied to perf counters. They
    count various geometry stats, for example number of
    vertices in, number of primnitives assembled etc.
-->

 <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES"/>
 <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES"/>
 <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS"/>
 <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS"/>
 <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS"/>
 <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS"/>
 <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES"/>
 <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS"/>
 <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES"/>
 <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS"/>
 <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS"/>

 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
 <reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>
 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
  <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
 </reg32>

 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
 <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>
 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/>
 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
  <bitfield name="TXDONE" pos="0" type="boolean"/>
 </reg32>
 <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/>
 <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/>
 <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/>
 <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/>
 <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/>
 <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/>
 <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/>
 <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/>
 <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/>
 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
 <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>

 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A6XX">
  <bitfield high="7" low="0" name="PING_INDEX"/>
  <bitfield high="15" low="8" name="PING_BLK_SEL"/>
 </reg32>
 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A7XX-">
  <bitfield high="7" low="0" name="PING_INDEX"/>
  <bitfield high="24" low="16" name="PING_BLK_SEL"/>
 </reg32>
 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
  <bitfield high="5" low="0" name="TRACEEN"/>
  <bitfield high="14" low="12" name="GRANU"/>
  <bitfield high="31" low="28" name="SEGT"/>
 </reg32>
 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
  <bitfield high="27" low="24" name="ENABLE"/>
 </reg32>
 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
  <bitfield high="3" low="0" name="BYTEL0"/>
  <bitfield high="7" low="4" name="BYTEL1"/>
  <bitfield high="11" low="8" name="BYTEL2"/>
  <bitfield high="15" low="12" name="BYTEL3"/>
  <bitfield high="19" low="16" name="BYTEL4"/>
  <bitfield high="23" low="20" name="BYTEL5"/>
  <bitfield high="27" low="24" name="BYTEL6"/>
  <bitfield high="31" low="28" name="BYTEL7"/>
 </reg32>
 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
  <bitfield high="3" low="0" name="BYTEL8"/>
  <bitfield high="7" low="4" name="BYTEL9"/>
  <bitfield high="11" low="8" name="BYTEL10"/>
  <bitfield high="15" low="12" name="BYTEL11"/>
  <bitfield high="19" low="16" name="BYTEL12"/>
  <bitfield high="23" low="20" name="BYTEL13"/>
  <bitfield high="27" low="24" name="BYTEL14"/>
  <bitfield high="31" low="28" name="BYTEL15"/>
 </reg32>
 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
 <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2" variants="A6XX"/>
 <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX">
  <doc>
   Set to true when binning, isn't changed afterwards
  </doc>
  <bitfield name="BINNING" pos="0" type="boolean"/>
 </reg32>
 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
 <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/>
 <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/>
 <reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/>
 <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/>
 <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>
 <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/>
 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
 <reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd">
  <bitfield high="7" low="0" name="PERFSEL"/>
 </reg32>
 <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
 <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
 <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>

 <reg32 offset="0x3000" name="VBIF_VERSION"/>
 <reg32 offset="0x3001" name="VBIF_CLKON">
  <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
 </reg32>
 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
  <bitfield low="0" high="3" name="DATA_SEL"/>
 </reg32>
 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
  <bitfield low="0" high="8" name="DATA_SEL"/>
 </reg32>
 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>

 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
 <reg32 offset="0x3c45" name="GBIF_HALT"/>
 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
 <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>

 <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
 <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit">
  <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
  <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
 </reg32>
 <reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/>
 <reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="rp_blit">
  <bitfield name="NX" low="1" high="10" type="uint"/>
  <bitfield name="NY" low="11" high="20" type="uint"/>
 </reg32>
 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit">
  <reg32 offset="0x0" name="REG">
   <doc>
    Configures the mapping between VSC_PIPE buffer and
    bin, X/Y specify the bin index in the horiz/vert
    direction (0,0 is upper left, 0,1 is leftmost bin
    on second row, and so on).  W/H specify the number
    of bins assigned to this VSC_PIPE in the horiz/vert
    dimension.
   </doc>
   <bitfield name="X" low="0" high="9" type="uint"/>
   <bitfield name="Y" low="10" high="19" type="uint"/>
   <bitfield name="W" low="20" high="25" type="uint"/>
   <bitfield name="H" low="26" high="31" type="uint"/>
  </reg32>
 </array>
 <!--
HW binning primitive & draw streams, which enable draws and primitives
within a draw to be skipped in the main tile pass.  See:
https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format

Compared to a5xx and earlier, we just program the address of the first
stream and hw adds (pipe_num * VSC_*_STRM_PITCH)

LIMIT is set to PITCH - 64, to make room for a bit of overflow
 -->
 <reg64 offset="0x0c30" name="VSC_PIPE_DATA_PRIM_BASE" type="waddress" usage="cmd"/>
 <reg32 offset="0x0c32" name="VSC_PIPE_DATA_PRIM_STRIDE" usage="cmd"/>
 <reg32 offset="0x0c33" name="VSC_PIPE_DATA_PRIM_LENGTH" usage="cmd"/>
 <reg64 offset="0x0c34" name="VSC_PIPE_DATA_DRAW_BASE" type="waddress" usage="cmd"/>
 <reg32 offset="0x0c36" name="VSC_PIPE_DATA_DRAW_STRIDE" usage="cmd"/>
 <reg32 offset="0x0c37" name="VSC_PIPE_DATA_DRAW_LENGTH" usage="cmd"/>

 <array offset="0x0c38" name="VSC_CHANNEL_VISIBILITY" stride="1" length="32" usage="rp_blit">
  <doc>
   Seems to be a bitmap of which tiles mapped to the VSC
   pipe contain geometry.

   I suppose we can connect a maximum of 32 tiles to a
   single VSC pipe.
  </doc>
  <reg32 offset="0x0" name="REG"/>
 </array>

 <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
  <doc>
   Has the size of data written to corresponding VSC_PRIM_STRM
   buffer.
  </doc>
  <reg32 offset="0x0" name="REG"/>
 </array>

 <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
  <doc>
   Has the size of data written to corresponding VSC pipe, ie.
   same thing that is written out to VSC_SIZE_BASE
  </doc>
  <reg32 offset="0x0" name="REG"/>
 </array>

 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>

 <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
 <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
 <!-- always 0x03200000 ? -->
 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"  usage="cmd"/>

 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
 <bitset name="a6xx_reg_xy" inline="yes">
  <bitfield name="X" low="0" high="13" type="uint"/>
  <bitfield name="Y" low="16" high="29" type="uint"/>
 </bitset>

 <reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit">
  <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
  <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
  <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
  <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
  <!-- controls near z clip behavior (set for vulkan) -->
  <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
  <!-- guess based on a3xx and meaning of bits 8 and 9
     if the guess is right then this is related to point sprite clipping -->
  <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
  <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
  <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
 </reg32>

 <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes">
  <bitfield name="CLIP_MASK" low="0" high="7"/>
  <bitfield name="CULL_MASK" low="8" high="15"/>
 </bitset>
 <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/>
 <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/>
 <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/>
 <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit"/>

 <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" usage="rp_blit">
  <!-- see also RB_INTERP_CNTL -->
  <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
  <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
  <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
  <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
  <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
  <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
  <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
  <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>
  <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>
 </reg32>
 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit">
  <bitfield name="HORZ" low="0" high="8" type="uint"/>
  <bitfield name="VERT" low="10" high="18" type="uint"/>
 </reg32>

 <!-- Something connected to depth-stencil attachment size -->
 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>

 <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>

 <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
 <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
 <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
 <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>

 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->

 <!-- 0x8006-0x800f invalid -->
 <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" usage="rp_blit">
  <reg32 offset="0" name="XOFFSET" type="float"/>
  <reg32 offset="1" name="XSCALE" type="float"/>
  <reg32 offset="2" name="YOFFSET" type="float"/>
  <reg32 offset="3" name="YSCALE" type="float"/>
  <reg32 offset="4" name="ZOFFSET" type="float"/>
  <reg32 offset="5" name="ZSCALE" type="float"/>
 </array>
 <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" usage="rp_blit">
  <reg32 offset="0" name="MIN" type="float"/>
  <reg32 offset="1" name="MAX" type="float"/>
 </array>

 <reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit">
  <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
  <bitfield name="CULL_BACK" pos="1" type="boolean"/>
  <bitfield name="FRONT_CW" pos="2" type="boolean"/>
  <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
  <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
  <bitfield name="UNK12" pos="12"/>
  <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
  <bitfield name="UNK15" low="15" high="16"/>
  <!--
                        On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have
                        the ability to add the view index to either the RT array
                        index or the viewport index, and it seems that
                        MULTIVIEW_ENABLE doesn't do anything, instead we need to
                        set at least one of RENDERTARGETINDEXINCR or
                        VIEWPORTINDEXINCR to enable multiview. The blob still
                        sets MULTIVIEW_ENABLE regardless.
                        TODO: what about gen2 (a640)?
-->
  <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/>
  <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
  <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
  <bitfield name="UNK20" low="20" high="22"/>
 </reg32>
 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit">
  <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
  <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
 </reg32>
 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/>
 <!-- 0x8093 invalid -->
 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit">
  <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
 </reg32>
 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/>
 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/>
 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/>
 <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit">
  <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
  <bitfield name="UNK3" pos="3"/>
 </reg32>

 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd">
  <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
  <enum name="a6xx_shift_amount">
   <value value="0" name="NO_SHIFT"/>
   <value value="1" name="HALF_PIXEL_SHIFT"/>
   <value value="2" name="FULL_PIXEL_SHIFT"/>
  </enum>
  <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/>
  <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>
  <bitfield name="UNK4" low="4" high="5"/>
 </reg32>
 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
  <bitfield name="UNK0" pos="0" type="boolean"/>
  <bitfield name="LINELENGTHEN" pos="1" type="boolean"/>
 </reg32>

 <bitset name="a6xx_gras_us_xs_siv_cntl" inline="yes">
  <bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
  <bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
 </bitset>
 <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/>
 <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/>
 <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/>
 <!-- 0x809e/0x809f invalid -->

 <enum name="a6xx_sequenced_thread_dist">
  <value value="0x0" name="DIST_SCREEN_COORD"/>
  <value value="0x1" name="DIST_ALL_TO_RB0"/>
 </enum>

 <enum name="a6xx_single_prim_mode">
  <value value="0x0" name="NO_FLUSH"/>
  <doc>
   In addition to FLUSH_PER_OVERLAP, guarantee that UCHE
   and CCU don't get out of sync when fetching the previous
   value for the current pixel. With NO_FLUSH, there's the
   possibility that the flags for the current pixel are
   flushed before the data or vice-versa, leading to
   texture fetches via UCHE getting out of sync values.
   This mode should eliminate that. It's used in bypass
   mode for coherent blending
   (GL_KHR_blend_equation_advanced_coherent) as well as
   non-coherent blending.
  </doc>
  <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/>
  <doc>
   Invalidate UCHE and wait for any pending work to finish
   if there was possibly an overlapping primitive prior to
   the current one. This is similar to a combination of
   GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and
   WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for
   coherent blending
   (GL_KHR_blend_equation_advanced_coherent).
  </doc>
  <value value="0x3" name="FLUSH_PER_OVERLAP"/>
 </enum>

 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
 <enum name="a6xx_raster_mode">
  <value value="0x0" name="TYPE_TILED"/>
  <value value="0x1" name="TYPE_WRITER"/>
 </enum>

 <!-- I'm guessing this is the same as a3xx -->
 <enum name="a6xx_raster_direction">
  <value value="0x0" name="LR_TB"/>
  <value value="0x1" name="RL_TB"/>
  <value value="0x2" name="LR_BT"/>
  <value value="0x3" name="RB_BT"/>
 </enum>

 <reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit">
  <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
  <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
  <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
  <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
  <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>
  <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
  <bitfield name="UNK9" pos="9" type="boolean"/>
  <bitfield name="ROTATION" low="10" high="11" type="uint"/>
  <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
 </reg32>

 <enum name="a6xx_render_mode">
  <value value="0x0" name="RENDERING_PASS"/>
  <value value="0x1" name="BINNING_PASS"/>
 </enum>

 <enum name="a6xx_buffers_location">
  <value value="0" name="BUFFERS_IN_GMEM"/>
  <value value="3" name="BUFFERS_IN_SYSMEM"/>
 </enum>

 <enum name="a6xx_lrz_feedback_mask">
  <value value="0x0" name="LRZ_FEEDBACK_NONE"/>
  <value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/>
  <value value="0x2" name="LRZ_FEEDBACK_EARLY_Z_LATE_Z"/>
  <!-- We don't have a flag type and this flags combination is often used -->
  <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z"/>
  <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/>
 </enum>

 <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" usage="rp_blit">
  <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
  <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
  <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
  <doc>Disable LRZ feedback writes</doc>
  <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
  <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/>
  <doc>
   Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have
   GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass.
   In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered.
  </doc>
  <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>
  <bitfield name="UNK27" pos="27"/>
 </reg32>

 <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" usage="rp_blit">
  <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
  <bitfield name="UNK2" pos="2"/>
  <bitfield name="UNK3" pos="3"/>
 </reg32>
 <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" usage="rp_blit">
  <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
  <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
 </reg32>

 <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes">
  <bitfield name="UNK0" pos="0"/>
  <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
 </bitset>

 <bitset name="a6xx_programmable_msaa_pos" inline="yes">
  <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
  <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
  <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
  <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
  <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
  <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
  <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
  <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
 </bitset>

 <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/>
 <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/>
 <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/>

 <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>

 <!-- 0x80a7-0x80ae invalid -->
 <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/>

 <bitset name="a6xx_scissor_xy" inline="yes">
  <bitfield name="X" low="0" high="15" type="uint"/>
  <bitfield name="Y" low="16" high="31" type="uint"/>
 </bitset>
 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit">
  <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
  <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
 </array>
 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit">
  <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
  <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
 </array>

 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>

 <enum name="a6xx_fsr_combiner">
  <value value="0" name="FSR_COMBINER_OP_KEEP"/>
  <value value="1" name="FSR_COMBINER_OP_REPLACE"/>
  <value value="2" name="FSR_COMBINER_OP_MIN"/>
  <value value="3" name="FSR_COMBINER_OP_MAX"/>
  <value value="4" name="FSR_COMBINER_OP_MUL"/>
 </enum>

 <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" variants="A7XX-" usage="rp_blit">
  <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/>
  <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/>
  <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/>
  <bitfield name="COMBINER_OP_1" low="5" high="7" type="a6xx_fsr_combiner"/>
  <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/>
  <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/>
  <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/>
 </reg32>
 <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
  <bitfield name="LAYERED" pos="0" type="boolean"/>
  <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/>
 </reg32>
 <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" variants="A7XX-" usage="rp_blit">
  <bitfield name="WIDTH" low="0" high="15" type="uint"/>
  <bitfield name="HEIGHT" low="16" high="31" type="uint"/>
 </reg32>
 <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX-" type="waddress" usage="rp_blit"/>
 <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" variants="A7XX-" usage="rp_blit">
  <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/>
  <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/>
 </reg32>

 <enum name="a6xx_lrz_dir_status">
  <value value="0x1" name="LRZ_DIR_LE"/>
  <value value="0x2" name="LRZ_DIR_GE"/>
  <value value="0x3" name="LRZ_DIR_INVALID"/>
 </enum>

 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit">
  <bitfield name="ENABLE" pos="0" type="boolean"/>
  <doc>LRZ write also disabled for blend/etc.</doc>
  <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
  <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
  <bitfield name="GREATER" pos="2" type="boolean"/>
  <doc>
   Clears the LRZ block being touched to:
   - 0.0 if GREATER
   - 1.0 if LESS
  </doc>
  <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/>
  <!-- set when depth-test + depth-write enabled -->
  <bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/>
  <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
  <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>
  <doc>
   If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
   buffer, in case of mismatched direction writes 0 (disables LRZ).
  </doc>
  <bitfield name="DIR_WRITE" pos="8" type="boolean"/>
  <doc>
   Disable LRZ based on previous direction and the current one.
   If DIR_WRITE is not enabled - there is no write to direction buffer.
  </doc>
  <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/>
  <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
 </reg32>

 <enum name="a6xx_fragcoord_sample_mode">
  <value value="0" name="FRAGCOORD_CENTER"/>
  <value value="3" name="FRAGCOORD_SAMPLE"/>
 </enum>

 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit">
  <bitfield name="SAMPLEID" pos="0" type="boolean"/>
  <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
 </reg32>

 <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" usage="rp_blit">
  <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
 </reg32>
 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/>
 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit">
  <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
  <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/>
 </reg32>

 <!--
The LRZ "fast clear" buffer is initialized to zero's by blob, and
read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set.  It appears
to store 1b/block.  It appears that '0' means block has original
depth clear value, and '1' means that the corresponding block in
LRZ has been modified.  Ignoring alignment/padding, the size is
given by the formula:

// calculate LRZ size from depth size:
if (nr_samples == 4) {
width *= 2;
height *= 2;
} else if (nr_samples == 2) {
height *= 2;
}

lrz_width = div_round_up(width, 8);
lrz_heigh = div_round_up(height, 8);

// calculate # of blocks:
nblocksx = div_round_up(lrz_width, 16);
nblocksy = div_round_up(lrz_height, 4);

// fast-clear buffer is 1bit/block:
fc_sz = div_round_up(nblocksx * nblocksy, 8);

In practice the blob seems to switch off FC_ENABLE once the size
increases beyond 1 page.  Not sure if that is an actual limit or
not.
 -->
 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/>
 <!-- 0x8108 invalid -->
 <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="rp_blit">
  <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
 </reg32>
 <!--
LRZ buffer represents a single array layer + mip level, and there is
a single buffer per depth image. Thus to reuse LRZ between renderpasses
it is necessary to track the depth view used in the past renderpass, which
GRAS_LRZ_VIEW_INFO is for.
GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_VIEW_INFO is equal to
the value stored in the LRZ buffer, if not - LRZ is disabled.
-->
 <reg32 offset="0x810a" name="GRAS_LRZ_VIEW_INFO" usage="cmd">
  <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>
  <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/>
  <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>
 </reg32>

 <reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit">
  <bitfield name="DISABLE_ON_WRONG_DIR" pos="0" type="boolean"/>
  <bitfield name="FC_ENABLE" pos="1" type="boolean"/>
 </reg32>

 <!-- 0x810c-0x810f invalid -->

 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/>

 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
 <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX-"/>

 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
  <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
  <bitfield name="UNK3" pos="3"/>
 </reg32>

 <!-- Always written together and always equal 09510840 00000a62 -->
 <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
 <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>

 <!-- 0x8112-0x83ff invalid -->

 <enum name="a6xx_rotation">
  <value value="0x0" name="ROTATE_0"/>
  <value value="0x1" name="ROTATE_90"/>
  <value value="0x2" name="ROTATE_180"/>
  <value value="0x3" name="ROTATE_270"/>
  <value value="0x4" name="ROTATE_HFLIP"/>
  <value value="0x5" name="ROTATE_VFLIP"/>
 </enum>

 <bitset name="a6xx_a2d_bit_cntl" inline="yes">
  <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
  <bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
  <bitfield name="UNK4" low="4" high="6"/>
  <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
  <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
  <bitfield name="SCISSOR" pos="16" type="boolean"/>
  <bitfield name="UNK17" low="17" high="18"/>
  <!-- required when blitting D24S8/D24X8 -->
  <bitfield name="D24S8" pos="19" type="boolean"/>
  <!-- some sort of channel mask, disabled channels are set to zero ? -->
  <bitfield name="MASK" low="20" high="23"/>
  <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
  <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
  <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>
 </bitset>

 <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/>
 <!-- note: the low 8 bits for src coords are valid, probably fixed point
     it would be a bit weird though, since we subtract 1 from BR coords
     apparently signed, gallium driver uses negative coords and it works?
 -->
 <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" usage="rp_blit"/>
 <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" usage="rp_blit"/>
 <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" usage="rp_blit"/>
 <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" usage="rp_blit"/>
 <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" usage="rp_blit"/>
 <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" usage="rp_blit"/>
 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
--> --------------------

--> maximum size reached

--> --------------------