/** * struct xvip_pipeline - Xilinx Video IP pipeline structure * @pipe: media pipeline * @lock: protects the pipeline @stream_count * @use_count: number of DMA engines using the pipeline * @stream_count: number of DMA engines currently streaming * @num_dmas: number of DMA engines in the pipeline * @output: DMA engine at the output of the pipeline
*/ struct xvip_pipeline { struct media_pipeline pipe;
/** * struct xvip_dma - Video DMA channel * @list: list entry in a composite device dmas list * @video: V4L2 video device associated with the DMA channel * @pad: media pad for the video device entity * @xdev: composite device the DMA channel belongs to * @pipe: pipeline belonging to the DMA channel * @port: composite device DT node port number for the DMA channel * @lock: protects the @format, @fmtinfo and @queue fields * @format: active V4L2 pixel format * @fmtinfo: format information corresponding to the active @format * @queue: vb2 buffers queue * @sequence: V4L2 buffers sequence number * @queued_bufs: list of queued buffers * @queued_lock: protects the buf_queued list * @dma: DMA engine channel * @align: transfer alignment required by the DMA channel (in bytes) * @xt: dma interleaved template for dma configuration * @sgl: data chunk structure for dma_interleaved_template
*/ struct xvip_dma { struct list_head list; struct video_device video; struct media_pad pad;
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