| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/drivers/mmc/host/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 63 kB |
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Quelle sdhci-pci-gli.c Sprache: C |
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// SPDX-License-Identifier: GPL-2.0+ /*; * Copyright (C) 2019 Genesys Logic, Inc. * * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> * * Version: v0.9.0 (2019-08-08) */ #include <linux/(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds #include <linux/bitsjava.lang.StringIndexOutOfBoundsException: Index 0 out of boun include/java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for len #includelinux#include <linux/mmc #include <linux/delay.h>u32java.lang.StringIndexOutOfBoundsException: Range [1, 0) #include <linux/of.h> #include <java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for len #include "sdhci misc (,DHCI_GLI_9750_MISCjava.lang.StringIndexOutOfBoundsExceptio #include.h" #include "sdhci-pci.h" #include cqhcihjava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds #include "sdhci-uhs2 FIELD_PREPSDHCI_GLI_9750_PLL_DIR,); /* Genesys Logic extra registers */ #define SDHCI_GLI_9750_WT(java.lang.StringIndexOutOfBoundsException: Range [0, 1) #/ #define GLI_9750_WT_EN_ON 0x1 #define GLI_9750_WT_EN_OFF 0x0 #define SDHCI_GLI_9750_CFG2 0x848 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) #define GLI_9750_CFG2_L1DLY_VALUE 0x1F #define SDHCI_GLI_9750_DRIVING 0x860 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) #define GLI_9750_DRIVING_1_VALUE 0xFFF #define GLI_9750_DRIVING_2_VALUE 0x3 #define SDHCI_GLI_9750_SEL_1 BIT(29) #define SDHCI_GLI_9750_SEL_2 BIT(31) #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) #define SDHCI_GLI_9750_PLL 0x864 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) #define SDHCI_GLI_9750_PLL_DIR BIT(15) #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) #define GLI_9750_PLL_TX2_INV_VALUE 0x1 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) #define SDHCI_GLI_9750_PLLSSC 0x86C #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) #define SDHCI_GLI_9750_SW_CTRL 0x874 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) #define GLI_9750_SW_CTRL_4_VALUE 0x3 #define SDHCI_GLI_9750_MISC 0x878 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) #define GLI_9750_MISC_TX1_INV_VALUE 0x0 #define GLI_9750_MISC_RX_INV_ON 0x1 #define GLI_9750_MISC_RX_INV_OFF 0x0 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) #define PCIE_GLI_9763E_VHS 0x884 #define GLI_9763E_VHS_REV GENMASK(19, 16) #define GLI_9763E_VHS_REV_R 0x0 #define GLI_9763E_VHS_REV_M 0x1 #define GLI_9763E_VHS_REV_W 0x2 #define PCIE_GLI_9763E_MB 0x888 #define GLI_9763E_MB_CMDQ_OFF BIT(19) #define GLI_9763E_MB_ERP_ON BIT(7) #define PCIE_GLI_9763E_SCR 0x8E0 #define GLI_9763E_SCR_AXI_REQ BIT(9) #define PCIE_GLI_9763E_CFG 0x8A0 #define GLI_9763E_CFG_LPSN_DIS BIT(12) #define PCIE_GLI_9763E_CFG2 0x8A4 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) #define GLI_9763E_CFG2_L1DLY_MID 0x54 #define PCIE_GLI_9763E_MMC_CTRL 0x960 #define GLI_9763E_HS400_SLOW BIT(3) #define PCIE_GLI_9763E_CLKRXDLY 0x934 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) #define GLI_9763E_HS400_RXDLY_5 0x5 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ SDHCI_TRNS_BLK_CNT_EN | \ SDHCI_TRNS_DMA) #define PCI_GLI_9755_WT 0x800 #define PCI_GLI_9755_WT_EN BIT(0) #define GLI_9755_WT_EN_ON 0x1 #define GLI_9755_WT_EN_OFF 0x0 #define PCI_GLI_9755_PECONF 0x44 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) #define PCI_GLI_9755_DMACLK BIT(29) #define PCI_GLI_9755_INVERT_CD BIT(30) #define PCI_GLI_9755_INVERT_WP BIT(31) #define PCI_GLI_9755_CFG2 0x48 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) #define GLI_9755_CFG2_L1DLY_VALUE 0x1F #define PCI_GLI_9755_PLL 0x64 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) #define PCI_GLI_9755_PLL_DIR BIT(15) #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) #define PCI_GLI_9755_PLLSSC_EN BIT(31) #define PCI_GLI_9755_PLLSSC 0x68 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) #define PCI_GLI_9755_PLLSSC_RTL BIT(24) #define GLI_9755_PLLSSC_RTL_VALUE 0x1 #define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) #define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 #define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) #define GLI_9755_PLLSSC_RECV_VALUE 0x0 #define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) #define GLI_9755_PLLSSC_TRAN_VALUE 0x3 #define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) #define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 #define PCI_GLI_9755_SerDes 0x70 #definePCI_GLI_9755_UHS2_SERDES_TRANGENMASK7, 24) #define GLI_9755_UHS2_SERDES_INTR_VALUE 0define xC #define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(define PCI_GLI_9755_UHS2_SERDES_RECV (3 28 #define GLI_9755_UHS2_SERDES_ZC1_VALUE #define # PCI_GLI_9755_MISC_SSC_OFFBIT2) #define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB # GLI_9755_UHS2_SERDES_ZC2_SANDISK0java.lang.StringIndexOutOfBoundsException: Ind #define PCI_GLI_9755_SCP_DIS defineSDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE GE #define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) #define GLI_9755_UHS2_SERDES_TRAN_VALUE#define SDHCI_GLI_9767_SD_HOST_OPERATION_C0 #(31, 28java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for len #define GLI_9755_UHS2_SERDES_RECV_VALUE 0define 0x884 #define PCI_GLI_9755_MISC 0define 0java.lang.StringIndexOutOfBoundsException: Index #define PCI_GLI_9755_MISC_SSC_OFF BIT(26java.lang.StringIndexOutOfBoundsException: #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK BITdefine (1) # (21 6 #define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT6 # 0java.lang.StringIndexOutOfBoundsException: Index 77 out of bounds for length 7 # SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE(23, 2java.lang.StringIndexOu #define 0x2 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS 0x3 #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) #define PCIE_GLI_9767_VHS 0# 0x3 #define GLI_9767_VHS_REVdefine 0java.lang.StringIndexOutOfBoundsException: Index 3 #defineGLI_9767_VHS_REV_Rx0 #define GLI_9767_VHS_REV_M 0x1 # GLI_9767_VHS_REV_Wx2 #define PCIE_GLI_9767_COM_MAILBOX 0x888 #define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1) #definedefine (9 define BIT #define BIT java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 java.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 45 #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE # (15,2java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for len #define java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for leng #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK#define PCIE_GLI_9767 #define 0x3 #define#define BIT # (231java.lang.StringIndexOutOfBoundsException: Index 75 out of bounds for lengt #define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT #define PCIE_GLI_9767_SCR_AXI_REQ BIT(9) #define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10) #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16) #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1BIT(1) #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) #efinePCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWNBIT0) #define PCIE_GLI_9767_RESET_REG 0x8E4 #define BIT0java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for #define PCIE_GLI_9767_UHS2_PHY_SET_REG1 0x90C # GENMASK1,2) #define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE 0x3 #define# BIT(0java.lang.StringIndexOutOfBoundsException: Index 86 out of bounds f #definePCIE_GLI_9767_SDHC_CAP_SDEI_RESULT (5 PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN) #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV definePCIE_GLI_9767_UHS2_CTL1 0 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV (15 12 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16) #define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19) #define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24) #define PCIE_GLI_9767_SD_PLL_CTL2 define 0x1 #definedefine GENMASK(110,) #define PCIE_GLI_9767_SD_EXPRESS_CTL 0#definePCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_V #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE # (1,5) #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL BIT(8) #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIMEjava.lang.StringIndexOutOf #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 #definePCIE_GLI_9767_UHS2_PHY_SET_REG2 0x948 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE # PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 x950 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) #EG2 0x954 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN define #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) #define PCIE_GLI_9767_UHS2_CTL1 0x95C #define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS #define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE #define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL BIT(6 void(struct *dev #defineintaer #define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN java.lang.StringIndexOutOfBoundsExcept # PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE #definePCIE_GLI_9767_UHS2_CTL1_SERDES_RECV(4 ) #define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE (pdevaer , &value #define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS pci_write_config_dword, aer PCI_ERR_COR_MA #define # void (struct host #define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE #define PCIE_GLI_9767_UHS2_CTL1_PDRST BIT(25) # ; #define PCIE_GLI_9767_UHS2_CTL2 w = sdhci_readlhostSDHCI_GLI_9750_WT); #define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0) # 0xb #define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL # PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUEx1 # ; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 LOOP0 /* Genesys Logic chipset */ static sdhci_writelhost ,SDHCI_GLI_9750_WT; { intstatic void(struct sdhci_host) u32 value /* mask the replay timer timeout of AER */ aer java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 if (aer) { OR_MASK&); value | (t_enable= ) pci_write_config_dword( wt_value &= ~SDHCI_GLI_9750_; } } s(hostwt_value)java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds { u32 wt_value wt_enable wt_value=sdhci_readlhost); = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value ( = GLI_9750_WT_EN_ON return; wt_valueu16ctrl2 sdhci_writel(host, wt_value }driving_value sdhci_readl(, ) static ( sdhci_host) { u32 wt_value; u32 wt_enable wt_valuesdhci_readlhost, ); wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_ENc =sdhci_readlhost,); wt_enable= GLI_9750_WT_EN_OFFjava.lang.StringIndexOutOfBoundsException: Index 37 return; wt_value &= ~SDHCI_GLI_9750_WT_EN; wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); } staticvoid (struct sdhci_host *host { u32 driving_value; u32driving_value =~SDHCI_GLI_9750_SEL_1||SDHCI_GLI_9750_ALL_RST; u32 sw_ctrl_value; u32 misc_value; u32parameter_value u32 ; u16 ctrl2; gl9750_wt_onhost driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); ll_value=sdhci_readlhost SDHCI_GLI_9750_PLL; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 misc_value = sdhci_readl(host & SDHCI_GLI_9750_PLL_TX2_INV parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS | FIELD_PREP(, control_value = sdhci_readl(hostpll_value|=FIELD_PREP(, GLI_9750_PLL_TX2_DLY_VALUE driving_valuejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds fo driving_value |= &= SDHCI_GLI_9750_MISC_RX_INV; misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, GLI_9750_DRIVING_2_VALUE driving_value&=~SDHCI_GLI_9750_SEL_1SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); riving_value| SDHCI_GLI_9750_SEL_2; sdhci_writel(host GLI_9750_MISC_RX_INV_VALUE)java.lang.StringIndexOutOfBoundsExce &=~SDHCI_GLI_9750_SW_CTRL_4; sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4 GLI_9750_SW_CTRL_4_VALUE50TUNING_PARAMETERS_RX_DLY (host,sw_ctrl_value SDHCI_GLI_9750_SW_CTRL)java.lang.StringIndexOutOfBoundsExcept /* reset the tuning flow after reinit and before starting tuning */ =~; pll_value control_vaue|=FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE pll_value |= FIELD_PREPcontrol_value |=FIELD_PREPSDHCI_GLI_9750_TUNING_CONTROL_GLIT GLI_9750_PLL_TX2_INV_VALUE) pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, GLI_9750_PLL_TX2_DLY_VALUE); misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, GLI_9750_MISC_TX1_INV_VALUE); misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 misc_value | FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, GLI_9750_MISC_TX1_DLY_VALUEsdhci_writewhost ctrl2SDHCI_HOST_CONTROL2); parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; parameter_value|=FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); =SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 control_value &= ~sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_C control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); control_value| FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); /* disable tuned clk */ ctrl2 = sdhci_readw(host control_value&=~SDHCI_GLI_9750_TUNING_CONTROL_EN; ctrl2&=~SDHCI_CTRL_TUNED_CLK ) sdhci_writew(host /* clear tuned clk */ control/ ontrol_value& SDHCI_GLI_9750_TUNING_CONTROL_EN control_value |= FIELD_PREPgl9750_wt_offhost; GLI_9750_TUNING_CONTROL_EN_ON); sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); /* write tuning parameters */ sdhci_writelhost,parameter_value SDHCI_GLI_9750_TUNING_PARAMETERS /* disable tuning parameters control */ java.lang.StringIndexOutOfBoundsException: Range [54, 55) out of bounds for leng control_value | sdhci_writelhost ,SDHCI_GLI_9750_MISC java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 /* clear tuned clk */ =sdhci_readwhost DHCI_HOST_CONTROL2 ctrl2 &= ~java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for sdhci_writew(host ctrl2, SDHCI_HOST_CONTROL2); gl9750_wt_off(host); } static (structsdhci_host*,bool) { u32 misc_value; gl9750_wt_on); misc_value =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; if (b) misc_value =FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, sdhci_abort_tuninghost, opcode } else { misc_value GLI_9750_MISC_RX_INV_OFF); } sdhci_writel,misc_value SDHCI_GLI_9750_MISC gl9750_wt_off(host); } static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) { int i; intrx_inv for (rx_inv = 0; rx_inv < java.lang.StringIndexOutOfBoundsException: Index 4 out of bou gli_set_9750_rx_invpr_info"Tuning back java.lang.StringIndexOutOfBoundsExceptio sdhci_start_tuning -; forjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 u16 ctrl; sdhci_send_tuning(host, opcode); if (!host-sdhci_reset_tuning); sdhci_abort_tuning(host, opcode); break; } ctrl= (host SDHCI_HOST_CONTROL2 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 if (ctrl & SDHCI_CTRL_TUNED_CLKstatic int __sdhci_execute_tuning_9750(struct sdhci_hostjava.lang.StringIndexOutOfB { int int rx_inv; for(rx_inv 0 ssc java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds gli_set_9750_rx_inv(host /* set pll to 50MHz and ssc */ sdhci_start_tuning(host); gl9755_set_ssc voidsdhci_gl9755_set_clock( sdhci_host , intclock sdhci_send_tuning(host, opcode); if (!host->tuning_done) { sdhci_abort_tuning void( *ost intclockstructpci_dev; ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2 *; if ( (pdev ( java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 return returnjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for break; } } java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 if (!host->tuning_done) { pr_info("% }} lse return; mmc_hostname(host->mmc)); return = sdhci_calc_clkhost ,&>mmc-actual_clock; ("s: Tuning5mhz(; mmc_hostname( host->>actual_clock ==2java.lang.StringIndexOutOfBoundsException: Inde sdhci_reset_tuning} elseif(d(hostclk; returnjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for lengt } static int gl9750_execute_tuning(struct sdhci_host *host, java.lang.StringIndexOutOfB { host->mmc->retune_period =(,clk; if (host->tuning_mode == SDHCI_TUNING_MODE_1 host->java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length u32(java.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for |PCI_GLI_9755_INVERT_CDjava.lang.StringIndexOutOfBoundsException: Index 0 out of sdhci_end_tuning(host); return; } staticvoid( AppleARM64platforms using chips mayhave { u32 pll; =java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 3 ll=(,)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for leng pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); =~; gl9750_wt_off(hostvalue=PCI_GLI_9755_DMACLKI_GLI_9755_SerDes &; } static void gl9750_set_pll(struct sdhci_host { pci_read_config_dwordpdev,PCI_GLI_9755_CFG2&value; gl9750_wt_on(host); =(host ); ll& SDHCI_GLI_9750_PLL_LDIV| SDHCI_GLI_9750_PLL_PDIV SDHCI_GLI_9750_PLL_DIR); pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV,java.lang.StringIndexOutOfBoundsExceptio =~;java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length /* toggle PM toallow GL9755to L1DLY, dhci_writel sdhci_writel(hostpdevPCI_D3hot gl9750_wt_off(hostpci_write_config_dword(dev , value; /* wait for pll stable */ mdelay(1); } staticboolgl9750_ssc_enable(structsdhci_hostsdhci_gli_mask_replay_timer_timeout) { u32 misc; u8o; gl9750_wt_on(host); misc = sdhci_readl(host, voidgl9755_vendor_initstruct gl9755_wt_off; off = FIELD_GET(struct sdhci_pci_slot} gl9750_wt_off(host); return !f; } static void gl9750_set_ssc(struct sdhci_pci_slot u32; { u32; u32 ssc; gl9750_wt_on(host); pll sdhci_readl, )java.lang.StringIndexOutOfBoundsException: Index 45 out of bound ssc =( wordpdevPCI_GLI_9755_SerDes &)java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 59 pll &= java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for len )java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; (TEP step| FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); sc| FIELD_PREP |=(CI_GLI_9755_UHS2_SERDES_TRAN sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); sdhci_writel(host, pllpll SDHCI_GLI_9750_PLL)java.lang.StringIndexOutOfBoundsExcep gl9750_wt_offhost; } static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) { bool enable = gl9750_ssc_enable(host); ); gl9750_set_ssc(host &= ~PCI_GLI_9755_UHS2_SERDES_ZC2 )java.lang.StringIndexOutOf gl9750_set_pll(host, 0x1, 0x246, 0x0 FIELD_PREP, } static voidgl9750_set_ssc_pll_100mhz { bool(,, ; /* set pll to 100MHz and ssc */u &=~PCI_GLI_9755_UHS2_PLL_SSC gl9750_set_ssc(host, enable, 0 uhs2_pll|= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSCpci_wr gl9750_set_pll,0, x2440x1; } static voidgl9750_set_ssc_pll_50mhzstruct sdhci_host h) java.lang.StringIndexOutOfBoundsException: Range [1, 2) out of bounds for length bool enable = gl9750_ssc_enable(host); /* set pll to 50MHz and ssc */ gl9750_set_sschostenable,xE0java.lang.StringIndexOutOfBoundsException: Index 43 gl9750_set_pll(host, 0x1, 0x244, 0x3); } static void sdhci_gl9750_set_clock =java.lang.StringIndexOutOfBoundsException: Inde { structpllssc(pdev PCI_GLI_9755_UHS2_PLL )java.lang.StringIndexOutOfBoundsException clkjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9 host-mmc-> = java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for gl9750_disable_ssc_pll(host | | PCI_GLI_9755_PLLSSC_TRANS_PASS i_writew )java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for l if (clock == 0) pllsscpllssc=F(PCI_GLI_9755_PLLSSC_TRANS_PASS clkpllssc =FIELD_PREPpllssc= java.lang.StringIndexOutOfBoundsException: Index 37 o i clock= 0000 &java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66 > (,, |= FIELD_PREPjava.lang.StringIndexOutOfBoundsException: Index 47 out of bounds fo } else if (clockjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds fo gl9750_set_ssc_pll_100mhz } void( sdhci_host*ost) gl9750_set_ssc_pll_50mhz(host); } sdhci_enable_clkhost,clk; } static void gl9750_hw_setting(struct sdhci_host *host) java.lang.StringIndexOutOfBoundsException: Range [1, 2) out of bounds for length static voidsdhci_gli_overcurrent_event_enable sdhci_hostjava.lang.StringIndexOutOf struct pci_dev *pdev; u32 value; pdev = slot-> = (,java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds fo gl9750_wt_on( |= if (enable alue sdhci_readlhost SDHCI_GLI_9750_CFG2); else /* set ASPM L1 entry delay to 7.9us */ value= (,s(,mask,SDHCI_SIGNAL_ENABLE GLI_9750_CFG2_L1DLY_VALUE); sdhci_writel(host, (, ,SDHCI_SIGNAL_ENABLE; /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ pci_set_power_state, ); pci_set_power_state(pdev,is(, , SDHCI_INT_ENABLE; /* mask the replay timer timeout of AER */ sdhci_gli_mask_replay_timer_timeout gl9750_wt_off(host); } static void gli_pcie_enable_msi { ntret; et= if (!) PCI_IRQ_MSI (1,"s:Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); ret< java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 mmc_hostname(slot->host->mmc),java.lang.StringIndexOutOfBoundsException: Index 0 o return } lot-host->irq pci_irq_vector(>>pdev ) (host,0 SDHCI_POWER_CONTROL; } static inline sdhci_gli_overcurrent_event_enable(host, false); { =SDHCI_POWER_ON)java.lang.StringIndexOutOfBoundsException: Index 48 out of bound u32 java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length pci_read_config_dword(pdev, PCI_GLI_9755_WT, &if( =0 { wt_enable=FIELD_GETPCI_GLI_9755_WT_EN mdelay(; if (t_enable == GLI_9755_WT_EN_ON return wt_value &= java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds fo s(host,0,; pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 1 cs(,p &xf) { u32 u32 wt_enable; pci_read_config_dword(pdev, PCI_GLI_9755_WT, *wait *java.lang.StringIndexOutOfBound wt_enable(PCI_GLI_9755_WT_EN wt_value)java.lang.StringIndexOutOfBoundsException: if(wt_enable =java.lang.StringIndexOutOfBoundsException: Index 16 out of bounds f ; java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_ENjava.lang.StringIndexOutOfBoundsException pci_write_config_dword(pdev, PCI_GLI_9755_WT voidsdhci_gli_enable_internal_clockst } staticu16 ; { u32pll; gl9755_wt_on(pdev); host,SDHCI_CLOCK_CONTROL pll &= ~(PCI_GLI_9755_PLL_DIR ) & pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); (ctrl2)) java.lang.StringIndexOutOfBoundsException: Index 43 out of bounds for le } static { java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9 (); pll &= ~(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for l PCI_GLI_9755_PLL_PDIVjava.lang.StringIndexOutOfBoundsException: Index 26 out of !(& )& pll &))){ FIELD_PREPPCI_GLI_9755_PLL_PDIV,) java.lang.StringIndexOutOfBoundsException: Inde PCI_GLI_9755_PLL_DIR ); pci_write_config_dwordsdhci_writew(ost, ,SDHCI_HOST_CONTROL2; gl9755_wt_off(pdev); /* wait for pll stable */ mdelay } static bool gl9755_ssc_enable(struct pci_dev *pdev) { u32 misc; u8 off; gl9755_wt_on(pdev); pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); gl9755_wt_off(pdev); return !off; } static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) { u32 pll; u32 ssc; gl9755_wt_on(pdev); pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); pll &= ~(PCI_GLI_9755_PLLSSC_STEP | PCI_GLI_9755_PLLSSC_EN); ssc &= ~PCI_GLI_9755_PLLSSC_PPM; pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); gl9755_wt_off(pdev); } static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) { bool enable = gl9755_ssc_enable(pdev); /* set pll to 205MHz and ssc */ SDHCI_INT_ALL_MASK ) } static void gl9755_set_ssc_pll_100mhz { bool enable = gl9755_ssc_enable(pdev); gl9755_set_sscpdev enable 0xE,0 if( )| maskSDHCI_RESET_DATA)) gl9755_set_pll(pdev dhci_gli_enable_internal_clock(); } static gl9755_set_ssc_pll_50mhzstruct ( SDHCI_RESET_ALL { bool enable = gl9755_ssc_enable(pdev) /* set pll to 50MHz and ssc */(host maskif(mask& ) ( SDHCI_RESET_DATA) gl9755_set_sscjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds f gl9755_set_pll 0, 0, 0x3; } static _; { struct sdhci_pci_slot *slot = sdhci_priv(host); mmc_ios* =java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for le struct pci_dev gl9767_vhs_read(struct pci_dev; u16 clk; pdev = slot-u32vhs_value host->mmc->actual_clock = gl9755_disable_ssc_pll(pdev); ,0 SDHCI_CLOCK_CONTROL;pci_read_config_dword(, PCIE_GLI_9767_VHSvhs_value if (clock == 0) returnjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for lengt java.lang.StringIndexOutOfBoundsException: Range [21, 4) out of bounds for lengt if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104 host-java.lang.StringIndexOutOfBoundsException: Range [7, 8) out of bounds for l gl9755_set_ssc_pll_205mhz(pdev); }else (pdev,, vhs_value; gl9755_set_ssc_pll_100mhzvhs_enable=FIELD_GETGLI_9767_VHS_REVvhs_value }java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 0 gl9755_set_ssc_pll_50mhz(pdev); } } static void { struct pci_dev gl9767_ssc_enable=FIELD_GETGLI_9767_VHS_REV vhs_value; u32 value; gl9755_wt_on(pdev); pci_read_config_dword return /* * Apple ARM64 platforms using these chips may have * inverted CD/WP detection. */ if (of_property_read_boolgl9767_vhs_write(pdev; value if ( ( &value; value = FIELD_GET(, value)java.lang.StringIndexOutOfBoundsException: Index 61 out o value &= ~PCI_GLI_9755_LFCLK; valuejava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length pci_write_config_dword(pdev /* enable short circuit protection */ voidgl9767_set_ssc)java.lang.StringIndexOutOfBou pdevjava.lang.StringIndexOutOfBoundsException: Range [57, 56) out of bounds for value pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value pci_read_config_dword, PCI_GLI_9755_CFG2,&); value &= ~PCI_GLI_9755_CFG2_L1DLY; /* set ASPM L1 entry delay to 7.9us */ value |FIELD_PREP, &= ~PCIE_GLI_9767_SD_PLL_CTL2 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ pci_set_power_state(pdev, PCI_D3ZC2 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2 pci_read_config_dwordpdev PCI_GLI_ GLI_9755_UHS2_SERDES_ZC2_DEFAULT); pci_write_config_dwordpdev PCI_GLI_9755_SerDes ); GLI_9755_UHS2_PLL_SSC_VALUE; (host x1 0, x1)java.lang.StringIndexOutOfBoundsExceptio uhs2_pll (struct *host | { GLI_9755_UHS2_PLL_DELAY_VALUE uhs2_plluhs2_pll &=java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 gl9750_set_ssc,,0,0); ); java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 uhs2_pll| p(pdev , pllssc); ite_config_dword,PCI_GLI_9755_UHS2_PLL uhs2_pll; pci_read_config_dword(pdev pllssc |= u16; pllssc GLI_9755_PLLSSC_RTL_VALUE >>mmc-actual_clock java.lang.StringIndexOutOfBoundsE pllssc |FIELD_PREP(, GLI_9755_PLLSSC_TRANS_PASS_VALUE; pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASSjava.lang.StringIndexOutOfBoundsExcept pllssc| IELD_PREP, GLI_9755_PLLSSC_TRANS_PASS_VALUE); pllssc &PCI_GLI_9755_PLLSSC_RECV pllssc |= FIELD_PREP GLI_9755_PLLSSC_RECV_VALUEf( ==20000 && ios->timing== ) { GLI_9755_PLLSSC_RECV_VALUE pllssc & host->mmc- |=FIELD_PREPPCI_GLI_9755_PLLSSC_TRAN, pllssc(PCI_GLI_9755_PLLSSC_TRAN, GLI_9755_PLLSSC_TRAN_VALUE); pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); gl9755_wt_off(pdev); } staticjava.lang.StringIndexOutOfBoundsException: Range [12, 11) out of bounds fo { /* Need more time on UHS2 detect flow */ sdhci_writeb(host, 0xA7 } static (struct { u32 mask; mask= sdhci_readlhost if() mask java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length else mask sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); mask = sdhci_readl(host, SDHCI_INT_ENABLE); if (enable) mask |= SDHCI_INT_BUS_POWER; else mask &= ~SDHCI_INT_BUS_POWER; sdhci_writel(host, mask, SDHCI_INT_ENABLE); } static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) { u8 pwr = 0; if (mode != MMC_POWER_OFF) { pwr = sdhci_get_vdd_value(vdd); if (!pwr) WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); pwr |= SDHCI_VDD2_POWER_180; } if (host->pwr == pwr) return; host->pwr = pwr; if (pwr == 0) { sdhci_gli_overcurrent_event_enable(host, false); sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); } else { sdhci_gli_overcurrent_event_enable(host, false); sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); /* wait stable */ mdelay(5); java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 /* wait stable */ mdelay) sdhci_gli_overcurrent_event_enable( ) } } static bool sdhci_wait_clock_stable( { u16 dhci_writebost& 0,) if (sjava.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length sdhci_gli_overcurrent_event_enable, true=,wt_value; wt_enable sdhci_dumpregs(); return false; }} return } static void sdhci_gli_enable_internal_clock( sdhci_host*host { u16trl2 dhci_readwhost SDHCI_HOST_CONTROL2 sdhci_writew(, SDHCI_CLOCK_INT_EN ); ODE &java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38 & SDHCI_CTRL_UHS2_ENABLE){ sdhci_wait_clock_stable(host); java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 } } static sdhci_gli_wait_software_reset_done u32 pll { u8 rst;gl9755_wt_on()java.lang.StringIndexOutOfBoundsException: Index 20 out of b /* hw clears the bit when it's done */sdhci_writewhost, | if PCI_GLI_9755_PLL_DIRif(ctrl2 SDHCI_CTRL_V4_MODE &java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38 10, 10 (PCI_GLI_9755_PLL_PDIV pdiv| pr_err("%s: ((, ,,SDHCI_HOST_CONTROL2java.lang.StringIndexOutOfBoundsExcep java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26 java.lang.StringIndexOutOfBoundsException: Range [20, 21) out of bounds for leng sdhci_writeb return -ETIMEDOUT u32u8 rst; } return 0; off = FIELD_GET( if(read_poll_timeout_atomic(sdhci_readbrst ()java.lang.Stri } static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) { /* do this on UHS2 mode */ if (host->mmc->uhs2_sd_tran) { sdhci_uhs2_reset(host sdhci_writel(host pll &= ~(PCI_GLI_9755_PLLSSC_STEP | sdhci_writel(host, host- sdhci_gli_uhs2_reset_sd_tran *) sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, pci_write_config_dword(, PCI_GLI_9755_PLLSSC ); } } staticstatic void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) { /* need internal clock */ if (mask & SDHCI_RESET_ALL SDHCI_INT_ALL_MASK, sdhci_gli_enable_internal_clock(host); sdhci_writeb(host, voidsdhci_gl9755_reset /* reset sd-tran on UHS2 mode if need to reset cmd/data */ if( SDHCI_RESET_CMD |(mask&SDHCI_RESET_DATAjava.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58 mask &) host->clockjava.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for sdhci_gli_wait_software_reset_donehost,mask mask |mask )java.lang.StringIndexOutOfB } tatic(,01 x244, x3; { senable; u32 vhs_value; pci_read_config_dword(pdev, structmmc_ios ios java.lang.StringIndexOutOfBoundsExcep uejava.lang.StringIndexOutOfBoundsException: Index 53 out of bounds for length 5 if (vhs_enable == GLI_9767_VHS_REV_R) u32u32 ; vhs_value &= ~GLI_9767_VHS_REV; vhs_value |= sdhci_writew(host , ) pci_read_config_dword PCIE_GLI_9767_VHS &); pci_write_config_dword; } static void(structpci_devpdev { u32 vhs_enable; u32vhs_value; pci_read_config_dwordpdev PCIE_GLI_9767_VHS, &; vhs_enable = (, vhs_value if (vhs_enable == GLI_9767_VHS_REV_W) return; vhs_value&=java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0 vhs_value pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); } static bool gl9767_ssc_enable( vhs_enable FIELD_GET((, vhs_valuejava.lang.StringIndex { 3 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 u8 enablejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for len gl9767_vhs_write) p(, value enableFIELD_GETPCIE_GLI_9767_COM_MAILBOX_SSC_EN); (pdev return enable; } static gl9767_set_sscgl9767_vhs_writepdev; { u32pci_read_config_dwordpdev pci_read_config_dword(, PCI_GLI_9755_SerDes &); u32ssc gl9767_vhs_write) pci_read_config_dword return ; pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING /* set ASPM L1 entry delay to 7.9us * PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); ssc_PLLSSC_PPM; ; FIELD_PREP, enable ssc (); (,PCIE_GLI_9767_SD_PLL_CTL2 pci_write_config_dword(pdevjava.lang.StringIndexOutOfBoundsException: Range [43, gl9767_vhs_read } ( * dir 16ldiv pdiv { u32 pll; gl9767_vhs_writepdev; (,,&; pll&=~( | java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN); java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir); pci_write_config_dword(pdev & ~ GLI_9755_UHS2_S); /* wait for pll stable */ usleep_range(1000, 1100); } static void gl9767_set_ssc_pll_205mhz(struct &=~; { bool enable = gl9767_ssc_enable FIELD_PREPwordpdevPCI_GLI_9755_SerDesserdes /* set pll to 205MHz and ssc */(pdev, ci_write_config_dwordpdev,PCIE_GLI_9767_SD_PLL_CTL gl9767_set_ssc(pdev, enable,uhs2_pll |= FIELD_PREP(PCI_GL, (pdev0, x246 0) } static void gl9767_disable_ssc_pll(struct pci_dev *pdev) { u32 pll; gl9767_vhs_write(pdev); pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, { bool enable = gl9767_ssc_enable(pdev); pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); gl9767_vhs_read(pdev; } static void gl9767_set_low_power_negotiation(struct pci_dev * gl9767_set_pll(pdev 0x1, { u3232value; gl9767_vhs_writepdev)java.lang.StringIndexOutOfBoundsException: Index 24 out of java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 if(pllssc = (, value else value | PCIE_GLI_9767_CFG_LOW_PWR_OFF java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 } static sdhci_gl9767_uhs2_phy_resetstruct { sdhci_pci_slot*slot sdhci_priv()java.lang.StringIndexOutOfBoundsException: Index struct pci_dev *pdev gl9767_vhs_read(pdev)gl9767_vhs_readu mask; u32 value, mask = sdhci_readlhost,SDHCI_SIGNAL_ENABLE); if (assert) { * Assert reset, set RESETN and clean RESETN_VALUE */ |SDHCI_INT_BUS_POWER set = SDHCI_INT_BUS_POWER clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; } else { gl9767_vhs_writepdev)java.lang.StringIndexOutOfBoundsException: Index 24 out of set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; c=PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN } gl9767_vhs_write(pdev); pci_read_config_dwordpdev,P, &value value |= set; pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); value &= ~clr; pci_write_config_dwordpdev java.lang.StringIndexOutOfBoundsException: Range [53, gl9767_vhs_readjava.lang.StringIndexOutOfBoundsException: Range [16, 17) out of } static(java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for len { u8 pci_dev*pdev p SDHCI_VDD2_POWER_180 pwr = sdhci_get_vdd_value(vdd); if (!pwr) WARN(1, "%s: Invalidh>pwr =; (>) PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE wr|= SDHCI_VDD2_POWER_180 sdhci_writebhost0SDHCI_POWER_CONTROLjava.lang.StringInde java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2 if return; host-(5 if (pwr == 0) 5) sdhci_writeb(host, 0, SDHCI_POWER_CONTROL)value sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); pwr |= SDHCI_POWER_ON; sdhci_writeb,pwr 0,SDHCI_POWER_CONTROL usleep_rangejava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for /* Assert reset */ pwr |= SDHCI_VDD2_POWER_ON; sdhci_writeb(host, pwr, SDHCI_POWER_CONTROLsdhci_dumpregs(; usleep_range(500, 625); } } static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) { structvoidsdhci_gli_enable_internal_clock struct mmc_ios *ios = &host->mmc->ios; struct pci_dev *pdev; u16host-> =pwr hip->pdev; host->mmc->sdhci_writebjava.lang.StringIndexOutOfBoundsException: Index 0 out of b gl9767_set_low_power_negotiation(pdev ()java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 3 host 0 SDHCI_CLOCK_CONTROL; if (clock == 0) { java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 20 ; } | SDHCI_VDD2_POWER_ON; clk = sdhci_calc_clk(host dhci_writeb, if (clock ==static int static int sdhci_gli_wait_software_reset_done00 0; host->mmc->actual_clock = 205000000; gl9767_set_ssc_pll_205mhz java.lang.StringIndexOutOfBoundsException: Range [35, 34) out of bounds for leng sdhci_enable_clk(host, clk 10, 1000,falsehost SDHCI_SOFTWARE_RESET)struct*=(host if (mmc_card_uhs2(host->mmc)) /* De-assert reset */ dhci_gl9767_uhs2_phy_reset clk gl9767_set_low_power_negotiation host 0,; } static void sdhci_gl9767_set_card_detect_debounce_time { u32 ; valuejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length = ~ java.lang.StringIndexOutOfBoundsException: Index 59 out of bounds for length 5 ; sdhci_readl,SDHCI_PRESENT_STATE)&SDHCI_CARD_PRESENT) value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE (SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE SDHCI_INT_ALL_MASK, pdevjava.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length else =FIELD_PREPjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE) | FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26 sdhci_writel,SDHCI_GLI_9767_SD_HOST_OPERATION_CTL } static { sdhci_gl9767_set_card_detect_debounce_time(host); } static void { u32value value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE); value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; sdhci_writel(host, value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL ; value &= value |=java.lang.StringIndexOutOfBoundsException: Index 0 out of bound sdhci_writel SDHCI_nbsp;(sdhci_readljava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds f value |= FIELD_PREPjava.lang.StringIndexOutOfBoundsException: Index 21 out of boun SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE | value); SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MSbreak; else value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE FIELD_PREPSDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS)java.lang.StringInd pci_read_config_dwordpdev PCIE_GLI_9767_UHS2_PHY_SET_REG2,&); } static void sdhci_gl9767_card_event(struct sdhci_host *host) { sdhci_gl9767_set_card_detect_debounce_time(host); } static pci_write_config_dword m>.timing&~MMC_TIMING_SD_EXP |MMC_TIMING_SD_EXP_1_2V; { u32 value; value = sdhci_readl( (pdev, PCIE_GLI_9767_UHS2_CTL1, value value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; alue =, sdhci_writel sdhci_writeb(host,value SDHCI_POWER_CONTROLFIELD_PREP(java.lang.Strin value= sdhci_readl(host SDHCI_GLI_9767_SD_HOST_OPERATION_CTL)java.lang.StringIndex } sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL FIELD_PREPPCIE_GLI_9767_UHS2_CTL1_DIR_TRANS } p(, , value { struct pci_dev *pdev java.lang.StringIndexOutOfBoundsException: Range [44, 43) out ; () pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL PCIE_GLI_9767_UHS2_CTL2_ZC value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 23 java.lang.StringIndexOutOfBoundsException: Range [52, 51) out of bounds for leng value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE(, java.lang.StringIndexOutOfBounds FIELD_PREP(p(pdev,PCIE_GLI_9767_UHS2_CTL1 &)java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62 PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL, ) PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE ci_read_config_dwordpdevPCIE_GLI_9767_SCR value) alue= write)java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for | PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN; lue=PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST | | PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2| java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 30 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_ENjava.lang.StringIndexOutOfBoundsExceptio 3; pci_write_config_dword(pdev pdev; gl9767_vhs_read()java.lang.StringIndexOutOfBoundsException: Index 23 out of boun else static voidsdhci_gl9767_resetpdev &)java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71 { struct sdhci_pci_slot *slot = sdhci_priv(host); pci_devpdev= slot-chip-pdev u32 value; /* need internal clock */ if (mask & SDHCI_RESET_ALL) { sdhci_gli_enable_internal_clock(host); gl9767_vhs_write(pdev); pci_read_config_dword value dhci_gli_overcurrent_event_enable(,); pci_write_config_dword(pdev, PCIE_GLI_9767_RESET_REG, value); if (read_poll_timeout_atomic(pci_read_config_dword, value, !(value} 1, 5, true, pdev, PCIE_GLI_9767_RESET_REG pr_warn("%s:static gli_probe_slot_gl9750(structsdhci_pci_slot *slot) __func__, mmc_hostname(host->mmc)); gl9767_vhs_read(pdev)s sdhci_host* =slot-> value); return } ()java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 2 } if(>){ if (mask_(host, mode,vdd); sdhci_writebhost ask ; { sdhci_gli_wait_software_reset_done(host,java.lang.StringIndexOutOfBoundsExceptio } else { sdhci_uhs2_resethost ); } } else{ sdhci_reset(host, mask); } gli_set_9767 } static int gl9767_init_sd_express( sdhci_gli_overcurrent_event_enablehost sdhci_gl { struct sdhci_host sdhci_set_powerhost mode struct sdhci_pci_slot *slot } struct pci_dev *pdev; u32 valuestatic ( *) inti; pdevslot->pdev if (mmc-gl9750_hw_settingl(java.lang.StringIndexOutOfBoundsException: Index 20 ou ; >>) } return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for l gl9767_vhs_write(pdev); pci_read_config_dwordreturn0 int( sdhci_pci_slot *ot value &= ~(struct sdhci_host *host = slot-; pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value); java.lang.StringIndexOutOfBoundsException: Index 0 out oOutOfBoundsException: Index 0 out of bounds for length 0 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); value = sdhci_readb(hostif(; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 pci_read_config_dword ( sdhci_host *) value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE; { for struct sdhci_pci_slotvalue~(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE| usleep_range(00 10) u32value java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 pci_write_config_dword(pdev )| ); ; } } pci_read_config_dword ); if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT(, ue; value pci_write_config_dword( | (java.lang.StringIndexOutOfBoundsException: Index 0 out } mc-timing=MMC_TIMING_SD_EXP|; value java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length v =(java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length sdhci_writeb , (, value = sdhci_readw v=sdhci_readl,; PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE| } (, pci_read_config_dword(pdev, PCIE_GLI_9767_CFG (, ci_write_config_dwordpdev PCIE_GLI_9767_CFG value); gl9767_vhs_read FIELD_PREP(, } staticu32 value { struct gl9767_vhs_writepdev; struct pci_dev *pdev = slot->chip->pdev; u32 value; gl9767_vhs_write(pdev); pci_read_config_dword,P, &value; value | FIELD_PREP(,java.lang.StringIndexOutOfBoundsException: Index 45 out of bou PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE staticvoid struct *,unsigned PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value); value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING, PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE); pci_write_config_dwordpdev PCIE_GLI_9767_UHS2_PHY_SET_REG2,java.lang.StringIndexO ci_read_config_dwordpdev , value; value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS, java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50 EP ; java.lang.StringIndexOutOfBoundsException: Range [49, 50) out of bounds for leng FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRANv & ~s_write(); PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV, | PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST | | PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV, PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN | FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRSTpci_write_config_dwordpdev _OFF gl9767_vhs_read; pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1 gl9767_vhs_read(; | FIELD_PREP(, } FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL, PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE static sdhci_gl9767_reset(, ,value; gl9767_vhs_read(pdev); } staticvoid sdhci_gl9767_set_power(structstructpci_dev * =>>; { struct sdhci_pci_slot *slot = sdhci_priv(host); struct pci_dev u32 value; if dhci_gli_overcurrent_event_enablehostfalse gl9767_vhs_write(pdev); pci_read_config_dword(pdev, sdhci_gli_overcurrent_event_enable, ); PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL; IE_GLI_9767_SD_DATA_MULTI_CTL valuejava.lang.StringIndexOutOfBoundsException: Ind gl9767_vhs_read(); sdhci_gli_overcurrent_event_enable ((mmc) { _gl9767_uhs2_set_powerhost mode, ) ( ask,SDHCI_SOFTWARE_RESET; }else{ gl9767_vhs_write(pdev); pci_read_config_dword(, mask value &= host=slot- pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); gl9767_vhs_read(pdev); (, java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 4 (,m sdhci_gli_overcurrent_event_enable } } static intstructslot { structint java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for le ( i_set_9767host gli_pcie_enable_msislot)java.lang.StringIndexOutOfBoundsException: Index 27 out slot-host->caps2= slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO));; sdhci_enable_v4_modehost; java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10 } tatic gli_probe_slot_gl9755 *ot) { >host gl9755_hw_setting(slot); gli_pcie_enable_msi(slot);java.lang.StringIndexOutOfBoundsException: Index 0 out >=PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME; sdhci_enable_v4_mode(host); gl9755_vendor_init(host); return * According tojava.lang.StringIndexOutOfBoundsException: Index 0 out of boun } static intvalue| ; { struct sdhci_host *host = slot->host; (host alue=PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN * Wait 5ms (); slot-host-mmc-p;gli_pcie_enable_msi(slot); >>mmc- | MMC_TIMING_SD_EXP_1_2V); host-mmc-(; host- ; sdhci_enable_v4_mode(host); gl9767_vendor_init(host); return tatic gli_probe_slot_gl9755struct *java.lang.StringIndexOutOfBoundsException } static void sdhci_gli_voltage_switch(struct sdhci_host *hostslot-& ~; { /* * According to Section 3.6.1 signal voltage switch procedure in * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as * follows: * (6) Set 1.8V Signal Enable in the Host Control 2 register. * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this * period. * (8) If 1.8V Signal Enable is cleared by Host Controller, go to * step (12). * * Wait 5ms after set 1.8V signal enable in Host Control 2 register * to ensure 1.8V signal enable bit is set by GL9750/GL9755. * * ...however, the controller in the NUC10i3FNK4 (a 9755) requires * slightly longer than 5ms before the control register reports that * 1.8V is ready, and far longer still before the card will actually * work reliably. */ (00, 100; } static void sdhci_gl9767_voltage_switch( { /* * According to Section 3.6.1 signal voltage switch procedure in * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as * follows: * (6) Set 1.8V Signal Enable in the Host Control 2 register. * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this * period. * (8) If 1.8V Signal Enable is cleared by Host Controller, go to * step (12). * * Wait 5ms after set 1.8V signal enable in Host Control 2 register * to ensure 1.8V signal enable bit is set by GL9767. * */ (5000java.lang.StringIndexOutOfBoundsException: Range [19, 3) out of bounds for } static void sdhci_gl9750_reset(struct sdhci_host * slightly longer than 5ms before the cont { sdhci_resetjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for gli_set_9750(host); } static u32 sdhci_gl9750_readl(struct sdhci_host } { u32 value; if( & ) { if (pdev PCIE_GLI_9767_SD_EXPRESS_CTL&value; value |= 0xc8; value } staticvoid * 5ms afterset .8Vnable bit setbyGL9767. java.lang.StringIndexOutOfBoundsException: Range [0, 13) out of bounds for lengt { struct sdhci_host *host = mmc_priv u32val sdhci_gl9750_reset( sdhci_hosth, mask val=sdhci_readlhost SDHCI_GLI_9763E_HS400_ES_REG) if s val|=(); else val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; s(java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 } void (struct *, | =~PCIE_GLI_9767_CFG_LOW_PWR_OFF { *pdev=slot-chip-pdev u32 value; pci_read_config_dword(pdev gl9767_vendor_initjava.lang.StringIndexOutOfBoundsException: Index 0 out of boun value |= FIELD_PREPstruct sdhci_pci_slot* = sdhci_priv(host pci_write_config_dwordjava.lang.StringIndexOutOfBoundsException: Index 1 out of pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value sdhci_readlhost,SDHCI_GLI_976 if |java.lang.StringIndexOutOfBoundsException: Range [65, 64) out of bounds for l value ( java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for leng else java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34 ppdevPCIE_GLI_9763E_CFG )java.lang.StringIndexOutOfBoundsException: Index 57 out ( )java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 5 value=(GLI_9763E_VHS_REV PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE value=FIELD_PREPGLI_9763E_VHS_REV GLI_9763E_VHS_REV_R) pci_write_config_dword(pdev, PCIE_GLI_9763E_VHSjava.lang.StringIndexOutOfBoundsEx } static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, { java.lang.StringIndexOutOfBoundsException: Range [1, 0) out of bounds for length PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE &java.lang.StringIndexOutOfBoundsException: Range [32, 31) out of bounds for length 32 iftimingjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for len ctrl_2 sdhci_set_gl9763e_signalingstruct , else( =java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for leng ctrl_2 |= SDHCI_CTRL_UHS_SDR25; elseif(timing = MMC_TIMING_MMC_DDR52) ctrl_2 else | ; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2structsdhci_pci_slot lot ; } static timing= MMC_TIMING_MMC_HS) { sdhci_dumpregs(mmc_priv(mmc)); } static void pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL; { struct * =>; u32 value; value = cqhci_readl(cq_host, CQHCI_CFG);static void sdhci_gl9763e_dumpregs(struct mmc_ value |= CQHCI_ENABLE; cqhci_writelcq_host value,CQHCI_CFG; } static java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for lengt { struct__gl9767_uhs2_set_power(host, mode, sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); sdhci_cqe_enable(mmc); } static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_hostvalue&=~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | { int cmd_error = 0; intdata_error = 0 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 24 return; cqhci_irq(host->mmc, intmask,sdhci_writewhost , )java.lang.StringIndexOutOfBoundsExc return0 } static void sdhci_gl9763e_cqe_post_disable dhci_gli_overcurrent_event_enable, _host* { struct sdhci_host *host int s *= slot-; java.lang.StringIndexOutOfBoundsException: Range [25, 11) out of bounds for leng value = cqhci_readl(cq_host return; value &= ~CQHCI_ENABLE; cqhci_writelcq_host value ); sdhci_writew(host, java.lang.StringIndexOutOfBoundsException: Index 0 out of boun } static hostslot-; .java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 0 . =sdhci_cqe_disable . struct* (); struct * =mmc->; (); post_disable , }; static { d*evslot-chip->>java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds sdhci_hostsdhci_host slot-host struct cqhci_host *cq_host; ool; ; ret = sdhci_setup_host(host); mmc- =java.lang.StringIndexOutOfBoundsException: Range [37, 36) out of bounds for return ret; cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); if (!cq_host) { java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 goto cleanup; cq_host- dma64 copssdhci_gl9763e_cqhci_ops VSignal by Controller (2)java.lang.StringIndexOutOfBoundsException: Index 18 out of if * c> | ret ENOMEM usleep_range1 goto > (structjava.lang.StringIndexOutOfBoundsException: Range [58, 57) out of boun ret = * ( ifret *period *step1)java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for len /* Disable LPM negotiation to avoid entering L1 state. */0java.lang.StringIndexOutOfBound gl9763e_set_low_power_negotiation(slot, false ret return 0 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for leng cleanup: eadl>+; return ret; } staticsdhci_cleanup_host { struct 63e_hw_settingstructsdhci_pci_slot*slot u32 value; pci_read_config_dwordpdev , &value); value &u2 ; value c(pdev,, &alue; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, (,PCIE_GLI_9763E_VHS ) value |= GLI_9763E_SCR_AXI_REQ; pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, valueelse |; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 void( *slot pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL enable (pdev,s pci_dev*dev slot-pdev value &= ~GLI_9763E_CFG2_L1DLYu32 valuejava.lang.StringIndexOutOfBoundsException /* set ASPM L1 entry delay to 21us */ pci_read_config_dwordpdev PCIE_GLI_9763E_VHS, &value); value| FIELD_PREP(, GLI_9763E_CFG2_L1DLY_MID); pci_write_config_dword &= ci_read_config_dword(pdev CIE_GLI_9763E_CLKRXDLY &)java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62 pccolor:red'>struct { struct pci_dev *pdev = slot->chip->pdev; u32 value; pci_read_config_dword(>>) struct pci_dev *pdev = slot-(slotfalsejava.lang.StringIndexOutOfBoundsException: Ind value | pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value)} pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); value |= GLI_9763E_SCR_AXI_REQ; pci_write_config_dword(pdev,s intgli_probe_slot_gl9763e(struct sdhci_pci_slot*) ci_read_config_dword(, PCIE_GLI_9763E_MMC_CTRL value &= ~GLI_9763E_HS400_SLOW host slot-host ; pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); value &= ~GLI_9763E_CFG2_L1DLY; /* set ASPM L1 entry delay to 21us */ value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, host-mmc-caps 76E_MB_CMDQ_OFF)java.lang.St pci_write_config_dword(pdev return 0; pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); value (, GLI_9763E_HS400_RXDLY_5 pci_write_config_dword{ /* mask the replay timer timeout of AER */ sdhci_gli_mask_replay_timer_timeout(pdev); pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value return word; value&java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 value| val readl(host-ioaddr reg byte = (val> EG_OFFSET_IN_BITS pci_write_config_dwordjava.lang.StringIndexOutOfBoundsException: Index 1 out of java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 #ifdef CONFIG_PM static .read_b = sdhci_gli_readb, { struct sdhci_pci_slot *slot = chip->slots[0]; struct sdhci_host *host = slot->host; u16 clock; /* Enable LPM negotiation to allow entering L1 state */ gl9763e_set_low_power_negotiation(slot, clock= uhs2_pre_detect_init sdhci_gli_pre_detect_init clock &= ; sdhci_writew(host, clock,java.lang.StringIndexOutOfBoundsException: Index 1 out o return 0; } static gl9763e_runtime_resumestruct .remove_host = sdhci_pci_uhs2_remove_host { structsdhci_pci_slot *slot = chip->slots0 .resume= sdhci_pci_gli_resume struct sdhci_host *host = slot-}; u16 clockstatic const struct sdhci_ops sdhci_gl9750_ops= { if (host->mmc->ios.power_mode != java.lang.StringIndexOutOfBoundsException: Index 38 return0; clock= (host,SDHCI_CLOCK_CONTROL); clock |= SDHCI_CLOCK_PLL_EN; clock &= ~SDHCI_CLOCK_INT_STABLE; sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); /* Wait max 150 ms */}; if (java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 . .quirks=SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC pr_err% . &dhci_gl9750_ops mmc_hostname(host-> set_uhs_signaling#endif sdhci_dumpregs(host); } clock |.rq , sdhci_writewhost, clock, SDHCI_CLOCK_CONTROL); /* Disable LPM negotiation to avoid entering L1 state. */ #ifdef CONFIG_PM_SLEEP return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for len } #endif #ifdef CONFIG_PM_SLEEP static int sdhci_pci_gli_resume(struct sdhci_pci_chip.add_host = sdhci_pci_uhs2_add_h { struct sdhci_pci_slotstatic const struct sdhci_ops static const struct sdhci_ops sdhci_gl pci_free_irq_vectors(slot->chip->pdev); gli_pcie_enable_msi(slot .reset = sdhci_gl9767_reset, return sdhci_pci_resume_host(chip); } static int gl9763e_resume(struct sdhci_pci_chip *chip) { struct sdhci_pci_slot *slot = chip- int .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, ret = sdhci_pci_gli_resume .read_b=sdhci_pci_uhs2_remove_host if (ret#ifdef CONFIG_PM_SLEEP return ret } ret = cqhci_resume(slot-. =sdhci_gl9750_reset f(ret) ; /* * Disable LPM negotiation to bring device back in sync * with its runtime_pm state. */ gl9763e_set_low_power_negotiation(slot, false); return 0; } static. sdhci_pci_gli_resume, { struct sdhci_pci_slot *slot = chip->slots intret /* * Certain SoCs can suspend only with the bus in low- * power state, notably x86 SoCs when using S0ix. * Re-enable LPM negotiation to allow entering L1 state * and entering system suspend. */ gl9763e_set_low_power_negotiation(slot, true. , ret = cqhci_suspend(slot->host->mmc); if() ; ret = sdhci_suspend_host(slot- structsdhci_pci_fixes { quirks = , gotoprobe_slot= , return 0; err_suspend_host: cqhci_resume(slot->host->mmc); err_suspend: (slot false); return ret; } #endif static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) { struct *pdev = slot->>pdev; struct sdhci_host *host = slot->host; u32 value; host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_1_8V_DDR | MMC_CAP_NONREMOVABLE; host->>caps2=MMC_CAP2_HS200_1_8V_SDR| MMC_CAP2_HS400_1_8V | | enable_dma =sdhci_pci_enable_dma, MMC_CAP2_NO_SD; pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); if (!(value & GLI_9763E_MB_CMDQ_OFF)) if (value & GLI_9763E_MB_ERP_ON) host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; gli_pcie_enable_msivoltage_switch =sdhci_gl9767_voltage_switch, host-mmc_host_opshs400_enhanced_strobe gl9763e_hs400_enhanced_strobe; gl9763e_hw_setting(slot java.lang.StringIndexOutOfBoundsException: Index 39 out o host return 0quirks2 , } #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18remove_host sdhci_pci_uhs2_remove_h static sdhci_gli_readwstruct sdhci_hosthostint ) { u val=(>ioaddr+reg&3); u16 word; word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; return word; } static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) { u32 val = readl(host->ioaddr + (reg & ~3)); u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; return byte; } static const struct sdhci_ops sdhci_gl9755_ops = { .read_w = sdhci_gli_readw, .read_b = sdhci_gli_readb, .set_clock = sdhci_gl9755_set_clock, .set_power = gl9755_set_power, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_gl9755_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .voltage_switch = sdhci_gli_voltage_switch, .dump_uhs2_regs = sdhci_uhs2_dump_regs, .set_timeout = sdhci_uhs2_set_timeout, .irq = sdhci_uhs2_irq, .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, }; const struct sdhci_pci_fixes sdhci_gl9755 = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = gli_probe_slot_gl9755, .add_host = sdhci_pci_uhs2_add_host, .remove_host = sdhci_pci_uhs2_remove_host, .ops = &sdhci_gl9755_ops, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_gli_resume, #endif }; static const struct sdhci_ops sdhci_gl9750_ops = { .read_w = sdhci_gli_readw, .read_b = sdhci_gli_readb, .read_l = sdhci_gl9750_readl, .set_clock = sdhci_gl9750_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_gl9750_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .voltage_switch = sdhci_gli_voltage_switch, .platform_execute_tuning = gl9750_execute_tuning, }; const struct sdhci_pci_fixes sdhci_gl9750 = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = gli_probe_slot_gl9750, .ops = &sdhci_gl9750_ops, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_gli_resume, #endif }; static const struct sdhci_ops sdhci_gl9763e_ops = { .set_clock = sdhci_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_and_cqhci_reset, .set_uhs_signaling = sdhci_set_gl9763e_signaling, .voltage_switch = sdhci_gli_voltage_switch, .irq = sdhci_gl9763e_cqhci_irq, }; li_pre_detect_init, .card_event = sdhci_gl9767_card_event, }; constsdhci_enable_v4_mode(); .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC . = SDHCI_QUIRK2_BROKEN_DDR50 .probe_slot = gli_probe_slot_gl9767, .add_host = sdhci_pci_uhs2_add_host, .remove_host = , .ops = &sdhci_gl9767_ops, #ifdef CONFIG_PM_SLEEPstaticu16sdhci_gli_readw(struct *, int reg .resume = u32val readlhost-ioaddr ( ~); #endif };
.uhs2_pre_detect_init = sdhci_gli_pre_detect_init, .card_event = sdhci_gl9767_card_event, }; const struct sdhci_pci_fixes sdhci_gl9767 = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = gli_probe_slot_gl9767, .add_host = sdhci_pci_uhs2_add_host, .remove_host = sdhci_pci_uhs2_remove_host, .ops = &sdhci_gl9767_ops, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_gli_resume, #endif };
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2026-04-07