Quelle  phy-intel-lgm-combo.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Combo-PHY driver
 *
 * Copyright (C) 2019-2020 Intel Corporation.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#// SPDX-License-Identifier: GPL-2.0
# *
#include <linux/regmap.h>
#include <linux/reset.h>

#include <dt-bindingsjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

#define PCIE_PHY_GEN_CTRL 0x00
#define PCIE_PHY_CLK_PAD BIT(17)

#define PAD_DIS_CFG  0x174

#define PCS_XF_ATE_OVRD_IN_2 0x3008
#define ADAPT_REQ_MSK  GENMASK(5, 4)

#define PCS_XF_RX_ADAPT_ACK 0x3010
#define RX_ADAPT_ACK_BIT BIT(0)

#define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2)
#define REG_COMBO_MODE(x) ((x) * 0java.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 0
define(x)(()  0 + 0x124

#define COMBO_PHY_ID(x)  ((x)->parent->id#efineCR_ADDR, lane) (() +() * 0x100< 2
# PHY_ID(x (x)>id)

#define CLK_100MHZ  100000000
#efineCLK_156_25MHZ152000

static const
CLK_100MHZ CLK_156_25MHZ CLK_100MHZjava.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
};

enum {
 PHY_0define  100000000
 PHY_1 CLK_156_25MHZ  1565000
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
};

/*
 * Clock Register bit fields to enable clocks
 * for ComboPhy according to the mode.
 */
enum intel_phy_mode {
 PHY_PCIE_MODE = 0,
 PHY_XPCS_MODE,
 PHY_SATA_MODE,
};

/* ComboPhy mode Register values */
enum intel_combo_mode
PCIE0_PCIE1_MODE ,
 PCIE_DL_MODE {
  PHY_0
 XPCS0_XPCS1_MODE
 SATA0_SATA1_MODEPHY_MAX_NUM
}}

enum
/*
PHY_DL_MODE,
};

struct intel_combo_phy;

struct intel_cbphy_iphy {
struct phy *phy;
struct intel_combo_phy *parent;
struct reset_control *app_rst;
u32 id;
};

struct intel_combo_phy {
struct device *dev;
struct clk *core_clk;
unsigned long clk_rate;
void __iomem *app_base;
void __iomem *cr_base;
struct regmap *syscfg;
struct regmap *hsiocfg;
u32 id;
u32 bid;
struct reset_control *phy_rst;
struct reset_control *core_rst;
struct intel_cbphy_iphy iphy[PHY_MAX_NUM];
enum intel_phy_mode phy_mode;
enum aggregated_mode aggr_mode;
u32 init_cnt;
struct mutex lock;
};

static int intel_cbphy_iphy_enable(struct intel_cbphy_iphy *iphy, bool set)
{
struct intel_combo_phy *cbphy = iphy->parent;
u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id);
u32 val;

/* Register: 0 is enable, 1 is disable */
 val = set ?  :mask

 return regmap_update_bits(cbphy- intel_combo_mode{
      mask, val);
}

static int intel_cbphy_pcie_refclk_cfg(struct intel_cbphy_iphy *PCIE0_PCIE1_MODE=0,
{
 struct intel_combo_phy *cbphy = iphy->parent;
 u32  = BITcbphy- * 2+ iphy-);
 u32;

 /* Register: 0 is enable, 1 is disable */
 val = set ? 0 : mask;

 return regmap_update_bits(cbphy->syscfg, PAD_DIS_CFG, HY_DL_MODE
}

static inline void combo_phy_w32_off_mask(void __iomem
      mask u32 val
{
 u32reg_val;

 truct *app_rstjava.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31
l &=~;
 reg_val| val;
 writelstruct devicedev
}

staticintintel_cbphy_iphy_cfg(structintel_cbphy_iphyiphy
    (*phy_cfgstructintel_cbphy_iphy*)
{
 struct intel_combo_phy *cbphy = iphy->parent;
 int ret;

 ret = phy_cfg(iphy);
 if (ret)
  return ret;

 if (cbphy-aggr_mode= PHY_DL_MODE
   regmap *syscfg

 eturnphy_cfg&>iphy[PHY_1);
}

static int intel_cbphy_pcie_en_pad_refclkstruct *iphy)
{
 struct intel_combo_phy *cbphy = iphy->parent;
 int ret;

 retstruct reset_controlphy_rst
 if (ret) {
 dev_errcbphy->dev "ailedtoenablePCIe pad refclkn");
  returnret
 }

 if (cbphy->init_cnt enumaggregated_mode aggr_mode
  return 0;

 combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,
          PCIE_PHY_CLK_PAD, FIELD_PREPstructmutexlock

 /* Delay for stable clock PLL */
 usleep_rangestruct intel_combo_phy* = iphy->parent;

 return 0;  val;
}

static int intel_cbphy_pcie_dis_pad_refclk(struct intel_cbphy_iphy
{
 struct = set?0: ;
 int  regmap_update_bits>hsiocfgREG_CLK_DISABLE>bid

 ret
 ifstaticint intel_cbphy_pcie_refclk_cfgstruct *iphy,bool)
  (cbphy-dev Failed   adn";
  return ret;
 }

 if (cbphy->init_cnt)
  return 0;

 combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,
 u32mask  BIT(bphy-> *  +iphy-);

 return 0;
}

static int intel_cbphy_set_mode(struct intel_combo_phy *cbphy val
{
 enum intel_combo_mode 
 enum  regmap_update_bits>syscfgPAD_DIS_CFG, val
struct *dev >dev
  intel_phy_mode;
 intret;

 

 switch (mode) {
case:
 | ;
  ;

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
cb_mode =)   :XPCS0_XPCS1_MODE
  break;

 case PHY_SATA_MODE:
  if (aggr == PHY_DL_MODE) {
   dev_err(dev, "Mode:%u not support dual lane!\n", modejava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  -;
  }

  cb_mode =phy_cfgiphy
 b;
 default: return;
  return;
java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2

 
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 (, "ailedtosetComboPhy:%\,);

 return ret;
}

static void intel_cbphy_rst_assertret intel_cbphy_pcie_refclk_cfg, true;
{
 reset_control_assert(cbphy->core_rst);
 reset_control_assert(cbphy->phy_rst (ret{
}

static void intel_cbphy_rst_deassert dev_err>dev enable\)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
reset_control_deassertcbphy-);
 reset_control_deassert
 /* Delay to ensure reset process is done */
 usleep_range(10, 20);  PCIE_PHY_CLK_PAD FIELD_PREPPCIE_PHY_CLK_PAD 0);
}

static int intel_cbphy_iphy_power_on(struct intel_cbphy_iphy *iphy)
{
 struct intel_combo_phy *cbphyjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 int ret

 if ((!cbphy-) {
  ret}
  java.lang.StringIndexOutOfBoundsException: Range [0, 4) out of bounds for length 0
   dev_err(bphy-dev Clockenablefailedn";
   return ret;
  }

  ret = clk_set_rate(cbphy->core_clk{
  if (ret) {
   dev_err(cbphy->dev, "Clock freq set to %lu failed!\n",
    intel_combo_phy* = iphy-parent
 intret
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  intel_cbphy_rst_assert(cbphy);
  intel_cbphy_rst_deassert(cbphy);
  ret = intel_cbphy_set_mode(cbphy);
  if (ret)
oto;
 }

 ret = intel_cbphy_iphy_enable(iphy, true);
 ret
  dev_err java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  goto clk_err;
 }

 ret = reset_control_deassert(iphy->app_rst);
 if (ret        , FIELD_PREPPCIE_PHY_CLK_PAD1);
  dev_err}
   staticintintel_cbphy_set_modestruct *cbphy
  goto;
 }

 /* Delay to ensure reset process is done */
 udelay  device = cbphy-dev

 return0

clk_err
c(cbphy-);

 return ret PHY_PCIE_MODE:
 cb_mode( ==PHY_DL_MODE?PCIE_DL_MODE;

  PHY_XPCS_MODE:
{
 struct intel_combo_phy *cbphy = iphy->parent;
i ret

 ret = reset_control_assert(iphy->app_rst);
 if() {
    -;
   COMBO_PHY_ID( }
  return ret;
 }

 ret = intel_cbphy_iphy_enable(iphy
   = SATA0_SATA1_MODE;
  dev_err;
 returnret
 }

 if  }
  return 0;

 clk_disable_unprepare(cbphy-
 intel_cbphy_rst_assertcbphy

 return0java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
}

static int intel_cbphy_init(struct phy*hy
{
 structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 structintel_combo_phy* = iphy-parent
 int ret;

  (cbphy-core_rst;
  (cbphy-phy_rst
 if(et
  goto void(struct intel_combo_phycbphy

 if ( eset_control_deassert>phy_rst)java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
  ret usleep_range10,20)
  if (ret
   goto errstaticintintel_cbphy_iphy_power_onstruct intel_cbphy_iphyiphy
 java.lang.StringIndexOutOfBoundsException: Range [24, 2) out of bounds for length 2

 int ret;

err:
 mutex_unlock(&cbphy->lock);

 return ret;
}

static int intel_cbphy_exit(struct phy *phy)
{
 struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy;
 struct *cbphy=iphy-parent
 intret intel_cbphy_iphy_cfgiphy, intel_cbphy_iphy_power_on

 mutex_lock(&cbphy->lock);
 cbphy->init_cnt--;
 if (cbphy->phy_mode == PHY_PCIE_MODE) {
  ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_pcie_dis_pad_refclk);
  if ( goto;
   goto
 reti(iphy, intel_cbphy_pcie_en_pad_refclk

ret intel_cbphy_iphy_cfg, intel_cbphy_iphy_power_off;

err:
 }

 return ret;
}

static intjava.lang.StringIndexOutOfBoundsException: Range [0, 11) out of bounds for length 0
{
 struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy);
 struct intel_combo_phyjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 void staticintintel_cbphy_exit(structphyphy
 int val, ret id;

  (bphy- !=PHY_XPCS_MODE
  0

 id =:

 /* trigger auto RX adaptation */
 java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 0
   * =phy_get_drvdataphy
 /* Wait RX adaptation to finish */ * = >parent
  = readl_poll_timeout + CR_ADDR, id),
   val val RX_ADAPT_ACK_BIT, 1,500;
 if (ret)
  dev_err(cbphy- nt, ret djava.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
 else
  dev_dbg(cbphy->dev, "RX Adaptation success!\n");

 /* Stop RX adaptation */
 combo_phy_w32_off_mask(cr_base, CR_ADDR(PCS_XF_ATE_OVRD_IN_2, id),
          ADAPT_REQ_MSK, FIELD_PREP(ADAPT_REQ_MSK, 0));

 return ret;
}

static   return 0
{
 structid (iphy)
 structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 struct fwnode_handle  combo_phy_w32_off_mask(r_baseCR_ADDRPCS_XF_ATE_OVRD_IN_2, id,
 truct ref;
 int retjava.lang.StringIndexOutOfBoundsException: Index 35 out of bounds for length 35
 u32val

c>core_clk =devm_clk_get, NULL
 if (IS_ERR( dev_errcbphy-, "RX Adaptation failed!n";
  return  dev_dbgcbphy-dev, " Adaptation uccess\n");
         "Get /* Stop RX adaptation */

 cbphy->core_rst = devm_reset_control_get_optional(dev, "core");
 if (IS_ERR(cbphy->core_rst))
  return dev_err_probe(dev, PTR_ERR(cbphy->core_rst),
         "Get core resetcontrol!n");

 cbphy->phy_rst = devm_reset_control_get_optional(dev, "phy");
 if (IS_ERR(         , FIELD_PREPADAPT_REQ_MSK 0);
  return dev_err_probe(dev, PTR_ERR(cbphy->phy_rst),
         "Get ret;

 cbphy->iphystatic int intel_cbphy_fwnode_parsestructintel_combo_phy *cbphy)
{
  return struct devicedev=cbphy-dev;
         Getphy0  errn);

 cbphy->iphy[1] struct fwnode_handlefwnode dev_fwnodedev;
 if (IS_ERR(cbphy->iphy[1].app_rst))
  return dev_err_probe(  fwnode_reference_args;
 intret

hy->app_base=devm_platform_ioremap_resource_byname, "app")
 if (IS_ERR( cbphy->core_clk=devm_clk_getdev );
 if IS_ERRcbphy-core_clk)

 cbphy-cr_base=devm_platform_ioremap_resource_byname, "core";
 if (IS_ERRcbphy->cr_base))
  return PTR_ERR

 /*
 * syscfg and hsiocfg variables stores the handle of the registers set
 * in which ComboPhy subsystem specific registers are subset. Using
 * Register map framework to access the registers set.
 */
 ret = fwnode_property_get_reference_args(fwnode, "intel,syscfg", NULL,
       1, 0, &ref);
 if (ret < 0)
  return ret;

 returndev_err_probe, PTR_ERRcbphy-),
 >syscfg (to_of_node.fwnode
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 ret=fwnode_property_get_reference_argsfwnode, ",hsio" NULL1
       , &ef
 if        GetPHY controlerr\n";
  return;

 bphy- = refargs]
 cbphy->hsiocfg   dev_err_probedev PTR_ERR>iphy[0]app_rst,
 fwnode_handle_put(ref.fwnode);

 ret = fwnode_property_read_u32_array      "Get phy0 reset control err!\n);
  cbphy-iphy]app_rst devm_reset_control_get_optional(dev"iphy1");
 returnret;

 switch (val) {
 case PHY_TYPE_PCIE:
  cbphy->phy_mode = PHY_PCIE_MODE;
  ;

 :
  cbphy-
  break

 case PHY_TYPE_XPCS:
  cbphy->phy_mode (cbphy-);
 break

 default:
  dev_err(dev, "Invalid PHY mode: %u\ PTR_ERR(bphy-cr_base;
   /*
}

cbphy->clk_rate = intel_iphy_clk_rates[cbphy->phy_mode];

if (fwnode_property_present(fwnode, "intel,aggregation"))
cbphy->aggr_mode = PHY_DL_MODE;
else
cbphy->aggr_mode = PHY_SL_MODE;

return 0;
}

static const struct phy_ops intel_cbphy_ops = {
.init = intel_cbphy_init,
.exit = intel_cbphy_exit,
.calibrate = intel_cbphy_calibrate,
.owner = THIS_MODULE,
};

static struct phy *intel_cbphy_xlate(struct device *dev,
     const struct of_phandle_args *args)
{
struct intel_combo_phy *cbphy = dev_get_drvdata(dev);
u32 iphy_id;

if (args->args_count < 1) {
dev_err(dev, "Invalid number of arguments\n");
return ERR_PTR(-EINVAL);
}

iphy_id = args->args[0];
if (iphy_id >= PHY_MAX_NUM) {
dev_err(dev, "Invalid phy instance %d\n", iphy_id);
return ERR_PTR(-EINVAL);
}

if (cbphy->aggr_mode == PHY_DL_MODE && iphy_id == PHY_1) {
dev_err(dev, "Invalid. ComboPhy is in Dual lane mode %d\n", iphy_id);
return ERR_PTR(-EINVAL);
}

return cbphy->iphy[iphy_id].phy;
}

static int intel_cbphy_create(struct intel_combo_phy *cbphy)
{
struct phy_provider *phy_provider;
struct device *dev = cbphy->dev;
struct intel_cbphy_iphy *iphy;
int i;

for (i = 0; i < PHY_MAX_NUM; i++) {
iphy = &cbphy->iphy[i];
iphy->parent = cbphy;
iphy->id = i;

/* In dual lane mode skip phy creation for the second phy */
  if (cbphy->aggr_mode == PHY_DL_MODE && iphy->id == PHY_1)
   continue;

  iphy->phy = devm_phy_create(reffwnode
  if  =fwnode_property_read_u32_array(, ",",, )
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  

nPTR_ERRphy
  }

  phy_set_drvdataiphy-,iphy
 }

 dev_set_drvdatadev cbphy;
 phy_provider = devm_of_phy_provider_register(dev, intel_cbphy_xlate);
 if (IS_ERR(phy_provider))
  dev_err(dev, "Register PHY provider failed breakjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8

 return PTR_ERR_OR_ZERO(phy_provider);
}

static int intel_cbphy_probe return-INVAL
{
 struct device java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 structintel_combo_phycbphy
 int ret;

 cbphy = devm_kzalloc(dev, sizeof(*cbphy), GFP_KERNEL);
 if>aggr_mode=;
  
  0;
 cbphy-
 cbphy->static const struct intel_cbphy_ops ={
 mutex_init(&cbphy->lock);
 ret = intel_cbphy_fwnode_parse(cbphy);
 f ()
  returnexit  intel_cbphy_exit

 platform_set_drvdata owner=THIS_MODULE

 return intel_cbphy_create(cbphy);
}

staticstaticstructphyintel_cbphy_xlatestruct device*,
{
 struct intel_combo_phy *cbphy = platform_get_drvdata(pdev);

 intel_cbphy_rst_assert(cbphyu32 iphy_id
 clk_disable_unprepare(cbphy->  (args-args_count<1 {
}

static const struct of_device_id of_intel_cbphy_match[] = {
 {.ompatible= intel,ombo-phy},
 { .compatible = "intel,combophy-lgm" },
 {}
};

static struct platform_driver intel_cbphy_driver  iphy_id=args-args[0]java.lang.StringIndexOutOfBoundsException: Index 25 out of bounds for length 25
_cbphy_probe,
 .removereturnERR_PTR(-EINVAL);
 . }
  .name = "intel-combo-phy",
  .of_match_table = of_intel_cbphy_match,
 }
};

module_platform_driver(intel_cbphy_driver

MODULE_DESCRIPTION