staticint ecc_size;
module_param(ecc_size, int, 0400);
MODULE_PARM_DESC(ecc_size, "ECC parity data size in bytes. A positive value enables ECC for the ramoops region.");
staticconststruct dmi_system_id chromeos_pstore_dmi_table[] __initconst = {
{ /* * Today all Chromebooks/boxes ship with Google_* as version and * coreboot as bios vendor. No other systems with this * combination are known to date.
*/
.matches = {
DMI_MATCH(DMI_BIOS_VENDOR, "coreboot"),
DMI_MATCH(DMI_BIOS_VERSION, "Google_"),
},
},
{ /* x86-alex, the first Samsung Chromebook. */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
DMI_MATCH(DMI_PRODUCT_NAME, "Alex"),
},
},
{ /* x86-mario, the Cr-48 pilot device from Google. */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "IEC"),
DMI_MATCH(DMI_PRODUCT_NAME, "Mario"),
},
},
{ /* x86-zgb, the first Acer Chromebook. */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
},
},
{ }
};
MODULE_DEVICE_TABLE(dmi, chromeos_pstore_dmi_table);
/* * On x86 chromebooks/boxes, the firmware will keep the legacy VGA memory * range untouched across reboots, so we use that to store our pstore * contents for panic logs, etc.
*/ staticstruct ramoops_platform_data chromeos_ramoops_data = {
.mem_size = 0x100000,
.mem_address = 0xf00000,
.record_size = 0x40000,
.console_size = 0x20000,
.ftrace_size = 0x20000,
.pmsg_size = 0x20000,
.max_reason = KMSG_DUMP_OOPS,
};
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