/* Wait for bitmask in a register to get set or cleared. * timeout is in units of ten-microseconds.
*/ staticint bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask, int timeout)
{ int i;
u32 val;
for (i = 0; i < timeout; i++) {
val = bcma_read32(dev, reg); if ((val & bitmask) == bitmask) return 0;
udelay(10);
}
return -ETIMEDOUT;
}
staticvoid bcma_hcd_4716wa(struct bcma_device *dev)
{ #ifdef CONFIG_BCMA_DRIVER_MIPS /* Work around for 4716 failures. */ if (dev->bus->chipinfo.id == 0x4716) {
u32 tmp;
tmp = bcma_cpu_clock(&dev->bus->drv_mips); if (tmp >= 480000000)
tmp = 0x1846b; /* set CDR to 0x11(fast) */ elseif (tmp == 453000000)
tmp = 0x1046b; /* set CDR to 0x10(slow) */ else
tmp = 0;
/* Change Shim mdio control reg to fix host not acking at * high frequencies
*/ if (tmp) {
bcma_write32(dev, 0x524, 0x1); /* write sel to enable */
udelay(500);
/* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ staticvoid bcma_hcd_init_chip_mips(struct bcma_device *dev)
{
u32 tmp;
/* * USB 2.0 special considerations: * * 1. Since the core supports both OHCI and EHCI functions, it must * only be reset once. * * 2. In addition to the standard SI reset sequence, the Host Control * Register must be programmed to bring the USB core and various * phy components out of reset.
*/ if (!bcma_core_is_enabled(dev)) {
bcma_core_enable(dev, 0);
mdelay(10); if (dev->id.rev >= 5) { /* Enable Misc PLL */
tmp = bcma_read32(dev, 0x1e0);
tmp |= 0x100;
bcma_write32(dev, 0x1e0, tmp); if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100))
printk(KERN_EMERG "Failed to enable misc PPL!\n");
/* Take out of resets */
bcma_write32(dev, 0x200, 0x4ff);
udelay(25);
bcma_write32(dev, 0x200, 0x6ff);
udelay(25);
/* Make sure digital and AFE are locked in USB PHY */
bcma_write32(dev, 0x524, 0x6b);
udelay(50);
tmp = bcma_read32(dev, 0x524);
udelay(50);
bcma_write32(dev, 0x524, 0xab);
udelay(50);
tmp = bcma_read32(dev, 0x524);
udelay(50);
bcma_write32(dev, 0x524, 0x2b);
udelay(50);
tmp = bcma_read32(dev, 0x524);
udelay(50);
bcma_write32(dev, 0x524, 0x10ab);
udelay(50);
tmp = bcma_read32(dev, 0x524);
/* Take USB and HSIC out of non-driving modes */
bcma_write32(dev, 0x510, 0);
} else {
bcma_write32(dev, 0x200, 0x7ff);
udelay(1);
}
bcma_hcd_4716wa(dev);
}
}
/* * bcma_hcd_usb20_old_arm_init - Initialize old USB 2.0 controller on ARM * * Old USB 2.0 core is identified as BCMA_CORE_USB20_HOST and was introduced * long before Northstar devices. It seems some cheaper chipsets like BCM53573 * still use it. * Initialization of this old core differs between MIPS and ARM.
*/ staticint bcma_hcd_usb20_old_arm_init(struct bcma_hcd_device *usb_dev)
{ struct bcma_device *core = usb_dev->core; struct device *dev = &core->dev; struct bcma_device *pmu_core;
usleep_range(10000, 20000); if (core->id.rev < 5) return 0;
pmu_core = bcma_find_core(core->bus, BCMA_CORE_PMU); if (!pmu_core) {
dev_err(dev, "Could not find PMU core\n"); return -ENOENT;
}
/* Take USB core out of reset */
bcma_awrite32(core, BCMA_IOCTL, BCMA_IOCTL_CLK | BCMA_IOCTL_FGC);
usleep_range(100, 200);
bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
usleep_range(100, 200);
bcma_awrite32(core, BCMA_RESET_CTL, 0);
usleep_range(100, 200);
bcma_awrite32(core, BCMA_IOCTL, BCMA_IOCTL_CLK);
usleep_range(100, 200);
/* Set packet buffer OUT threshold */
val = bcma_read32(dev, 0x94);
val &= 0xffff;
val |= 0x80 << 16;
bcma_write32(dev, 0x94, val);
/* Enable break memory transfer */
val = bcma_read32(dev, 0x9c);
val |= 1;
bcma_write32(dev, 0x9c, val);
/* * Broadcom initializes PHY and then waits to ensure HC is ready to be * configured. In our case the order is reversed. We just initialized * controller and we let HCD initialize PHY, so let's wait (sleep) now.
*/
usleep_range(1000, 2000);
}
ret = platform_device_add_resources(hci_dev, hci_res,
ARRAY_SIZE(hci_res)); if (ret) goto err_alloc; if (data)
ret = platform_device_add_data(hci_dev, data, size); if (ret) goto err_alloc;
ret = platform_device_add(hci_dev); if (ret) goto err_alloc;
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