/** * struct llcc_slice_desc - Cache slice descriptor * @slice_id: llcc slice id * @slice_size: Size allocated for the llcc slice
*/ struct llcc_slice_desc {
u32 slice_id;
size_t slice_size;
};
/** * struct llcc_edac_reg_data - llcc edac registers data for each error type * @name: Name of the error * @reg_cnt: Number of registers * @count_mask: Mask value to get the error count * @ways_mask: Mask value to get the error ways * @count_shift: Shift value to get the error count * @ways_shift: Shift value to get the error ways
*/ struct llcc_edac_reg_data { char *name;
u32 reg_cnt;
u32 count_mask;
u32 ways_mask;
u8 count_shift;
u8 ways_shift;
};
/** * struct llcc_drv_data - Data associated with the llcc driver * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast OR offset * @bcast_and_regmap: regmap associated with llcc broadcast AND offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers * @lock: mutex associated with each slice * @cfg_size: size of the config data table * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids * @ecc_irq: interrupt for llcc cache error detection and reporting * @ecc_irq_configured: 'True' if firmware has already configured the irq propagation * @version: Indicates the LLCC version
*/ struct llcc_drv_data { struct regmap **regmaps; struct regmap *bcast_regmap; struct regmap *bcast_and_regmap; conststruct llcc_slice_config *cfg; conststruct llcc_edac_reg_offset *edac_reg_offset; struct mutex lock;
u32 cfg_size;
u32 max_slices;
u32 num_banks; unsignedlong *bitmap; int ecc_irq; bool ecc_irq_configured;
u32 version;
};
#if IS_ENABLED(CONFIG_QCOM_LLCC) /** * llcc_slice_getd - get llcc slice descriptor * @uid: usecase_id of the client
*/ struct llcc_slice_desc *llcc_slice_getd(u32 uid);
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