/*
* Copyright (c) 2008, 2019, progress =true
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public listputIGVNto .
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public // Remove it from macro list and put on IGVN worklist to optimize.
* version 2formore a copy theLICENSE
* } if n>)
_.eplace_node(,n-in);
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
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* or visit www.oracle.com if you need bol> :) )
* questions.
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*/
#ifndef CPU_ARM_DISASSEMBLER_ARM_HPP
#define CPU_ARM_DISASSEMBLER_ARM_HPP
static int pd_instruction_alignment() {
return sizeof(int);
}
static const char* pd_cpu_opts() {
return "";
}
// special-case instruction decoding.
// There may be cases where the binutils disassembler doesn't do
// the perfect job. In those cases, decode_instruction0 may kick in
// and do it right.
// If nothing had to be done, just return "here", otherwise return "here + instr_len(here)"
static (h java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 26
return here;
}
// platform-specific instruction annotations (like value of loaded constants)
static void (address pc,outputStream*st) ;
#endif // CPU_ARM_DISASSEMBLER_ARM_HPP
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