/* * Now for every possible bit set, work through them and call * the appropriate interrupt handler.
*/ while (pld) {
i = ffz(~pld);
pld &= pld - 1; /* clear least bit set */ if (i < 16) {
isa_device_interrupt(vector);
} else {
handle_irq(i);
}
}
}
staticvoid __init
mikasa_init_irq(void)
{ long i;
if (alpha_using_srm)
alpha_mv.device_interrupt = srm_device_interrupt;
mikasa_update_irq_hw(0);
for (i = 16; i < 32; ++i) {
irq_set_chip_and_handler(i, &mikasa_irq_type,
handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
init_i8259a_irqs();
common_init_isa_dma();
}
/* * PCI Fixup configuration. * * Summary @ 0x536: * Bit Meaning * 0 Interrupt Line A from slot 0 * 1 Interrupt Line B from slot 0 * 2 Interrupt Line C from slot 0 * 3 Interrupt Line D from slot 0 * 4 Interrupt Line A from slot 1 * 5 Interrupt line B from slot 1 * 6 Interrupt Line C from slot 1 * 7 Interrupt Line D from slot 1 * 8 Interrupt Line A from slot 2 * 9 Interrupt Line B from slot 2 *10 Interrupt Line C from slot 2 *11 Interrupt Line D from slot 2 *12 NCR 810 SCSI *13 Power Supply Fail *14 Temperature Warn *15 Reserved * * The device to slot mapping looks like: * * Slot Device * 6 NCR SCSI controller * 7 Intel PCI-EISA bridge chip * 11 PCI on board slot 0 * 12 PCI on board slot 1 * 13 PCI on board slot 2 * * * This two layered interrupt approach means that we allocate IRQ 16 and * above for PCI interrupts. The IRQ relates to which bit the interrupt * comes in on. This makes interrupt processing much easier.
*/
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