| Quellcodebibliothek Statistik Leitseite products/sources/formale Sprachen/C/Linux/arch/arm64/boot/dts/freescale/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 53 kB |
|
Quelle imx8mq.dtsi Sprache: unbekannt |
|
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* * Copyright 2017 NXP * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> */ #include <dt-bindings/clock/imx8mq-clock.h> #include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> #include "dt-bindings/input/input.h" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/interconnect/imx8mq.h> #include "imx8mq-pinfunc.h" / { interrupt-parent = <&gpc>; #address-cells = <2>; #size-cells = <2>; aliases { ethernet0 = &fec1; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; }; ckil: clock-ckil { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "ckil"; }; osc_25m: clock-osc-25m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; clock-output-names = "osc_25m"; }; osc_27m: clock-osc-27m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; clock-output-names = "osc_27m"; }; hdmi_phy_27m: clock-hdmi-phy-27m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; clock-output-names = "hdmi_phy_27m"; }; clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext1"; }; clk_ext2: clock-ext2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext2"; }; clk_ext3: clock-ext3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext3"; }; clk_ext4: clock-ext4 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <133000000>; clock-output-names = "clk_ext4"; }; cpus { #address-cells = <1>; #size-cells = <0>; A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; }; A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; }; }; a53_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <900000>; /* Industrial only */ opp-supported-hw = <0xf>, <0x4>; clock-latency-ns = <150000>; opp-suspend; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <900000>; /* Consumer only */ opp-supported-hw = <0xe>, <0x3>; clock-latency-ns = <150000>; opp-suspend; }; opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; opp-microvolt = <1000000>; opp-supported-hw = <0xc>, <0x4>; clock-latency-ns = <150000>; opp-suspend; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <1000000>; opp-supported-hw = <0x8>, <0x3>; clock-latency-ns = <150000>; opp-suspend; }; }; funnel { /* * non-configurable funnel don't show up on the AMBA * bus. As such no need to add "arm,primecell". */ compatible = "arm,coresight-static-funnel"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; ca_funnel_in_port0: endpoint { remote-endpoint = <&etm0_out_port>; }; }; port@1 { reg = <1>; ca_funnel_in_port1: endpoint { remote-endpoint = <&etm1_out_port>; }; }; port@2 { reg = <2>; ca_funnel_in_port2: endpoint { remote-endpoint = <&etm2_out_port>; }; }; port@3 { reg = <3>; ca_funnel_in_port3: endpoint { remote-endpoint = <&etm3_out_port>; }; }; }; out-ports { port { ca_funnel_out_port0: endpoint { remote-endpoint = <&hugo_funnel_in_port0>; }; }; }; }; pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tmu 0>; trips { cpu_alert: cpu-alert { temperature = <80000>; hysteresis = <2000>; type = "passive"; }; cpu-crit { temperature = <90000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_alert>; cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; gpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tmu 1>; trips { gpu_alert: gpu-alert { temperature = <80000>; hysteresis = <2000>; type = "passive"; }; gpu-crit { temperature = <90000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpu_alert>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; vpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tmu 2>; trips { vpu-crit { temperature = <90000>; hysteresis = <2000>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ interrupt-parent = <&gic>; arm,no-tick-in-suspend; }; soc: soc@0 { compatible = "fsl,imx8mq-soc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; nvmem-cells = <&imx8mq_uid>; nvmem-cell-names = "soc_unique_id"; etm0: etm@28440000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x28440000 0x1000>; cpu = <&A53_0>; clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; clock-names = "apb_pclk"; out-ports { port { etm0_out_port: endpoint { remote-endpoint = <&ca_funnel_in_port0>; }; }; }; }; etm1: etm@28540000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x28540000 0x1000>; cpu = <&A53_1>; clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; clock-names = "apb_pclk"; out-ports { port { etm1_out_port: endpoint { remote-endpoint = <&ca_funnel_in_port1>; }; }; }; }; etm2: etm@28640000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x28640000 0x1000>; cpu = <&A53_2>; clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; clock-names = "apb_pclk"; out-ports { port { etm2_out_port: endpoint { remote-endpoint = <&ca_funnel_in_port2>; }; }; }; }; etm3: etm@28740000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x28740000 0x1000>; cpu = <&A53_3>; clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; clock-names = "apb_pclk"; out-ports { port { etm3_out_port: endpoint { remote-endpoint = <&ca_funnel_in_port3>; }; }; }; }; funnel@28c03000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x28c03000 0x1000>; clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; clock-names = "apb_pclk"; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; hugo_funnel_in_port0: endpoint { remote-endpoint = <&ca_funnel_out_port0>; }; }; port@1 { reg = <1>; hugo_funnel_in_port1: endpoint { /* M4 input */ }; }; /* the other input ports are not connect to anything */ }; out-ports { port { hugo_funnel_out_port0: endpoint { remote-endpoint = <&etf_in_port>; }; }; }; }; etf@28c04000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x28c04000 0x1000>; clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; clock-names = "apb_pclk"; in-ports { port { etf_in_port: endpoint { remote-endpoint = <&hugo_funnel_out_port0>; }; }; }; out-ports { port { etf_out_port: endpoint { remote-endpoint = <&etr_in_port>; }; }; }; }; etr@28c06000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x28c06000 0x1000>; clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; clock-names = "apb_pclk"; in-ports { port { etr_in_port: endpoint { remote-endpoint = <&etf_out_port>; }; }; }; }; aips1: bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; sai1: sai@30010000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; sai6: sai@30030000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, <&clk IMX8MQ_CLK_SAI6_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; sai5: sai@30040000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; reg = <0x30040000 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; sai4: sai@30050000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; gpio1: gpio@30200000 { compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 10 30>; }; gpio2: gpio@30210000 { compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; reg = <0x30210000 0x10000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 40 21>; }; gpio3: gpio@30220000 { compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; reg = <0x30220000 0x10000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 61 26>; }; gpio4: gpio@30230000 { compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; reg = <0x30230000 0x10000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 87 32>; }; gpio5: gpio@30240000 { compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; reg = <0x30240000 0x10000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&iomuxc 0 119 30>; }; tmu: tmu@30260000 { compatible = "fsl,imx8mq-tmu"; reg = <0x30260000 0x10000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; little-endian; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; fsl,tmu-calibration = <0x00000000 0x00000023>, <0x00000001 0x00000029>, <0x00000002 0x0000002f>, <0x00000003 0x00000035>, <0x00000004 0x0000003d>, <0x00000005 0x00000043>, <0x00000006 0x0000004b>, <0x00000007 0x00000051>, <0x00000008 0x00000057>, <0x00000009 0x0000005f>, <0x0000000a 0x00000067>, <0x0000000b 0x0000006f>, <0x00010000 0x0000001b>, <0x00010001 0x00000023>, <0x00010002 0x0000002b>, <0x00010003 0x00000033>, <0x00010004 0x0000003b>, <0x00010005 0x00000043>, <0x00010006 0x0000004b>, <0x00010007 0x00000055>, <0x00010008 0x0000005d>, <0x00010009 0x00000067>, <0x0001000a 0x00000070>, <0x00020000 0x00000017>, <0x00020001 0x00000023>, <0x00020002 0x0000002d>, <0x00020003 0x00000037>, <0x00020004 0x00000041>, <0x00020005 0x0000004b>, <0x00020006 0x00000057>, <0x00020007 0x00000063>, <0x00020008 0x0000006f>, <0x00030000 0x00000015>, <0x00030001 0x00000021>, <0x00030002 0x0000002d>, <0x00030003 0x00000039>, <0x00030004 0x00000045>, <0x00030005 0x00000053>, <0x00030006 0x0000005f>, <0x00030007 0x00000071>; #thermal-sensor-cells = <1>; }; wdog1: watchdog@30280000 { compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; status = "disabled"; }; wdog2: watchdog@30290000 { compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; reg = <0x30290000 0x10000>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; status = "disabled"; }; wdog3: watchdog@302a0000 { compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; reg = <0x302a0000 0x10000>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; status = "disabled"; }; sdma2: dma-controller@302c0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x302c0000 0x10000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, <&clk IMX8MQ_CLK_SDMA2_ROOT>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; }; lcdif: lcd-controller@30320000 { compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif"; reg = <0x30320000 0x10000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>; clock-names = "pix", "axi", "disp_axi"; assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_LCDIF_PIXEL>, <&clk IMX8MQ_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, <&clk IMX8MQ_VIDEO_PLL1>, <&clk IMX8MQ_VIDEO_PLL1_OUT>; assigned-clock-rates = <0>, <0>, <0>, <594000000>; status = "disabled"; port { lcdif_mipi_dsi: endpoint { remote-endpoint = <&mipi_dsi_lcdif_in>; }; }; }; iomuxc: pinctrl@30330000 { compatible = "fsl,imx8mq-iomuxc"; reg = <0x30330000 0x10000>; }; iomuxc_gpr: syscon@30340000 { compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd"; reg = <0x30340000 0x10000>; mux: mux-controller { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ }; }; ocotp: efuse@30350000 { compatible = "fsl,imx8mq-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; #address-cells = <1>; #size-cells = <1>; /* * The register address below maps to the MX8M * Fusemap Description Table entries this way. * Assuming * reg = <ADDR SIZE>; * then * Fuse Address = (ADDR * 4) + 0x400 * Note that if SIZE is greater than 4, then * each subsequent fuse is located at offset * +0x10 in Fusemap Description Table (e.g. * reg = <0x4 0x8> describes fuses 0x410 and * 0x420). */ imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; anatop: clock-controller@30360000 { compatible = "fsl,imx8mq-anatop"; reg = <0x30360000 0x10000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; }; snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; regmap = <&snvs>; offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; clock-names = "snvs-rtc"; }; snvs_pwrkey: snvs-powerkey { compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; clock-names = "snvs-pwrkey"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; }; }; clk: clock-controller@30380000 { compatible = "fsl,imx8mq-ccm"; reg = <0x30380000 0x10000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_AUDIO_AHB>, <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; assigned-clock-rates = <0>, <0>, <800000000>, <0>, <0>, <0>, <786432000>, <722534400>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_ARM_PLL_OUT>, <0>, <&clk IMX8MQ_SYS2_PLL_500M>, <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; }; src: reset-controller@30390000 { compatible = "fsl,imx8mq-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; gpc: gpc@303a0000 { compatible = "fsl,imx8mq-gpc"; reg = <0x303a0000 0x10000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; interrupt-controller; #interrupt-cells = <3>; pgc { #address-cells = <1>; #size-cells = <0>; pgc_mipi: power-domain@0 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_MIPI>; }; /* * As per comment in ATF source code: * * PCIE1 and PCIE2 share the * same reset signal, if we * power down PCIE2, PCIE1 * will be held in reset too. * * So instead of creating two * separate power domains for * PCIE1 and PCIE2 we create a * link between both and use * it as a shared PCIE power * domain. */ pgc_pcie: power-domain@1 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_PCIE1>; power-domains = <&pgc_pcie2>; }; pgc_otg1: power-domain@2 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; }; pgc_otg2: power-domain@3 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; }; pgc_ddr1: power-domain@4 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_DDR1>; }; pgc_gpu: power-domain@5 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_GPU>; clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, <&clk IMX8MQ_CLK_GPU_AXI>, <&clk IMX8MQ_CLK_GPU_AHB>; }; pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_VPU>; clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>; assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>, <&clk IMX8MQ_VPU_PLL_BYPASS>; assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_VPU_PLL>; assigned-clock-rates = <600000000>, <300000000>, <800000000>, <0>; }; pgc_disp: power-domain@7 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_DISP>; }; pgc_mipi_csi1: power-domain@8 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; }; pgc_mipi_csi2: power-domain@9 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; }; pgc_pcie2: power-domain@a { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_PCIE2>; }; }; }; }; aips2: bus@30400000 { /* AIPS2 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30400000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; pwm1: pwm@30660000 { compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; reg = <0x30660000 0x10000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, <&clk IMX8MQ_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; #pwm-cells = <3>; status = "disabled"; }; pwm2: pwm@30670000 { compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; reg = <0x30670000 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, <&clk IMX8MQ_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; #pwm-cells = <3>; status = "disabled"; }; pwm3: pwm@30680000 { compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; reg = <0x30680000 0x10000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, <&clk IMX8MQ_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; #pwm-cells = <3>; status = "disabled"; }; pwm4: pwm@30690000 { compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; reg = <0x30690000 0x10000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, <&clk IMX8MQ_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; #pwm-cells = <3>; status = "disabled"; }; system_counter: timer@306a0000 { compatible = "nxp,sysctr-timer"; reg = <0x306a0000 0x20000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc_25m>; clock-names = "per"; }; }; aips3: bus@30800000 { /* AIPS3 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30800000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x30800000 0x30800000 0x400000>, <0x08000000 0x08000000 0x10000000>; spdif1: spdif@30810000 { compatible = "fsl,imx35-spdif"; reg = <0x30810000 0x10000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ <&clk IMX8MQ_CLK_DUMMY>; /* spba */ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba"; dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; dma-names = "rx", "tx"; status = "disabled"; }; ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; reg = <0x30820000 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, <&clk IMX8MQ_CLK_ECSPI1_ROOT>; clock-names = "ipg", "per"; dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; ecspi2: spi@30830000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; reg = <0x30830000 0x10000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, <&clk IMX8MQ_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; ecspi3: spi@30840000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; reg = <0x30840000 0x10000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, <&clk IMX8MQ_CLK_ECSPI3_ROOT>; clock-names = "ipg", "per"; dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; uart1: serial@30860000 { compatible = "fsl,imx8mq-uart", "fsl,imx6q-uart"; reg = <0x30860000 0x10000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, <&clk IMX8MQ_CLK_UART1_ROOT>; clock-names = "ipg", "per"; dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; dma-names = "rx", "tx"; status = "disabled"; }; uart3: serial@30880000 { compatible = "fsl,imx8mq-uart", "fsl,imx6q-uart"; reg = <0x30880000 0x10000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, <&clk IMX8MQ_CLK_UART3_ROOT>; clock-names = "ipg", "per"; dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; dma-names = "rx", "tx"; status = "disabled"; }; uart2: serial@30890000 { compatible = "fsl,imx8mq-uart", "fsl,imx6q-uart"; reg = <0x30890000 0x10000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, <&clk IMX8MQ_CLK_UART2_ROOT>; clock-names = "ipg", "per"; dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; dma-names = "rx", "tx"; status = "disabled"; }; spdif2: spdif@308a0000 { compatible = "fsl,imx35-spdif"; reg = <0x308a0000 0x10000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ <&clk IMX8MQ_CLK_DUMMY>; /* spba */ clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba"; dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; dma-names = "rx", "tx"; status = "disabled"; }; sai2: sai@308b0000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; reg = <0x308b0000 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, <&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; sai3: sai@308c0000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; reg = <0x308c0000 0x10000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; dma-names = "rx", "tx"; status = "disabled"; }; crypto: crypto@30900000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; reg = <0x30900000 0x40000>; ranges = <0 0x30900000 0x40000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_IPG_ROOT>; clock-names = "aclk", "ipg"; sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; }; sec_jr2: jr@3000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x3000 0x1000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; }; }; mipi_dsi: dsi@30a00000 { compatible = "fsl,imx8mq-nwl-dsi"; reg = <0x30a00000 0x300>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk IMX8MQ_CLK_DSI_CORE>, <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>, <&clk IMX8MQ_CLK_DSI_PHY_REF>, <&clk IMX8MQ_CLK_LCDIF_PIXEL>; clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_CORE>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, <&clk IMX8MQ_SYS1_PLL_266M>; assigned-clock-rates = <80000000>, <266000000>, <20000000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; mux-controls = <&mux 0>; power-domains = <&pgc_mipi>; phys = <&dphy>; phy-names = "dphy"; resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; reset-names = "byte", "dpi", "esc", "pclk"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_dsi_lcdif_in: endpoint@0 { reg = <0>; remote-endpoint = <&lcdif_mipi_dsi>; }; }; port@1 { reg = <1>; mipi_dsi_out: endpoint { }; }; }; }; dphy: dphy@30a00300 { compatible = "fsl,imx8mq-mipi-dphy"; reg = <0x30a00300 0x100>; clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; clock-names = "phy_ref"; assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_DSI_PHY_REF>, <&clk IMX8MQ_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, <&clk IMX8MQ_VIDEO_PLL1>, <&clk IMX8MQ_VIDEO_PLL1_OUT>; assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; #phy-cells = <0>; power-domains = <&pgc_mipi>; status = "disabled"; }; i2c1: i2c@30a20000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a20000 0x10000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c2: i2c@30a30000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a30000 0x10000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c3: i2c@30a40000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a40000 0x10000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; i2c4: i2c@30a50000 { compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; reg = <0x30a50000 0x10000>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart4: serial@30a60000 { compatible = "fsl,imx8mq-uart", "fsl,imx6q-uart"; reg = <0x30a60000 0x10000>; interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, <&clk IMX8MQ_CLK_UART4_ROOT>; clock-names = "ipg", "per"; dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; dma-names = "rx", "tx"; status = "disabled"; }; mipi_csi1: csi@30a70000 { compatible = "fsl,imx8mq-mipi-csi2"; reg = <0x30a70000 0x1000>; clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, <&clk IMX8MQ_CLK_CSI1_ESC>, <&clk IMX8MQ_CLK_CSI1_PHY_REF>; clock-names = "core", "esc", "ui"; assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, <&clk IMX8MQ_CLK_CSI1_PHY_REF>, <&clk IMX8MQ_CLK_CSI1_ESC>; assigned-clock-rates = <266000000>, <333000000>, <66000000>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, <&clk IMX8MQ_SYS2_PLL_1000M>, <&clk IMX8MQ_SYS1_PLL_800M>; power-domains = <&pgc_mipi_csi1>; resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; interconnect-names = "dram"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; csi1_mipi_ep: endpoint { remote-endpoint = <&csi1_ep>; }; }; }; }; csi1: csi@30a90000 { compatible = "fsl,imx8mq-csi"; reg = <0x30a90000 0x10000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; clock-names = "mclk"; status = "disabled"; port { csi1_ep: endpoint { remote-endpoint = <&csi1_mipi_ep>; }; }; }; mipi_csi2: csi@30b60000 { compatible = "fsl,imx8mq-mipi-csi2"; reg = <0x30b60000 0x1000>; clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, <&clk IMX8MQ_CLK_CSI2_ESC>, <&clk IMX8MQ_CLK_CSI2_PHY_REF>; clock-names = "core", "esc", "ui"; assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, <&clk IMX8MQ_CLK_CSI2_PHY_REF>, <&clk IMX8MQ_CLK_CSI2_ESC>; assigned-clock-rates = <266000000>, <333000000>, <66000000>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, <&clk IMX8MQ_SYS2_PLL_1000M>, <&clk IMX8MQ_SYS1_PLL_800M>; power-domains = <&pgc_mipi_csi2>; resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; interconnect-names = "dram"; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; csi2_mipi_ep: endpoint { remote-endpoint = <&csi2_ep>; }; }; }; }; csi2: csi@30b80000 { compatible = "fsl,imx8mq-csi"; reg = <0x30b80000 0x10000>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; clock-names = "mclk"; status = "disabled"; port { csi2_ep: endpoint { remote-endpoint = <&csi2_mipi_ep>; }; }; }; mu: mailbox@30aa0000 { compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; reg = <0x30aa0000 0x10000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_MU_ROOT>; #mbox-cells = <2>; }; usdhc1: mmc@30b40000 { compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; usdhc2: mmc@30b50000 { compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; status = "disabled"; }; qspi0: spi@30bb0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, <&clk IMX8MQ_CLK_QSPI_ROOT>; clock-names = "qspi_en", "qspi"; status = "disabled"; }; sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, <&clk IMX8MQ_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; }; fec1: ethernet@30be0000 { compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, <&clk IMX8MQ_CLK_ENET1_ROOT>, <&clk IMX8MQ_CLK_ENET_TIMER>, <&clk IMX8MQ_CLK_ENET_REF>, <&clk IMX8MQ_CLK_ENET_PHY_REF>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, <&clk IMX8MQ_CLK_ENET_TIMER>, <&clk IMX8MQ_CLK_ENET_REF>, <&clk IMX8MQ_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, <&clk IMX8MQ_SYS2_PLL_100M>, <&clk IMX8MQ_SYS2_PLL_125M>, <&clk IMX8MQ_SYS2_PLL_50M>; assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; nvmem-cells = <&fec_mac_address>; nvmem-cell-names = "mac-address"; fsl,stop-mode = <&iomuxc_gpr 0x10 3>; status = "disabled"; }; }; noc: interconnect@32700000 { compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; reg = <0x32700000 0x100000>; clocks = <&clk IMX8MQ_CLK_NOC>; fsl,ddrc = <&ddrc>; #interconnect-cells = <1>; operating-points-v2 = <&noc_opp_table>; noc_opp_table: opp-table { compatible = "operating-points-v2"; opp-133000000 { opp-hz = /bits/ 64 <133333333>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; }; aips4: bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; clock-names = "ipg"; fsl,channel = <0>; fsl,num-irqs = <64>; interrupt-controller; #interrupt-cells = <1>; }; }; gpu: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x40000>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, <&clk IMX8MQ_CLK_GPU_AXI>, <&clk IMX8MQ_CLK_GPU_AHB>; clock-names = "core", "shader", "bus", "reg"; #cooling-cells = <2>; assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI>, <&clk IMX8MQ_CLK_GPU_AHB>, <&clk IMX8MQ_GPU_PLL_BYPASS>; assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL>; assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>, <0>; power-domains = <&pgc_gpu>; }; usb_dwc3_0: usb@38100000 { compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; reg = <0x38100000 0x10000>; clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, <&clk IMX8MQ_CLK_USB_CORE_REF>, <&clk IMX8MQ_CLK_32K>; clock-names = "bus_early", "ref", "suspend"; assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, <&clk IMX8MQ_CLK_USB_CORE_REF>; assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, <&clk IMX8MQ_SYS1_PLL_100M>; assigned-clock-rates = <500000000>, <100000000>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg1>; snps,parkmode-disable-ss-quirk; status = "disabled"; }; usb3_phy0: usb-phy@381f0040 { compatible = "fsl,imx8mq-usb-phy"; reg = <0x381f0040 0x40>; clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; clock-names = "phy"; assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; assigned-clock-rates = <100000000>; #phy-cells = <0>; status = "disabled"; }; usb_dwc3_1: usb@38200000 { compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; reg = <0x38200000 0x10000>; clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, <&clk IMX8MQ_CLK_USB_CORE_REF>, <&clk IMX8MQ_CLK_32K>; clock-names = "bus_early", "ref", "suspend"; assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, <&clk IMX8MQ_CLK_USB_CORE_REF>; assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, <&clk IMX8MQ_SYS1_PLL_100M>; assigned-clock-rates = <500000000>, <100000000>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg2>; snps,parkmode-disable-ss-quirk; status = "disabled"; }; usb3_phy1: usb-phy@382f0040 { compatible = "fsl,imx8mq-usb-phy"; reg = <0x382f0040 0x40>; clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; clock-names = "phy"; assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; assigned-clock-rates = <100000000>; #phy-cells = <0>; status = "disabled"; }; vpu_g1: video-codec@38300000 { compatible = "nxp,imx8mq-vpu-g1"; reg = <0x38300000 0x10000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; }; vpu_g2: video-codec@38310000 { compatible = "nxp,imx8mq-vpu-g2"; reg = <0x38310000 0x10000>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; }; vpu_blk_ctrl: blk-ctrl@38320000 { compatible = "fsl,imx8mq-vpu-blk-ctrl"; reg = <0x38320000 0x100>; power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; power-domain-names = "bus", "g1", "g2"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>; clock-names = "g1", "g2"; #power-domain-cells = <1>; }; pcie0: pcie@33800000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <0>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, <&clk IMX8MQ_CLK_PCIE1_PHY>, <&clk IMX8MQ_CLK_PCIE1_PHY>, <&clk IMX8MQ_CLK_PCIE1_AUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, <&clk IMX8MQ_CLK_PCIE1_PHY>, <&clk IMX8MQ_CLK_PCIE1_AUX>; assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, <&clk IMX8MQ_SYS2_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_80M>; assigned-clock-rates = <250000000>, <100000000>, <10000000>; status = "disabled"; }; pcie0_ep: pcie-ep@33800000 { compatible = "fsl,imx8mq-pcie-ep"; reg = <0x33800000 0x100000>, <0x18000000 0x8000000>, <0x33900000 0x100000>, <0x33b00000 0x100000>; reg-names = "dbi", "addr_space", "dbi2", "atu"; num-lanes = <1>; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dma"; linux,pci-domain = <0>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, <&clk IMX8MQ_SYS2_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_80M>; assigned-clock-rates = <250000000>, <100000000>, <10000000>; num-ib-windows = <4>; num-ob-windows = <4>; fsl,max-link-speed = <2>; status = "disabled"; }; pcie1: pcie@33c00000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33c00000 0x400000>, <0x27f00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <2>; linux,pci-domain = <1>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, <&clk IMX8MQ_SYS2_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_80M>; assigned-clock-rates = <250000000>, <100000000>, <10000000>; status = "disabled"; }; pcie1_ep: pcie-ep@33c00000 { compatible = "fsl,imx8mq-pcie-ep"; reg = <0x33c00000 0x100000>, <0x20000000 0x8000000>, <0x33d00000 0x100000>, <0x33f00000 0x100000>; reg-names = "dbi", "addr_space", "dbi2", "atu"; num-lanes = <1>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dma"; fsl,max-link-speed = <2>; linux,pci-domain = <1>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; power-domains = <&pgc_pcie>; resets = <&src IMX8MQ_RESET_PCIEPHY2>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, <&clk IMX8MQ_SYS2_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_80M>; assigned-clock-rates = <250000000>, <100000000>, <10000000>; num-ib-windows = <4>; num-ob-windows = <4>; status = "disabled"; }; gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ <0x38880000 0xc0000>, /* GICR */ <0x31000000 0x2000>, /* GICC */ <0x31010000 0x2000>, /* GICV */ <0x31020000 0x2000>; /* GICH */ #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; }; ddrc: memory-controller@3d400000 { compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; reg = <0x3d400000 0x400000>; clock-names = "core", "pll", "alt", "apb"; clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, <&clk IMX8MQ_CLK_DRAM_APB>; status = "disabled"; }; ddr-pmu@3d800000 { compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; }; }; [ Dauer der Verarbeitung: 0.21 Sekunden (vorverarbeitet) ] |
2026-04-07